JP2011044654A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2011044654A
JP2011044654A JP2009193318A JP2009193318A JP2011044654A JP 2011044654 A JP2011044654 A JP 2011044654A JP 2009193318 A JP2009193318 A JP 2009193318A JP 2009193318 A JP2009193318 A JP 2009193318A JP 2011044654 A JP2011044654 A JP 2011044654A
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Japan
Prior art keywords
interposer
pad
chips
pads
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009193318A
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English (en)
Japanese (ja)
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JP2011044654A5 (enrdf_load_stackoverflow
Inventor
Akinori Shiraishi
晶紀 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
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Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009193318A priority Critical patent/JP2011044654A/ja
Publication of JP2011044654A publication Critical patent/JP2011044654A/ja
Publication of JP2011044654A5 publication Critical patent/JP2011044654A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
JP2009193318A 2009-08-24 2009-08-24 半導体装置 Pending JP2011044654A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009193318A JP2011044654A (ja) 2009-08-24 2009-08-24 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009193318A JP2011044654A (ja) 2009-08-24 2009-08-24 半導体装置

Publications (2)

Publication Number Publication Date
JP2011044654A true JP2011044654A (ja) 2011-03-03
JP2011044654A5 JP2011044654A5 (enrdf_load_stackoverflow) 2012-08-09

Family

ID=43831837

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JP2009193318A Pending JP2011044654A (ja) 2009-08-24 2009-08-24 半導体装置

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JP (1) JP2011044654A (enrdf_load_stackoverflow)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015220291A (ja) * 2014-05-15 2015-12-07 株式会社ソシオネクスト 半導体装置及びその製造方法
JP2016018876A (ja) * 2014-07-08 2016-02-01 日本電気株式会社 電子装置又はその製造方法
CN107041137A (zh) * 2014-09-05 2017-08-11 英帆萨斯公司 多芯片模块及其制法
US9875969B2 (en) 2009-06-24 2018-01-23 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10283434B2 (en) 2015-11-04 2019-05-07 Fujitsu Limited Electronic device, method for manufacturing the electronic device, and electronic apparatus
JP2021093515A (ja) * 2019-12-06 2021-06-17 インテル・コーポレーション 再構成ウェハアセンブリ
CN113948508A (zh) * 2021-10-12 2022-01-18 天津津航计算技术研究所 一种基于硅载板的芯片模块高密度互连方法
DE102014116417B4 (de) 2013-12-18 2022-01-27 Intel Corporation Paket integrierter Schaltungen mit eingebetteter Brücke, Verfahren zum Zusammenbau eines solchen und Paketzusammensetzung
WO2024053103A1 (ja) * 2022-09-09 2024-03-14 ウルトラメモリ株式会社 Ｉｃブリッジ、ｉｃモジュールおよびｉｃモジュールの製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223651A (ja) * 1999-01-28 2000-08-11 United Microelectronics Corp 対向マルチチップ用パッケージ
JP2001244388A (ja) * 2000-02-28 2001-09-07 Matsushita Electric Ind Co Ltd 半導体装置
JP2003303847A (ja) * 2002-04-10 2003-10-24 Kaijo Corp 半導体構造およびボンディング方法
JP2006073651A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置
JP2006261311A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置及びその製造方法
JP2008270446A (ja) * 2007-04-19 2008-11-06 Toshiba Corp 積層型半導体装置とその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223651A (ja) * 1999-01-28 2000-08-11 United Microelectronics Corp 対向マルチチップ用パッケージ
JP2001244388A (ja) * 2000-02-28 2001-09-07 Matsushita Electric Ind Co Ltd 半導体装置
JP2003303847A (ja) * 2002-04-10 2003-10-24 Kaijo Corp 半導体構造およびボンディング方法
JP2006073651A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置
JP2006261311A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置及びその製造方法
JP2008270446A (ja) * 2007-04-19 2008-11-06 Toshiba Corp 積層型半導体装置とその製造方法

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11824008B2 (en) 2009-06-24 2023-11-21 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US9875969B2 (en) 2009-06-24 2018-01-23 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10510669B2 (en) 2009-06-24 2019-12-17 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10763216B2 (en) 2009-06-24 2020-09-01 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10923429B2 (en) 2009-06-24 2021-02-16 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US12113026B2 (en) 2009-06-24 2024-10-08 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
DE112010002705B4 (de) 2009-06-24 2021-11-11 Intel Corporation Multi-Chip-Baugruppe und Verfahren zur Bereitstellung von Chip-Chip-Zwischenverbindungen in derselben
US11876053B2 (en) 2009-06-24 2024-01-16 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
DE102014116417B4 (de) 2013-12-18 2022-01-27 Intel Corporation Paket integrierter Schaltungen mit eingebetteter Brücke, Verfahren zum Zusammenbau eines solchen und Paketzusammensetzung
JP2015220291A (ja) * 2014-05-15 2015-12-07 株式会社ソシオネクスト 半導体装置及びその製造方法
JP2016018876A (ja) * 2014-07-08 2016-02-01 日本電気株式会社 電子装置又はその製造方法
CN107041137A (zh) * 2014-09-05 2017-08-11 英帆萨斯公司 多芯片模块及其制法
US10283434B2 (en) 2015-11-04 2019-05-07 Fujitsu Limited Electronic device, method for manufacturing the electronic device, and electronic apparatus
JP2021093515A (ja) * 2019-12-06 2021-06-17 インテル・コーポレーション 再構成ウェハアセンブリ
CN113948508A (zh) * 2021-10-12 2022-01-18 天津津航计算技术研究所 一种基于硅载板的芯片模块高密度互连方法
WO2024053103A1 (ja) * 2022-09-09 2024-03-14 ウルトラメモリ株式会社 Ｉｃブリッジ、ｉｃモジュールおよびｉｃモジュールの製造方法

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