JP2011040457A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
【解決手段】ビア・ラストにおいて、BEOLまで終えたシリコン基板10に対し、基板のおもて面に穴16を開け、穴16の内壁に絶縁膜18を形成し、穴16の中にビア導体24としてCuを電解めっき法により埋め込んでから、穴16の底部つまりCuビア導体24の底部が露出するまでシリコン基板10の裏面をウエットエッチングで削る。
【選択図】 図7
Description
圧力=350mTorr
処理ガス:TEOS/O2/Ar=5:20:75(流量比)
マイクロ波パワー=3.5kW
処理時間=60sec
Claims (14)
- 半導体基板にそのデバイス形成面側から所望の深さで穴を開ける第1の工程と、
前記穴の内壁に絶縁膜を形成する第2の工程と、
前記穴に導体を埋め込む第3の工程と、
ウエットエッチングにより前記半導体基板の裏面を前記導体が露出するまで削る第4の工程と
を有する半導体装置の製造方法。 - 前記第2の工程は、前記絶縁膜の少なくとも一部として、プラズマの生成にマイクロ波放電を利用するマイクロ波励起プラズマCVD法によりシリコン酸化膜を形成する、請求項1に記載の半導体装置の製造方法。
- 前記マイクロ波放電にラジアルラインスロットアンテナもしくは金属表面波励起プラズマを用いる、請求項2に記載の半導体装置の製造方法。
- 前記シリコン酸化膜の原料にTEOSを含む、請求項2または請求項3に記載の半導体装置の製造方法。
- 前記シリコン酸化膜の成膜温度を350℃以下とする、請求項2〜4のいずれか一項に記載の半導体装置の製造方法。
- 前記マイクロ波放電に使用されるガスがArガスまたはKrガスを含む、請求項2〜5のいずれか一項に記載の半導体装置の製造方法。
- 前記第2の工程と前記第3の工程との間で、前記シリコン酸化膜をプラズマ窒化法により窒化する第5の工程を有する、請求項1〜6のいずれか一項に記載の半導体装置の製造方法。
- 前記プラズマ窒化法は、マイクロ波放電にラジアルラインスロットアンテナもしくは金属表面波励起プラズマを用いるマイクロ波励起プラズマ窒化法である、請求項7に記載の半導体装置の製造方法。
- 前記プラズマ窒化の処理ガスとして、不活性ガスとNH3ガスもしくはN2ガスとを含む混合ガスを用いる、請求項7または請求項8に記載の半導体装置の製造方法。
- 前記第2の工程は、前記絶縁膜の少なくとも一部として窒化膜をCVD法により形成する、請求項1に記載の半導体装置の製造方法。
- 前記CVD法は、マイクロ波放電にラジアルラインスロットアンテナもしくは金属表面波励起プラズマを用いるマイクロ波励起プラズマCVD法である、請求項10に記載の半導体装置の製造方法。
- 前記第4の工程は、枚葉処理装置を使用して、前記半導体基板をスピン回転ヘッド上で回転させながら、その上からHFとNHO3とカルボン酸とを含有するエッチング液を噴き付ける、請求項1〜11のいずれか一項に記載の半導体装置の製造方法。
- おもて面上に半導体素子が形成される半導体基板と、
前記半導体基板を貫通する穴と、
前記穴の側壁に設けられる絶縁膜と、
前記穴に埋め込まれた導体と
を有し、
前記半導体基板の裏面がウエットエッチングにより削られて、前記導体が前記穴を貫通している、半導体装置。 - おもて面上に半導体素子が形成される半導体基板と、
前記半導体基板を貫通する穴と、
前記穴の側壁に設けられる絶縁膜と、
前記穴に埋め込まれた導体と
を有し、
前記絶縁膜が、成膜ガスとして、TEOSを用い、プラズマの生成にマイクロ波放電を利用するマイクロ波励起プラズマCVD法により形成された酸化シリコンよりなる膜を含む、半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2009184237A JP5885904B2 (ja) | 2009-08-07 | 2009-08-07 | 半導体装置の製造方法 |
PCT/JP2010/004937 WO2011016242A1 (ja) | 2009-08-07 | 2010-08-05 | 半導体装置及びその製造方法 |
TW099126181A TWI512890B (zh) | 2009-08-07 | 2010-08-06 | Semiconductor device and manufacturing method thereof |
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JP2009184237A JP5885904B2 (ja) | 2009-08-07 | 2009-08-07 | 半導体装置の製造方法 |
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JP2011040457A true JP2011040457A (ja) | 2011-02-24 |
JP5885904B2 JP5885904B2 (ja) | 2016-03-16 |
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JP (1) | JP5885904B2 (ja) |
TW (1) | TWI512890B (ja) |
WO (1) | WO2011016242A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9312171B2 (en) | 2013-11-29 | 2016-04-12 | Samsung Electronics Co., Ltd. | Semiconductor devices having through-electrodes and methods for fabricating the same |
US9594256B2 (en) | 2012-08-24 | 2017-03-14 | Okia Optical Co., Ltd. | Thermoplastic laminate, decorative part for eyewear and process of preparation thereof |
US10388592B2 (en) | 2016-11-29 | 2019-08-20 | Canon Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI449152B (zh) | 2011-12-21 | 2014-08-11 | Ind Tech Res Inst | 半導體元件堆疊結構 |
JP2013171862A (ja) * | 2012-02-17 | 2013-09-02 | Tokyo Electron Ltd | 金属ペースト充填方法及び金属ペースト充填装置及びビアプラグ作製方法 |
TWI611507B (zh) * | 2014-10-23 | 2018-01-11 | Acm Res Shanghai Inc | 矽通孔背面露頭的方法和裝置 |
US10354910B2 (en) * | 2016-05-27 | 2019-07-16 | Raytheon Company | Foundry-agnostic post-processing method for a wafer |
Citations (7)
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JPS607148A (ja) * | 1983-06-24 | 1985-01-14 | Nec Corp | 半導体装置の製造方法 |
JPH11145138A (ja) * | 1997-11-10 | 1999-05-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2003203914A (ja) * | 2002-01-09 | 2003-07-18 | Japan Science & Technology Corp | 半導体集積回路装置及びその製造方法 |
WO2006080337A1 (ja) * | 2005-01-31 | 2006-08-03 | Nec Corporation | 半導体装置およびその製造方法と、積層型半導体集積回路 |
JP2006286929A (ja) * | 2005-03-31 | 2006-10-19 | Nippon Zeon Co Ltd | 樹脂膜保持基板の製造方法及びその利用 |
JP2008124424A (ja) * | 2006-10-16 | 2008-05-29 | Tokyo Electron Ltd | プラズマ成膜装置及びプラズマ成膜方法 |
WO2008153064A1 (ja) * | 2007-06-11 | 2008-12-18 | Tokyo Electron Limited | プラズマ処理装置および処理方法 |
Family Cites Families (2)
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TWI239629B (en) * | 2003-03-17 | 2005-09-11 | Seiko Epson Corp | Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus |
JP3646720B2 (ja) * | 2003-06-19 | 2005-05-11 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
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2009
- 2009-08-07 JP JP2009184237A patent/JP5885904B2/ja not_active Expired - Fee Related
-
2010
- 2010-08-05 WO PCT/JP2010/004937 patent/WO2011016242A1/ja active Application Filing
- 2010-08-06 TW TW099126181A patent/TWI512890B/zh not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS607148A (ja) * | 1983-06-24 | 1985-01-14 | Nec Corp | 半導体装置の製造方法 |
JPH11145138A (ja) * | 1997-11-10 | 1999-05-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2003203914A (ja) * | 2002-01-09 | 2003-07-18 | Japan Science & Technology Corp | 半導体集積回路装置及びその製造方法 |
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WO2008153064A1 (ja) * | 2007-06-11 | 2008-12-18 | Tokyo Electron Limited | プラズマ処理装置および処理方法 |
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WO2011016242A1 (ja) | 2011-02-10 |
TWI512890B (zh) | 2015-12-11 |
TW201120995A (en) | 2011-06-16 |
JP5885904B2 (ja) | 2016-03-16 |
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