JP2011029663A - 装置及びプロセッサー - Google Patents
装置及びプロセッサー Download PDFInfo
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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Abstract
【解決手段】1つ以上の命令を実行するプロセッサーロジックは、2つ以上の向かい合わせに積み重ねられたダイ102,104に配分される。プロセッサーは、積み重ねられたダイの間に導電性インターフェース275を有し、ダイ間通信を可能にする。プロセッサーの性能(例えば、クロック周期当たりの命令数により測定される)及び熱及び電力管理の効率は、連携して命令を実行するよう共に機能する2つの積み重ねられたダイの間で、プロセッサーのコアを分離することにより、実現される。
【選択図】図17
Description
図9に示される新しいデータパス420aは、ロードデータがデータキャッシュ706から読み出された後、データは、実行ロジック704の先端820に到達するために、実行ロジック704の全体に沿って伝送される必要がないため、効率的である。その代わり、データは、導電性のダイ内インターフェース275を経由して実行ロジック704の先端820へ直接送信されて良い。このように、データは実行ロジック704を横切る時間を必要とせず、従って、所望のロードデータをデータキャッシュ706から実行ロジック704の先端(図7の730)へ得るための時間遅延が回避又は削減される。同様に時間遅延の削減は、図7の参照番号732により示されるデータパスの部分において実現されて良い。
102、104 ダイ
106、108 導電素子
203、205 シリコン活性層
210 放熱板
212 I/Oバンプ
214、216 金属層
220、230 非活性のバルクシリコン
233 バイアス
300 命令パイプライン
302、304、306、308、312、313、314 命令パイプラインのステージ
420 ロードアクセスデータパス
520 スケジュール実行データパス
700 スカラープロセッサーダイ
702 汎用レジスターファイル
704 実行ロジック
706 データキャッシュ
708 スケジューリングロジック
708a、708b ロジック部分
802、804、902、904、1002、1004、1102、1104、1202、1204 ダイ
1702 マルチダイプロセッサー
1704 インターフェース部分
1740 命令
1741 データ
Claims (17)
- 第1のダイに配置され、実行パイプライン動作の第1のステージを実行可能な実行パイプラインの第1のステージ部、
第2のダイに配置され、前記実行パイプラインの第1のステージ部が前記実行パイプライン動作の第1のステージを実行するのに応答して、前記実行パイプライン動作の第2のステージを実行可能な実行パイプラインの第2のステージ部、及び
前記実行パイプラインの第1のステージ部を前記実行パイプラインの第2のステージ部に結合する結合インターフェース、
を有し、
前記第1及び第2のダイは、前記実行パイプラインの第1のステージ部が前記実行パイプラインの第2のステージ部と少なくとも部分的に重なり合うように更に結合される、
ことを特徴とする装置。 - 前記実行パイプラインの第1のステージ部は、スケジューリング動作を実行可能なスケジューリングステージを有し、
前記実行パイプラインの第2のステージ部は、前記スケジューリングステージが前記スケジューリング動作を実行するのに応答して、演算動作を実行可能な実行ステージを有する、
請求項1記載の装置。 - クリティカルデータパスは、前記実行パイプラインの第1のステージ及び前記実行パイプラインの第2のステージ部を有する、
請求項1記載の装置。 - 前記実行パイプラインの第1のステージ部は、フェッチ動作を実行可能なフェッチステージを有し、
前記実行パイプラインの第2のステージ部は、デコード動作を実行可能なデコードステージを有する、
請求項1記載の装置。 - 前記実行パイプラインの第1のステージ部は、演算動作を実行可能な実行ステージを有し、
前記実行パイプラインの第2のステージ部は、メモリーアクセス動作を実行可能なメモリーアクセスステージを有する、
請求項1記載の装置。 - 前記実行パイプラインの第1のステージ部は、命令ポインタ生成動作を実行可能な命令ポインタ生成ステージを有し、
前記実行パイプラインの第2のステージ部は、フェッチ動作を実行可能なフェッチステージを有する、
請求項4記載の装置。 - 前記実行パイプラインの第1のステージ部は、第1の命令パイプラインステージ動作を実行可能な第1の命令パイプラインステージを有し、
前記実行パイプラインの第2のステージ部は、第2の命令パイプラインステージ動作を実行可能な第1の命令パイプラインステージを有する、
請求項1記載の装置。 - 前記第1のステージ及び第2のステージは、前記実行パイプラインの連続するステージである、
請求項1記載の装置。 - 前記第1のステージ及び第2のステージは、前記実行パイプラインの連続するステージではない、
請求項1記載の装置。 - 前記実行パイプラインの第1のステージ部は、レジスタリネーム動作を実行可能なレジスタリネームステージを有し、
前記実行パイプラインの第2のステージ部は、退避動作を実行可能な退避ステージを有する、
請求項9記載の装置。 - 演算実行部及び第1の配列の一部を有する第1のダイ、
前記第1の配列の一部とダイ間結合により結合され、命令と関連付けられた演算動作中に前記第1の配列の一部と共に配列として連携して動作する第2の配列の一部を有する第2のダイ、
を有し、
前記ダイ間結合は、前記第1の配列の一部が前記第2の配列の一部と少なくとも部分的に重なり合うように、前記第1の配列の一部及び前記第2の配列の一部を更に結合する、
ことを特徴とする装置。 - 前記第1のダイは、第1のスケジューリング部の一部を更に有し、
前記第2のダイは、前記第1のダイとダイ間結合により結合される第2のスケジューリング部の一部を更に有し、前記第1のスケジューリング部の一部と共にスケジューリング部として連携して動作する、
請求項11記載の装置。 - 前記第1のダイは、第1のアドレス生成部の一部を更に有し、
前記第2のダイは、第2のアドレス生成部の一部を更に有し、
前記第1のアドレス生成の一部は、前記第2のアドレス生成部の一部と結合され、前記第2のアドレス生成部の一部と共にアドレス生成部として連携して動作する、
請求項11記載の装置。 - 前記配列は、レジスターファイルの配列、マイクロコードメモリーの配列及びキャッシュメモリーの配列のグループから選択された1つの配列である、
請求項11記載の装置。 - マイクロプロセッサーは、前記第1の配列の一部を有する前記第1のダイ、前記第2の配列の一部を有する前記第2のダイ及び前記第1のダイに配置されたインターフェースを有し、
当該装置は、前記マイクロプロセッサーの前記インターフェース部と結合されたメモリーを更に有するシステムであり、
前記メモリーは、前記マイクロプロセッサーにより実行されると、前記マイクロプロセッサーに前記第1のダイの前記第1の配列の一部及び前記第2のダイの前記第2の配列の一部を呼び出させる命令を格納する、
請求項11記載の装置。 - 第1のダイに配置された演算ロジック、
第2のダイに配置されたキャッシュメモリー、及び
該キャッシュメモリーが前記演算ロジックと少なくとも部分的に重なり合うように、前記第1のダイを前記第2のダイに結合する結合インターフェース、
を有するプロセッサー。 - 前記演算ロジックは、前記キャッシュメモリーからデータを読み出すロードロジックを有する、
請求項16記載のプロセッサー。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/738,680 US20050127490A1 (en) | 2003-12-16 | 2003-12-16 | Multi-die processor |
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JP2006543849A Division JP2007514317A (ja) | 2003-12-16 | 2004-11-24 | 装置及びプロセッサー |
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JP2013173544A Division JP5847773B2 (ja) | 2003-12-16 | 2013-08-23 | 装置及びプロセッサー |
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JP2011029663A true JP2011029663A (ja) | 2011-02-10 |
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JP2006543849A Pending JP2007514317A (ja) | 2003-12-16 | 2004-11-24 | 装置及びプロセッサー |
JP2010225469A Pending JP2011029663A (ja) | 2003-12-16 | 2010-10-05 | 装置及びプロセッサー |
JP2013173544A Expired - Fee Related JP5847773B2 (ja) | 2003-12-16 | 2013-08-23 | 装置及びプロセッサー |
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Country | Link |
---|---|
US (2) | US20050127490A1 (ja) |
JP (3) | JP2007514317A (ja) |
CN (1) | CN1630080B (ja) |
TW (1) | TWI284410B (ja) |
WO (1) | WO2005062190A1 (ja) |
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2004
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- 2004-11-24 WO PCT/US2004/039236 patent/WO2005062190A1/en active Application Filing
- 2004-11-26 TW TW093136574A patent/TWI284410B/zh not_active IP Right Cessation
- 2004-11-29 CN CN2004100955659A patent/CN1630080B/zh not_active Expired - Fee Related
-
2009
- 2009-02-04 US US12/365,171 patent/US8860199B2/en not_active Expired - Fee Related
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2010
- 2010-10-05 JP JP2010225469A patent/JP2011029663A/ja active Pending
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2013
- 2013-08-23 JP JP2013173544A patent/JP5847773B2/ja not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
CN1630080B (zh) | 2010-05-05 |
US8860199B2 (en) | 2014-10-14 |
US20050127490A1 (en) | 2005-06-16 |
TWI284410B (en) | 2007-07-21 |
TW200532895A (en) | 2005-10-01 |
US20090138688A1 (en) | 2009-05-28 |
JP2007514317A (ja) | 2007-05-31 |
JP2013258425A (ja) | 2013-12-26 |
JP5847773B2 (ja) | 2016-01-27 |
WO2005062190A1 (en) | 2005-07-07 |
CN1630080A (zh) | 2005-06-22 |
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