JP2011014197A5 - - Google Patents
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- Publication number
- JP2011014197A5 JP2011014197A5 JP2009157696A JP2009157696A JP2011014197A5 JP 2011014197 A5 JP2011014197 A5 JP 2011014197A5 JP 2009157696 A JP2009157696 A JP 2009157696A JP 2009157696 A JP2009157696 A JP 2009157696A JP 2011014197 A5 JP2011014197 A5 JP 2011014197A5
- Authority
- JP
- Japan
- Prior art keywords
- test period
- voltage
- write voltage
- node
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims 2
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009157696A JP5328525B2 (ja) | 2009-07-02 | 2009-07-02 | 半導体装置 |
| US12/801,857 US8179734B2 (en) | 2009-07-02 | 2010-06-29 | Semiconductor device |
| US13/438,742 US8693268B2 (en) | 2009-07-02 | 2012-04-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009157696A JP5328525B2 (ja) | 2009-07-02 | 2009-07-02 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011014197A JP2011014197A (ja) | 2011-01-20 |
| JP2011014197A5 true JP2011014197A5 (https=) | 2012-04-05 |
| JP5328525B2 JP5328525B2 (ja) | 2013-10-30 |
Family
ID=43412573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009157696A Expired - Fee Related JP5328525B2 (ja) | 2009-07-02 | 2009-07-02 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US8179734B2 (https=) |
| JP (1) | JP5328525B2 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5328525B2 (ja) * | 2009-07-02 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US8054125B2 (en) * | 2009-12-31 | 2011-11-08 | Silicon Laboratories Inc. | Charge pump with low power, high voltage protection circuitry |
| JP6084520B2 (ja) * | 2013-06-13 | 2017-02-22 | サイプレス セミコンダクター コーポレーション | 半導体メモリおよび半導体メモリの試験方法 |
| US9478297B2 (en) * | 2014-01-31 | 2016-10-25 | Taiwan Semiconductor Manufacturing Company Limited | Multiple-time programmable memory |
| US10957364B2 (en) | 2018-09-26 | 2021-03-23 | Micron Technology, Inc. | Charge pump supply optimization and noise reduction method for logic systems |
| US11070128B2 (en) | 2019-01-23 | 2021-07-20 | Stmicroelectronics International N.V. | Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory |
| US11258358B2 (en) | 2019-01-23 | 2022-02-22 | Stmicroelectronics International N.V. | Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory |
| CN115910138B (zh) * | 2021-08-24 | 2025-09-19 | 浙江驰拓科技有限公司 | 一种mram写失效的检测处理方法及检测处理电路、mram |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5267201A (en) * | 1990-04-06 | 1993-11-30 | Mosaid, Inc. | High voltage boosted word line supply charge pump regulator for DRAM |
| JP2809921B2 (ja) * | 1992-03-10 | 1998-10-15 | 富士通株式会社 | 不揮発性半導体記憶装置 |
| JP3236105B2 (ja) * | 1993-03-17 | 2001-12-10 | 富士通株式会社 | 不揮発性半導体記憶装置及びその動作試験方法 |
| JP3705842B2 (ja) * | 1994-08-04 | 2005-10-12 | 株式会社ルネサステクノロジ | 半導体装置 |
| US5943263A (en) * | 1997-01-08 | 1999-08-24 | Micron Technology, Inc. | Apparatus and method for programming voltage protection in a non-volatile memory system |
| JP3884810B2 (ja) * | 1997-01-21 | 2007-02-21 | 株式会社ルネサステクノロジ | 高電圧発生装置 |
| JP4056611B2 (ja) * | 1998-03-17 | 2008-03-05 | 富士通株式会社 | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置のメモリデータの再生方法 |
| JP3854025B2 (ja) * | 1998-12-25 | 2006-12-06 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JP3563298B2 (ja) * | 1999-06-11 | 2004-09-08 | 株式会社 沖マイクロデザイン | 電圧検出回路 |
| US6166960A (en) * | 1999-09-24 | 2000-12-26 | Microchip Technology, Incorporated | Method, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an eeprom |
| JP2002008392A (ja) * | 2000-06-22 | 2002-01-11 | Matsushita Electric Ind Co Ltd | 半導体記憶装置およびその評価方法 |
| JP4314056B2 (ja) * | 2003-04-17 | 2009-08-12 | パナソニック株式会社 | 半導体記憶装置 |
| JP2005276345A (ja) * | 2004-03-25 | 2005-10-06 | Nec Electronics Corp | 不揮発性記憶装置及び不揮発性記憶装置の検証方法 |
| JP4565883B2 (ja) * | 2004-04-27 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| US7187600B2 (en) * | 2004-09-22 | 2007-03-06 | Freescale Semiconductor, Inc. | Method and apparatus for protecting an integrated circuit from erroneous operation |
| JP5328525B2 (ja) * | 2009-07-02 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2009
- 2009-07-02 JP JP2009157696A patent/JP5328525B2/ja not_active Expired - Fee Related
-
2010
- 2010-06-29 US US12/801,857 patent/US8179734B2/en active Active
-
2012
- 2012-04-03 US US13/438,742 patent/US8693268B2/en active Active
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