JP2011014195A - フラッシュメモリ - Google Patents

フラッシュメモリ Download PDF

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Publication number
JP2011014195A
JP2011014195A JP2009157560A JP2009157560A JP2011014195A JP 2011014195 A JP2011014195 A JP 2011014195A JP 2009157560 A JP2009157560 A JP 2009157560A JP 2009157560 A JP2009157560 A JP 2009157560A JP 2011014195 A JP2011014195 A JP 2011014195A
Authority
JP
Japan
Prior art keywords
data
bit
input
transferred
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009157560A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011014195A5 (https=
Inventor
Koichi Fukuda
田 浩 一 福
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2009157560A priority Critical patent/JP2011014195A/ja
Priority to US12/828,658 priority patent/US8331146B2/en
Publication of JP2011014195A publication Critical patent/JP2011014195A/ja
Publication of JP2011014195A5 publication Critical patent/JP2011014195A5/ja
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Electronic Switches (AREA)
JP2009157560A 2009-07-02 2009-07-02 フラッシュメモリ Pending JP2011014195A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009157560A JP2011014195A (ja) 2009-07-02 2009-07-02 フラッシュメモリ
US12/828,658 US8331146B2 (en) 2009-07-02 2010-07-01 Flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009157560A JP2011014195A (ja) 2009-07-02 2009-07-02 フラッシュメモリ

Publications (2)

Publication Number Publication Date
JP2011014195A true JP2011014195A (ja) 2011-01-20
JP2011014195A5 JP2011014195A5 (https=) 2012-07-26

Family

ID=43412574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009157560A Pending JP2011014195A (ja) 2009-07-02 2009-07-02 フラッシュメモリ

Country Status (2)

Country Link
US (1) US8331146B2 (https=)
JP (1) JP2011014195A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017004582A (ja) * 2015-06-12 2017-01-05 株式会社東芝 半導体記憶装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8041879B2 (en) * 2005-02-18 2011-10-18 Sandisk Il Ltd Flash memory backup system and method
US8788743B2 (en) * 2012-04-11 2014-07-22 Micron Technology, Inc. Mapping between program states and data patterns
TW201621670A (zh) 2014-09-06 2016-06-16 Neo半導體股份有限公司 非揮發性記憶體之多頁編程寫入方法與裝置
US10720215B2 (en) 2014-09-06 2020-07-21 Fu-Chang Hsu Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming
US9761310B2 (en) 2014-09-06 2017-09-12 NEO Semiconductor, Inc. Method and apparatus for storing information using a memory able to perform both NVM and DRAM functions
US9703719B2 (en) 2015-05-08 2017-07-11 Sandisk Technologies Llc Fast read for non-volatile storage

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08124389A (ja) * 1994-10-26 1996-05-17 Sharp Corp 不揮発性半導体記憶装置
JPH0991973A (ja) * 1995-09-28 1997-04-04 Sanyo Electric Co Ltd 不揮発性多値メモリ装置
JPH11273373A (ja) * 1998-01-09 1999-10-08 Inf Storage Devices Inc アナログ記録・再生システム
WO2006011222A1 (ja) * 2004-07-30 2006-02-02 Spansion Llc 半導体装置および書き込み方法
JP2009054246A (ja) * 2007-08-28 2009-03-12 Toshiba Corp 半導体記憶装置
JP2010061723A (ja) * 2008-09-02 2010-03-18 Toppan Printing Co Ltd 半導体メモリー装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6353554B1 (en) * 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
JP3629144B2 (ja) * 1998-06-01 2005-03-16 株式会社東芝 不揮発性半導体記憶装置
US5930172A (en) * 1998-06-23 1999-07-27 Advanced Micro Devices, Inc. Page buffer for a multi-level flash memory with a limited number of latches per memory cell
JP3936908B2 (ja) 2002-12-24 2007-06-27 株式会社日立ハイテクノロジーズ 質量分析装置及び質量分析方法
JP3920768B2 (ja) 2002-12-26 2007-05-30 株式会社東芝 不揮発性半導体メモリ
US7852671B2 (en) * 2008-10-30 2010-12-14 Micron Technology, Inc. Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08124389A (ja) * 1994-10-26 1996-05-17 Sharp Corp 不揮発性半導体記憶装置
JPH0991973A (ja) * 1995-09-28 1997-04-04 Sanyo Electric Co Ltd 不揮発性多値メモリ装置
JPH11273373A (ja) * 1998-01-09 1999-10-08 Inf Storage Devices Inc アナログ記録・再生システム
WO2006011222A1 (ja) * 2004-07-30 2006-02-02 Spansion Llc 半導体装置および書き込み方法
JP2009054246A (ja) * 2007-08-28 2009-03-12 Toshiba Corp 半導体記憶装置
JP2010061723A (ja) * 2008-09-02 2010-03-18 Toppan Printing Co Ltd 半導体メモリー装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017004582A (ja) * 2015-06-12 2017-01-05 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
US8331146B2 (en) 2012-12-11
US20110002165A1 (en) 2011-01-06

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