JP2011003250A5 - - Google Patents

Download PDF

Info

Publication number
JP2011003250A5
JP2011003250A5 JP2009146809A JP2009146809A JP2011003250A5 JP 2011003250 A5 JP2011003250 A5 JP 2011003250A5 JP 2009146809 A JP2009146809 A JP 2009146809A JP 2009146809 A JP2009146809 A JP 2009146809A JP 2011003250 A5 JP2011003250 A5 JP 2011003250A5
Authority
JP
Japan
Prior art keywords
clock signal
circuit
internal clock
buffer
cell array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009146809A
Other languages
English (en)
Japanese (ja)
Other versions
JP5441208B2 (ja
JP2011003250A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2009146809A priority Critical patent/JP5441208B2/ja
Priority claimed from JP2009146809A external-priority patent/JP5441208B2/ja
Priority to US12/814,478 priority patent/US8351283B2/en
Publication of JP2011003250A publication Critical patent/JP2011003250A/ja
Publication of JP2011003250A5 publication Critical patent/JP2011003250A5/ja
Application granted granted Critical
Publication of JP5441208B2 publication Critical patent/JP5441208B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2009146809A 2009-06-19 2009-06-19 半導体記憶装置 Active JP5441208B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009146809A JP5441208B2 (ja) 2009-06-19 2009-06-19 半導体記憶装置
US12/814,478 US8351283B2 (en) 2009-06-19 2010-06-13 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009146809A JP5441208B2 (ja) 2009-06-19 2009-06-19 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2011003250A JP2011003250A (ja) 2011-01-06
JP2011003250A5 true JP2011003250A5 (enExample) 2012-04-12
JP5441208B2 JP5441208B2 (ja) 2014-03-12

Family

ID=43354241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009146809A Active JP5441208B2 (ja) 2009-06-19 2009-06-19 半導体記憶装置

Country Status (2)

Country Link
US (1) US8351283B2 (enExample)
JP (1) JP5441208B2 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101998750B1 (ko) * 2012-07-16 2019-10-01 에스케이하이닉스 주식회사 반도체 장치
KR102041471B1 (ko) * 2012-12-24 2019-11-07 에스케이하이닉스 주식회사 반도체 장치
US9053768B2 (en) * 2013-03-14 2015-06-09 Gsi Technology, Inc. Systems and methods of pipelined output latching involving synchronous memory arrays
CN103440880A (zh) * 2013-09-03 2013-12-11 苏州宽温电子科技有限公司 一种sram存储器以及位单元追踪方法
KR102130611B1 (ko) 2013-12-31 2020-07-06 삼성전자주식회사 아날로그-디지털 변환 회로, 이를 포함하는 이미지 센서 및 이미지 센서의 동작 방법
US11227653B1 (en) 2016-12-06 2022-01-18 Gsi Technology, Inc. Storage array circuits and methods for computational memory cells
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10847213B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10777262B1 (en) 2016-12-06 2020-09-15 Gsi Technology, Inc. Read data processing circuits and methods associated memory cells
US10847212B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10725777B2 (en) 2016-12-06 2020-07-28 Gsi Technology, Inc. Computational memory cell and processing array device using memory cells
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
KR20190000663A (ko) * 2017-06-23 2019-01-03 에스케이하이닉스 주식회사 메모리 장치 및 그 동작 방법
US10877731B1 (en) 2019-06-18 2020-12-29 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10958272B2 (en) 2019-06-18 2021-03-23 Gsi Technology, Inc. Computational memory cell and processing array device using complementary exclusive or memory cells
US10930341B1 (en) 2019-06-18 2021-02-23 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US11955971B2 (en) * 2021-02-08 2024-04-09 Rambus Inc. Integrated transmitter slew rate calibration
US11909404B1 (en) * 2022-12-12 2024-02-20 Advanced Micro Devices, Inc. Delay-locked loop offset calibration and correction
US11916558B1 (en) * 2022-12-13 2024-02-27 Qualcomm Incorporated DDR phy parallel clock paths architecture

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1011966A (ja) * 1996-06-27 1998-01-16 Mitsubishi Electric Corp 同期型半導体記憶装置および同期型メモリモジュール
JP3549751B2 (ja) * 1998-11-30 2004-08-04 富士通株式会社 半導体集積回路装置
JP2001068650A (ja) * 1999-08-30 2001-03-16 Hitachi Ltd 半導体集積回路装置
JP2002100980A (ja) 2000-09-21 2002-04-05 Ricoh Co Ltd Ｄｌｌ回路
KR100422572B1 (ko) * 2001-06-30 2004-03-12 주식회사 하이닉스반도체 레지스터 제어 지연고정루프 및 그를 구비한 반도체 소자
KR100560644B1 (ko) * 2002-01-09 2006-03-16 삼성전자주식회사 클럭 동기회로를 구비하는 집적회로장치
JP4426277B2 (ja) * 2003-12-24 2010-03-03 株式会社リコー 半導体集積回路及びその半導体集積回路を使用した光ディスク記録装置
US7116143B2 (en) * 2004-12-30 2006-10-03 Micron Technology, Inc. Synchronous clock generator including duty cycle correction
KR100834400B1 (ko) 2005-09-28 2008-06-04 주식회사 하이닉스반도체 Ｄｒａｍ의 동작 주파수를 높이기 위한 지연고정루프 및 그의 출력드라이버
US7449930B2 (en) * 2005-09-29 2008-11-11 Hynix Semiconductor Inc. Delay locked loop circuit
KR100722775B1 (ko) * 2006-01-02 2007-05-30 삼성전자주식회사 반도체 장치의 지연동기루프 회로 및 지연동기루프제어방법

Similar Documents

Publication Publication Date Title
JP2011003250A5 (enExample)
WO2010016869A3 (en) Phase change memory structures and methods
WO2011087597A3 (en) Reduced area memory array by using sense amplifier as write driver
KR101509433B1 (ko) 데이터 출력 회로 및 이를 포함하는 씨아이에스
WO2013025262A3 (en) Memory devices and methods for high random transaction rate
WO2010080342A3 (en) Pseudo dual-ported sram
JP2011141928A (ja) 半導体装置及びその制御方法
JP2012198977A5 (ja) 半導体装置
CN202453864U (zh) 基于fpga和ddr2 sdram的大容量异步fifo缓存
WO2007117539A3 (en) Memory interface circuitry with phase detection
JP2012142562A5 (ja) 半導体装置
JP2013106931A5 (enExample)
JP2009206976A5 (enExample)
JP2010267326A5 (enExample)
JP2010288235A5 (ja) 半導体装置
WO2011005999A3 (en) Dqs resync calibration
DE602006015596D1 (de) Konfigurierbarer MVRAM und Konfigurationsverfahren
WO2007117969A3 (en) Fast rasterizer
EP1944869A3 (en) Variable sized soft memory macros in structured cell arrays, and related methods
US20130058174A1 (en) Controller and access method for ddr psram and operating method thereof
RU2009102314A (ru) Способ построения устройств хранения и передачи информации с обнаружением двойных ошибок
JP2014014021A5 (enExample)
JP2013527541A5 (enExample)
US8873306B2 (en) Pipe latch control circuit and semiconductor integrated circuit using the same
WO2008121426A3 (en) Testing for sram memory data retention