JP2010538497A - 不揮発性半導体メモリ・デバイスにおける欠陥を修復するための方法および装置 - Google Patents

不揮発性半導体メモリ・デバイスにおける欠陥を修復するための方法および装置 Download PDF

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JP2010538497A
JP2010538497A JP2010524138A JP2010524138A JP2010538497A JP 2010538497 A JP2010538497 A JP 2010538497A JP 2010524138 A JP2010524138 A JP 2010524138A JP 2010524138 A JP2010524138 A JP 2010524138A JP 2010538497 A JP2010538497 A JP 2010538497A
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annealing
heating element
memory device
self
semiconductor device
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JP2010538497A5 (https=
Inventor
ブローナー，ゲアリー，ビー．
リ，ミン
マレン，ドナルド，アール．
ウェア，フレデリック
ドナリー，ケビン，エス．
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ラムバス・インコーポレーテッド
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2010524138A 2007-09-05 2008-09-04 不揮発性半導体メモリ・デバイスにおける欠陥を修復するための方法および装置 Pending JP2010538497A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US97022307P 2007-09-05 2007-09-05
PCT/US2008/075261 WO2009032928A2 (en) 2007-09-05 2008-09-04 Method and apparatus to repair defects in nonvolatile semiconductor memory devices

Publications (2)

Publication Number Publication Date
JP2010538497A true JP2010538497A (ja) 2010-12-09
JP2010538497A5 JP2010538497A5 (https=) 2011-10-20

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JP2010524138A Pending JP2010538497A (ja) 2007-09-05 2008-09-04 不揮発性半導体メモリ・デバイスにおける欠陥を修復するための方法および装置

Country Status (4)

Country Link
US (2) US8193573B2 (https=)
EP (1) EP2191473A2 (https=)
JP (1) JP2010538497A (https=)
WO (1) WO2009032928A2 (https=)

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JP2012142576A (ja) * 2010-12-28 2012-07-26 Samsung Electronics Co Ltd 貫通電極を有する積層構造の半導体装置、半導体メモリ装置、半導体メモリ・システム及びその動作方法
WO2015008860A1 (ja) * 2013-07-19 2015-01-22 日本電信電話株式会社 電気素子のパッケージ
WO2016031117A1 (ja) * 2014-08-29 2016-03-03 日本電信電話株式会社 電気素子のパッケージ
KR101747191B1 (ko) 2011-01-14 2017-06-14 에스케이하이닉스 주식회사 반도체 장치
JP2023067686A (ja) * 2021-10-29 2023-05-16 旺宏電子股▲ふん▼有限公司 ３ｄフラッシュメモリモジュールチップおよびその製造方法

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KR101624969B1 (ko) 2009-05-26 2016-05-31 삼성전자주식회사 메모리 시스템 및 그것의 배드 블록 관리 방법
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CN104022086A (zh) * 2013-03-01 2014-09-03 日月光半导体制造股份有限公司 半导体封装结构与其制造方法
US9734919B2 (en) 2013-05-23 2017-08-15 Seagate Technology Llc Recovery of interfacial defects in memory cells
US9064824B2 (en) * 2013-11-12 2015-06-23 International Business Machines Corporation In-situ annealing for extending the lifetime of CMOS products
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US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
KR102142590B1 (ko) 2014-06-16 2020-08-07 삼성전자 주식회사 저항성 메모리 장치 및 저항성 메모리 장치의 동작방법
US9455038B2 (en) 2014-08-20 2016-09-27 Sandisk Technologies Llc Storage module and method for using healing effects of a quarantine process
US9613719B1 (en) 2015-02-17 2017-04-04 Darryl G. Walker Multi-chip non-volatile semiconductor memory package including heater and sensor elements
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US10499461B2 (en) * 2015-12-21 2019-12-03 Intel Corporation Thermal head with a thermal barrier for integrated circuit die processing
US10388397B2 (en) 2016-07-01 2019-08-20 Synopsys, Inc. Logic timing and reliability repair for nanowire circuits
US9761290B1 (en) 2016-08-25 2017-09-12 Sandisk Technologies Llc Overheat prevention for annealing non-volatile memory
US10467134B2 (en) 2016-08-25 2019-11-05 Sandisk Technologies Llc Dynamic anneal characteristics for annealing non-volatile memory
US20180108642A1 (en) * 2016-10-13 2018-04-19 Globalfoundries Inc. Interposer heater for high bandwidth memory applications
US10545805B2 (en) * 2017-03-29 2020-01-28 Macronix International Co., Ltd. Memory system, reading method thereof and writing method thereof
US10692793B2 (en) * 2018-03-02 2020-06-23 Micron Technology, Inc. Electronic device with a package-level thermal regulator mechanism and associated systems, devices, and methods
US10834853B2 (en) 2018-03-02 2020-11-10 Micron Technology, Inc. Electronic device with a card-level thermal regulator mechanism and associated systems, devices, and methods
TWI747153B (zh) * 2019-06-03 2021-11-21 旺宏電子股份有限公司 三維快閃記憶體模組以及三維快閃記憶體的修復與操作方法
WO2021002387A1 (ja) * 2019-07-04 2021-01-07 パナソニックＩｐマネジメント株式会社 記憶装置ユニット
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JP2012142576A (ja) * 2010-12-28 2012-07-26 Samsung Electronics Co Ltd 貫通電極を有する積層構造の半導体装置、半導体メモリ装置、半導体メモリ・システム及びその動作方法
KR101747191B1 (ko) 2011-01-14 2017-06-14 에스케이하이닉스 주식회사 반도체 장치
WO2015008860A1 (ja) * 2013-07-19 2015-01-22 日本電信電話株式会社 電気素子のパッケージ
JP2015023154A (ja) * 2013-07-19 2015-02-02 日本電信電話株式会社 電気素子のパッケージ
WO2016031117A1 (ja) * 2014-08-29 2016-03-03 日本電信電話株式会社 電気素子のパッケージ
JP2016051773A (ja) * 2014-08-29 2016-04-11 日本電信電話株式会社 電気素子のパッケージ
JP2023067686A (ja) * 2021-10-29 2023-05-16 旺宏電子股▲ふん▼有限公司 ３ｄフラッシュメモリモジュールチップおよびその製造方法
JP7362802B2 (ja) 2021-10-29 2023-10-17 旺宏電子股▲ふん▼有限公司 ３ｄフラッシュメモリモジュールチップおよびその製造方法
US12327594B2 (en) 2021-10-29 2025-06-10 Macronix International Co., Ltd. 3D flash memory module chip and method of fabricating the same

Also Published As

Publication number Publication date
WO2009032928A3 (en) 2009-05-14
US20120236668A1 (en) 2012-09-20
US20100230807A1 (en) 2010-09-16
WO2009032928A8 (en) 2010-04-15
WO2009032928A2 (en) 2009-03-12
US8497544B2 (en) 2013-07-30
EP2191473A2 (en) 2010-06-02
US8193573B2 (en) 2012-06-05

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