JP2010519767A - 半導体構造をエッチングするための、パルス化反応ガスを補充するパルス化プラズマシステム - Google Patents
半導体構造をエッチングするための、パルス化反応ガスを補充するパルス化プラズマシステム Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
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- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
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Abstract
【選択図】図3
Description
Claims (23)
- サンプルのエッチング方法であって、
パルス化プラズマ・プロセスを適用することによって前記サンプルの一部を除去する工程を含み、この場合前記パルス化プラズマ・プロセスは複数のデューティサイクルから成り、各デューティサイクルはプラズマのオン状態とオフ状態の組合せであり、前記プラズマは反応ガスから発生し、そして前記反応ガスは前記プラズマの前記オン状態の間でなく前記プラズマの前記オフ状態の間に補充される、方法。 - 前記反応ガスが前記プラズマの前記オフ状態の間に補充される結果、前記パルス化プラズマ・プロセスの終了時の前記プラズマのガス種の組成が、前記パルス化プラズマ・プロセスの開始時の前記プラズマのガス種の組成の1%以内となる、請求項1に記載の方法。
- 前記パルス化プラズマ・プロセスの終了時の前記プラズマの圧力が、前記パルス化プラズマ・プロセスの開始時の前記プラズマの圧力の1mトール以内である、請求項2に記載の方法。
- 前記オン状態の持続時間が、前記サンプルに隣接した反応領域におけるマイクロ・ローディングを実質的に阻止するのに十分に短く、且つ前記オフ状態の持続時間が、前記サンプルに隣接した前記反応領域からのエッチング副産物のセットの除去を実質的に可能にするのに十分に長い、請求項1に記載の方法。
- 前記オン状態の間に前記サンプルに負のバイアスを加え、前記オフ状態の間に前記サンプルにゼロバイアスを加える、請求項1に記載の方法。
- 前記オン状態から成る各デューティサイクルの部分を5〜95%の範囲とする、請求項1に記載の方法。
- 前記プラズマの前記オフ状態の持続時間を、エッチング副産物の50%超が前記反応領域から除去されるまでの時間に実質的に一致するように選択する、請求項4に記載の方法。
- 不活性ガスを使用して、前記プラズマの前記オフ状態の間に前記エッチング副産物のセットの除去を強化する、請求項4に記載の方法。
- サンプルのエッチング方法であって、
連続プラズマ・プロセスを適用することによって前記サンプルの第1部分を除去する工程と、
前記連続プラズマ・プロセスを終了する工程と、
パルス化プラズマ・プロセスを適用することによって前記サンプルの第2部分を除去する工程であって、前記パルス化プラズマ・プロセスが複数のデューティサイクルから成り、各デューティサイクルがプラズマのオン状態とオフ状態の組合せであり、前記プラズマが反応ガスから発生し、そして前記反応ガスが前記プラズマの前記オン状態の間でなく前記プラズマの前記オフ状態の間に補充される工程と
を含む方法。 - 前記反応ガスが前記プラズマの前記オフ状態の間に補充される結果、前記パルス化プラズマ・プロセスの終了時の前記プラズマのガス種の組成が、前記パルス化プラズマ・プロセスの開始時の前記プラズマのガス種の組成の1%以内となる、請求項9に記載の方法。
- 前記パルス化プラズマ・プロセスの終了時の前記プラズマの圧力が、前記パルス化プラズマ・プロセスの開始時の前記プラズマの圧力の1mトール以内である、請求項10に記載の方法。
- 前記オン状態の持続時間が、前記サンプルに隣接した反応領域におけるマイクロ・ローディングを実質的に阻止するのに十分に短く、且つ前記オフ状態の持続時間が、前記サンプルに隣接した前記反応領域からのエッチング副産物のセットの除去を実質的に可能にするのに十分に長い、請求項9に記載の方法。
- 前記オン状態の間に前記サンプルに負のバイアスを加え、前記オフ状態の間に前記サンプルにゼロバイアスを加える、請求項9に記載の方法。
- 前記オン状態から成る各デューティサイクルの部分が5〜95%の範囲である、請求項9に記載の方法。
- 前記連続エッチング・プロセスを終了する工程がエンドポイントを検出する工程を含む、請求項9に記載の方法。
- 前記エンドポイントを、前記連続エッチング・プロセスの間に生成される化学種のセットのリアルタイム組成により決定する、請求項15に記載の方法。
- 前記エンドポイントを、干渉分光法によるリアルタイム膜厚測定よって決定する、請求項15に記載の方法。
- 第2連続プラズマ・プロセスを適用することによって前記サンプルの第3部分を除去する工程と、
前記第2連続プラズマ・プロセスを終了する工程と、
第2パルス化プラズマ・プロセスを適用することによって前記サンプルの第4部分を除去する工程であって、前記第2パルス化プラズマ・プロセスが第2の複数のデューティサイクルから成り、各デューティサイクルが第2プラズマの第2オン状態と第2オフ状態の組合せであり、前記第2プラズマが第2反応ガスから発生し、そして前記第2反応ガスが前記第2プラズマの前記オン状態の間でなく前記オフ状態の間に補充される工程と
をさらに含む、請求項9に記載の方法。 - サンプルのエッチングに用いられるシステムであって、
サンプル・ホルダーを備えたチャンバと、
前記チャンバに連結する排出デバイスであって、前記チャンバを減圧するための排出デバイスと、
前記チャンバに連結するガス注入デバイスであって、前記チャンバに反応ガスを注入するためのガス注入デバイスと、
前記チャンバに連結するプラズマ・イグニション・デバイスであって、前記反応ガスから誘導されるプラズマに点火するためのプラズマ・イグニション・デバイスと、
前記プラズマ・イグニション・デバイス及び前記ガス注入デバイスに連結するコンピューティング・デバイスであって、プロセッサ及びメモリを備え、この場合前記メモリは、パルス化プラズマ・プロセスにおいて前記プラズマ・イグニション・デバイスを制御することによりプラズマのオン状態とオフ状態の間を切り換えるための命令セットを含み、前記パルス化プラズマ・プロセスは複数のデューティサイクルから成り、各デューティサイクルは前記プラズマの1つのオン状態と1つのオフ状態の組合せであり、前記メモリは前記ガス注入デバイスを制御することにより開状態と閉状態の間を切換えるための命令セットも含み、前記プラズマは前記反応ガスから発生し、前記ガス注入デバイスが前記開状態であるときに前記反応ガスが補充され、そして前記プラズマの前記オン状態の間でなく前記オフ状態の間に前記反応ガスが補充されるコンピューティング・デバイスと
を備えるシステム。 - 前記サンプル・ホルダーに連結する電圧源をさらに備え、前記電圧源が前記サンプルにバイアスを掛ける、請求項19に記載のシステム。
- 前記チャンバに連結する検出デバイスをさらに備え、前記検出デバイスが処理工程のエンドポイントを検出する、請求項19に記載のシステム。
- 前記オン状態の持続時間が、サンプルに隣接する反応領域においてマイクロ・ローディングを実質的に抑止するのに十分に短く、且つ前記オフ状態の持続時間が、前記サンプルに隣接する前記反応領域からのエッチング副産物のセットの除去を実質的に可能にするのに十分に長い、請求項19に記載のシステム。
- 前記オン状態から成る各デューティサイクルの部分が5〜95%の範囲である、請求項22に記載のシステム。
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US11/678,047 US7771606B2 (en) | 2007-02-22 | 2007-02-22 | Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures |
US11/678,047 | 2007-02-22 | ||
PCT/US2008/002367 WO2008103453A1 (en) | 2007-02-21 | 2008-02-21 | Pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures |
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JP2012084872A (ja) * | 2010-09-15 | 2012-04-26 | Tokyo Electron Ltd | プラズマエッチング処理装置、プラズマエッチング処理方法、および半導体素子製造方法 |
JP2014112697A (ja) * | 2014-01-15 | 2014-06-19 | Hitachi High-Technologies Corp | プラズマ処理方法 |
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EP3087586B1 (en) | 2013-12-23 | 2021-09-29 | Intel Corporation | Advanced etching techniques for straight, tall and uniform fins across multiple fin pitch structures |
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