JP2010515199A - 適応型メモリ状態区分を備えるｎａｎｄフラッシュメモリセルアレイおよび方法 - Google Patents

適応型メモリ状態区分を備えるｎａｎｄフラッシュメモリセルアレイおよび方法 Download PDF

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Publication number
JP2010515199A
JP2010515199A JP2009544161A JP2009544161A JP2010515199A JP 2010515199 A JP2010515199 A JP 2010515199A JP 2009544161 A JP2009544161 A JP 2009544161A JP 2009544161 A JP2009544161 A JP 2009544161A JP 2010515199 A JP2010515199 A JP 2010515199A
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JP
Japan
Prior art keywords
bit
memory
bits
memory cells
group
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Pending
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JP2009544161A
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English (en)
Japanese (ja)
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JP2010515199A5 (enrdf_load_stackoverflow
Inventor
ムーガット，ファルーク
輝彦 亀井
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SanDisk Corp
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SanDisk Corp
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Priority claimed from US11/618,498 external-priority patent/US7489548B2/en
Priority claimed from US11/618,482 external-priority patent/US7489547B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of JP2010515199A publication Critical patent/JP2010515199A/ja
Publication of JP2010515199A5 publication Critical patent/JP2010515199A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
JP2009544161A 2006-12-29 2007-12-12 適応型メモリ状態区分を備えるｎａｎｄフラッシュメモリセルアレイおよび方法 Pending JP2010515199A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/618,498 US7489548B2 (en) 2006-12-29 2006-12-29 NAND flash memory cell array with adaptive memory state partitioning
US11/618,482 US7489547B2 (en) 2006-12-29 2006-12-29 Method of NAND flash memory cell array with adaptive memory state partitioning
PCT/US2007/087262 WO2008082888A1 (en) 2006-12-29 2007-12-12 Nand flash memory cell array and method with adaptive memory state partitioning

Publications (2)

Publication Number Publication Date
JP2010515199A true JP2010515199A (ja) 2010-05-06
JP2010515199A5 JP2010515199A5 (enrdf_load_stackoverflow) 2011-02-03

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JP2009544161A Pending JP2010515199A (ja) 2006-12-29 2007-12-12 適応型メモリ状態区分を備えるｎａｎｄフラッシュメモリセルアレイおよび方法

Country Status (5)

Country Link
EP (1) EP2304733A1 (enrdf_load_stackoverflow)
JP (1) JP2010515199A (enrdf_load_stackoverflow)
KR (1) KR20090106461A (enrdf_load_stackoverflow)
TW (1) TW200849259A (enrdf_load_stackoverflow)
WO (1) WO2008082888A1 (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010250891A (ja) * 2009-04-14 2010-11-04 Toshiba Corp 不揮発性半導体記憶装置
US8867269B2 (en) 2012-02-10 2014-10-21 Kabushiki Kaisha Toshiba Semiconductor memory device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100953065B1 (ko) 2008-03-14 2010-04-13 주식회사 하이닉스반도체 불휘발성 메모리 소자
JP5710474B2 (ja) * 2008-07-01 2015-04-30 エルエスアイ コーポレーション フラッシュ・メモリにおける読み取り側セル間干渉軽減のための方法および装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005235260A (ja) * 2004-02-17 2005-09-02 Toshiba Corp Ｎａｎｄ型フラッシュメモリ

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3679970B2 (ja) * 2000-03-28 2005-08-03 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US7023739B2 (en) * 2003-12-05 2006-04-04 Matrix Semiconductor, Inc. NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
US7180775B2 (en) * 2004-08-05 2007-02-20 Msystems Ltd. Different numbers of bits per cell in non-volatile memory devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005235260A (ja) * 2004-02-17 2005-09-02 Toshiba Corp Ｎａｎｄ型フラッシュメモリ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010250891A (ja) * 2009-04-14 2010-11-04 Toshiba Corp 不揮発性半導体記憶装置
US8867269B2 (en) 2012-02-10 2014-10-21 Kabushiki Kaisha Toshiba Semiconductor memory device

Also Published As

Publication number Publication date
KR20090106461A (ko) 2009-10-09
WO2008082888A1 (en) 2008-07-10
TW200849259A (en) 2008-12-16
EP2304733A1 (en) 2011-04-06

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