Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits

Definitions

• NAND structure which includes arranging multiple charge-storage transistors acting as memory cells in series, sandwiched between two select gates.
• a NAND array has a number of memory cells, such as 8, 16, or even 32, connected in as a string of memory cells (NAND string) between a bit line and a reference potential through select transistors at either end.
• Word lines are connected with control gates of cells in different series strings.
• a NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line.
• the memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb.
• An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors.
• one unit of such two bits is able to have one of the two bits stored in a memory cell adjacent to one end of a NAND string and another of the two bits stored in another memory cell adjacent the other end.
• Fig. 2C shows the affect of a self boosting technique for an 8-cell NAND string
• Fig. 2F shows the GIDL effect when word line WLO is being programmed
• FIG. 3B shows an example of an organization of a memory array
• FIG. 5D illustrates the read operation that is required to discern the lower bit of the 4-state memory encoded with the LM code.
• FIG. 6A illustrates the effect of GIDL induced errors among the various memory cells in a conventional NAND string.
• FIG. 7A illustrates a previous solution of introducing additional dummy memory cells at the ends of the memory cell chain in a NAND string.
• FIG. 8C illustrates an alternate preferred scheme using the 2-bit LM coding described in FIGs. 5A-5E.
• N+ diffused layer 130 serves as the drain of transistor 122 and the source for transistor of 106
• N+ diffused layer 132 serves as the drain for transistor 106 and the source for transistor 104
• N+ diffused region 134 serves as the drain for transistor 104 and the source for transistor 102
• N+ diffused region 136 serves as the drain for transistor 102 and the source for transistor 100
• N+ diffused layer 138 serves as the drain for transistor 100 and the source for transistor 120.
• N+ diffused layer 126 connects to the bit line for the NAND string
• N+ diffused layer 128 connects to a common source line for multiple NAND strings.
• FIG.s IA- 1C shows four memory cells in the NAND string, the use of four transistors is only provided as an example.
• a NAND string can have less than four memory cells or more than four memory cells.
• some NAND strings will include 8 memory cells (as shown and described below with respect to FIG.s 2B-2F), 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
• FIG. 2B shows an example of an 8 memory cell NAND string.
• the additional word lines are shown as WL4-WL7 (for memory cells 222A-228A) and have similar functionality as word lines WL0-WL3.
• Each memory cell can store data (analog or digital).
• the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data "1" and "0.”
• the voltage threshold is negative after the memory cell is erased, and defined as logic "1.”
• the threshold voltage after a program operation is positive and defined as logic "0.”
• the threshold voltage is negative and a read is attempted, the memory cell will turn on to indicate logic one is being stored.
• the threshold voltage is positive and a read operation is attempted, the memory cell will not turn on, which indicates that logic zero is stored.
• a memory cell can also store multiple levels of information (or "data"), for example, multiple bits of digital data.
• data for example, multiple bits of digital data.
• the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information is stored, there will be four threshold voltage ranges assigned to the data values " 11"," 10", "01", and "00.”
• the threshold voltage after an erase operation is negative and defined as "11". Positive threshold voltages are used for the states of "10", "01", and "00.”
• a program voltage is applied to the control gate and the bit line is grounded. Electrons from the p-well are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the cell is raised. To apply the program voltage to the control gate of the cell being programmed, that program voltage is applied on the appropriate word line. As discussed above, that word line is also connected to one cell in each of the other NAND strings that utilize the same word line. For example, when programming cell 224 of FIG. 2A, the program voltage will also be applied to the control gate of cell 244 because both cells share the same word line.
• Boost self boosting
• the unselected bit lines are electrically isolated and a pass voltage (e.g. 10 volts) is applied to the unselected word lines during programming.
• the unselected word lines couple to the unselected bit lines, causing a voltage (e.g. eight volts) to exist in the channel of the unselected bit lines, which tends to reduce program disturb.
• Self boosting causes a voltage boost to exist in the channel which tends to lower the voltage across the tunnel oxide and hence reduce program disturb.
• FIG. 2C shows an example of the self-boosting technique with a boosted channel 252.
• a NAND string is typically (but not always) programmed from the source side to the drain side, for example, from memory cell 228 to memory cell 228A.
• the programming process is ready to program the last (or near the last) memory cell of the NAND string, if all or most of the previously programmed cells on the string being inhibited (e.g. string 204) were programmed, then there is negative charge in the floating gates of the previously programmed cells. Because of this negative charge on the floating gates, the boosting potential doesn't get high enough and there still may be program disturb on the last few word lines.
• each of those transistors (244, 246, and 248) has a negative charge on their floating gate which will limit the boosting level of the self boosting process and possibly cause program disturb on cell 242.
• LLB Local Self Boosting
• EASB Erased Area Self Boosting
• LSB Local Self Boosting
• EASB Erased Area Self Boosting
• bit line for the cell being programmed is at ground and the bit line of the string with the cell being inhibited is at Vdd.
• the program voltage Vpgm (e.g. 20 volts) is driven on the selected word line.
• the word lines neighboring the selected word line are at zero volts and the remaining non- selected word lines are at Vpass.
• bit line 202 is at zero volts and bit line 204 is at Vdd.
• Drain select SGD is at Vdd and source select SGS is at zero volts.
• Selected word line WL2 (for programming cell 224) is at Vpgm.
• Neighboring word lines WLl and WL3 are at zero volts, and other word lines (e.g. WLO) are at Vpass. The same is shown in FIG. 2B for an 8-memory cell NAND string.
• EASB is similar to LSB with the exception that only the source side neighbor word line is at zero volts.
• FIG. 2D shows an example of EASB.
• WL4 is at zero volts, which cuts-off the channel and WL3 is at Vpass.
• Vpass is 7-10 volts. If Vpass is too low, boosting in the channel is insufficient to prevent program disturb. If Vpass is too high, unselected word lines will be programmed.
• GIDL occurs with a large bias in the junction and a low or negative gate voltage, which is precisely the case when the source side neighbor cell is programmed and the drain junction is boosted. GIDL will cause the boosted voltage to leak away prematurely, resulting in a programming error. GIDL is more severe with the abruptly and highly doped junctions, which are required as cell dimensions are scaled. If the leakage current is high enough, the boosting potential in the channel region will go down and there can be program disturb. The closer the word line being programmed is to the drain, the less charge is present in the boosted junction. Thus, the voltage in the boosted junction will drop quickly, causing a program disturb. Even if the leakage current is not high enough, electrons induced by GIDL are easily injected into the floating gate in a high electric field between the gate and the channel. It will also cause program disturb.
• the spacing between the select gate transistor (e.g., select transistor 230 in FIG. 2A) and the adjacent memory transistor (e.g., memory cell 228) is made wider to relax electric field concentration and to reduce WL-SG coupling noise.
• the select gate transistor e.g., select transistor 230 in FIG. 2A
• the adjacent memory transistor e.g., memory cell 2248
• FIG. 2F shows that the problem of GIDL at the end of the string still exists. For example, when Vpgm is applied to WLO and GIDL still occurs due to band-to-band (B-to-B) tunneling.
• FIG. 3 A is a block diagram of one embodiment of a flash memory system that can be used to implement the present invention.
• Memory cell array 302 is controlled by column control circuit 304, row control circuit 306, c-source control circuit 310 and p-well control circuit 308.
• Column control circuit 304 is connected to the bit lines of memory cell array 302 for reading data stored in the memory cells, for determining a state of the memory cells during a program operation, and for controlling potential levels of the bit lines to promote the programming or to inhibit the programming.
• Row control circuit 306 is connected to the word lines to select one of the word lines, to apply read voltages, to apply a program voltage combined with the bit line potential levels controlled by column control circuit 304, and to apply an erase voltage.
• C- source control circuit 310 controls a common source line (labeled as "C-source” in FIG. 3B) connected to the memory cells.
• P-well control circuit 308 controls the p- well voltage.
• Memory cells are erased by raising the p-well to an erase voltage (e.g. 20 volts) and grounding the word lines of a selected block.
• the source and bit lines are floating. Erasing can be performed on the entire memory array, separate blocks, or another unit of cells. Electrons are transferred from the floating gate to the p-well region and the threshold voltage becomes negative.
• the select gates (SGD and SGS) and the unselected word lines (e.g., WLO, WLl and WL3) are raised to a read pass voltage (e.g. 4.5 volts) to make the transistors operate as pass gates.
• the selected word line (e.g. WL2) is connected to a voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell has reached such level. For example, in a read operation, the selected word line WL2 is grounded, so that it is detected whether the threshold voltage is higher than OV.
• the state of the memory cell is detected by a sense amplifier that is connected to the bit line.
• the difference between whether the memory cell is erased or programmed depends on whether or not negative charge is stored in the floating gate. For example, if negative charge is stored in the floating gate, the threshold voltage becomes higher and the transistor can be in enhancement mode.
• FIG. 5B illustrates the lower page programming in an existing, 2-round programming scheme using the LM code.
• the fault-tolerant LM code essentially avoids any upper page programming to transit through any intermediate states.
• the first round lower page programming has the logical state (1, 1) transits to some intermediate state (x, 0) as represented by programming the "unprogrammed" memory state "U” to an "intermediate” state designated by (x, 0) with a programmed threshold voltage among a broad distribution that is greater than D A but less than DQ.
• the intermediate state is verified relative a demarcation DV A -

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• 2007
  • 2007-12-12 JP JP2009544161A patent/JP2010515199A/ja active Pending
  • 2007-12-12 WO PCT/US2007/087262 patent/WO2008082888A1/en active Application Filing
  • 2007-12-12 EP EP07855106A patent/EP2304733A1/en not_active Withdrawn
  • 2007-12-12 KR KR1020097010405A patent/KR20090106461A/ko not_active Ceased
  • 2007-12-20 TW TW096149041A patent/TW200849259A/zh unknown

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