TW200849259A - NAND flash memory cell array and method with adaptive memory state partitioning - Google Patents

Abstract

A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb. An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors. For example, in a memory designed to store 2-bit data, the cells adjacent both ends of a NAND string would each be configured to store one bit of the 2-bit data.

Description

200849259 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a non-volatile semiconductor memory of the type of flash EEPROM (Electrically Erasable Programmable Read Only Memory), and more specifically 'Structure and method for operating a reversed type memory cell array and handling stylized interference near the edge of a string. [Prior Art] Many commercially available non-volatile memory products are used today, especially in the form of small form factor cards that use an array of flash EEProm (Electrically Erasable and Programmable Read Only Memory) units. One example of a flash memory system uses an inverse structure that includes configuring a plurality of charge storage transistors to act as a series of memory cells sandwiched between two select gates. In contrast, the array has a plurality of memory cells (eg, 8, 16, or even 32) that are connected as a string of memory cells (reverse and string) to one bit line and one of the selected transistors through either end Between potentials. The subwires are connected to the control gates of the cells in different series strings. To program a flash memory cell, a stylized voltage is applied to the gate and the 5 GHz line is grounded, causing the threshold voltage of the cell to rise. Because a stylized voltage is applied to all of the cells connected to a word line, an unselected cell on the word line (which does not wish to be programmed) can be unintentionally programmed. The accidental stylization of unselected cells on the selected word line is called "stylized interference, and continuous efforts are being carried out" to improve the program technology of the memory unit so that more information can be stored efficiently. And avoid stylized 127626.doc 200849259. Therefore, high performance and high capacity non-volatile memory is usually required. In particular, there is a need for a compact non-volatile memory with enhanced read and program performance, which has a An improved processor that is compact, efficient, and highly suitable for processing data between such read/write circuits. [Invention] A reverse-type flash memory system is organized into inverse strings, each of which: Ο series The chain of the memory unit, and the selection of the two ends of the string =

The crystal is connected to a possible one or a source line. In particular, memory cells that are immediately adjacent to L and the ends of the string are susceptible to stylized interference: errors. Overcoming such errors with an adaptive memory state cutting scheme, in which each memory cell is typically cut to store multi-bit data, except for memory cells that are stored at opposite ends of a relatively small number of bits. . In this manner, the storage of relatively few bits in the memory cells immediately adjacent to and opposite the strings is sufficient to provide sufficient margin to overcome such errors. In a specific embodiment, one of the memory systems is designed to have two elements, and one unit formed by the two bits will be: the two bits:: one and the other ones < storage, /, 夂 and string One of the memory cells adjacent to one end, and the other of the two bits is stored in another memory cell adjacent to the other end. In another embodiment, wherein the memory system is designed to store three bits per unit, 14·-, a soap element formed by the two bits will be: one end memory stores the bit _ ^ 匕餸 early One of the ,^, and the other end memory unit stores the ''bit' of the bit. One advantage is that it is easy to modify an existing memory system to adjust the adaptive scheme of 127626.doc 200849259. For a 2-bit or 3-bit memory system, at most one additional memory unit needs to be added to an existing inverse string to maintain the same memory capacitance. Additional features and advantages of the invention will be apparent from the description of the preferred embodiments of the invention. [Embodiment] To clarify the understanding of the preferred embodiment, a general architecture and operation of a reversed string will be described. The particular architecture and operation of the preferred embodiment will be described with reference to the general architecture. General Description of the Inverse Structure Figure 1A shows a top view of a reverse structure in which a plurality of transistors in series are sandwiched between two selected gates. The series connected transistors and the selected gates are referred to as inverse and string. (Transistors and gates are also referred to as non-volatile storage elements.) Figure 1A shows a 4 memory cell inverse and string. Fig. 1B shows an equivalent circuit of Fig. 1A. 1/ The reverse and string shown in Figures 1A and 18 comprise four transistors 1〇〇, 102, 104 and 1〇 connected in series and sandwiched between a first selected closed pole 120 and a second selected gate 122. 6. The gate 12 is selected to connect the inverse string to bit line 126. Selecting gate 122 connects the inverse string to the source line. The gate 120 is controlled by applying the appropriate voltage to the control gate 120CG of the selection gate 120. Select gate 122 is controlled by applying the appropriate voltage to control gate 122CG of select gate 122. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. For example, the transistor 100 includes a control gate 100CG and a floating gate 1〇〇F(}. 127626.doc 200849259 The crystal 102 includes a control gate i〇2CG and a floating gate 1〇2FG. The transistor 104 includes a control gate. The pole 104CG and the floating gate 1〇4FG. The transistor 1〇6 includes the control gate 106CG and the floating gate 106FG. The control gate ioocg is connected to the sub-line WL3. The control gate 102CG is connected to the word line WL2, and is controlled. The gate 104CG is connected to the word line WL1, and the control gate 1〇6CG is connected to the word line WL0. Fig. 1C is a cross-sectional view of the reverse line 142. As shown in Fig. 1C, the P is reversed. A string of transistors (also referred to as cells or memory cells) are formed in the P-well region 140. Each transistor includes a stacked gate structure that is controlled by gates (100CG, 102CG, 104CG, and 106CG) and Floating gates (100FG, 102FG, 104FG and 106FG) are formed on the surface of the P well 14 on top of an oxide film. The control gate is located above the floating gate. One of the oxide layers separates the control gate from the floating gate. It should be noted that Figure 1C seems to indicate electricity. A control gate and a floating gate of the bodies 120 and 122. However, for the transistors 120 and 122, the control gate is connected to the floating gate. Memory cells (1〇〇, 1〇2, 1) The control gates of 〇4 and 106) form the word lines. The diffusion layers 13〇, 132, • 134, 136 and 138 are shared between adjacent cells, whereby the cells are connected in series to each other to form a reverse The N+ diffusion layers form the source and drain of each cell. For example, the N+ diffusion layer 130 serves as the drain of the transistor 122 and the source of the transistor 106, and the N+ diffusion layer 132 serves as the transistor. The drain of 6 is the source of the transistor 104, the N+ diffusion layer 134 is used as the drain of the transistor 1〇4 and the source of the transistor 1〇2, and the N+ diffusion layer 136 is used as the drain of the transistor 1〇2 127626.doc -10- 200849259 and the source of the transistor 100, and the N+ diffusion layer 138 is used as the drain of the transistor 100 and the source of the transistor 120. The N+ diffusion layer 126 is connected to the bit line of the inverted string At the same time, the N+ diffusion layer 128 is connected to a common source line of the multi-reverse and the string. It should be noted that although FIGS. 1A to 1C show the four memories in the inverse string. Unit, but the use of four transistors is only an example. A reverse string can have less than four memory cells or more than four memory cells. For example, some inverse strings will contain 8 memory. Units (hereinafter shown with respect to Figures 2B through 2F and f, described), 16 memory units, 32 memory units, etc. The discussion herein is not limited to the presence of any particular number of memory units in a reverse string. Figure 2A shows three inverted strings 202, 204 and 206 with more memory arrays of inverted strings. Each of the inverse strings of Figure 2A includes two select transistors and four memory cells. For example, the inverse string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226, and 228. The inverse string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246 and 248. Each string is connected to the source line by its selection transistor (eg, select transistor 230 and select transistor 250). A select line SGS is used to control the source side select gates. The various inverse and string are connected to the individual bit lines by selecting the selected transistors 220, 240, etc. controlled by the line SGD. In other embodiments, the select lines do not necessarily have to be shared. Word line WL3 is coupled to the control gates of memory unit 222 and memory unit 242. The sub-line WL2 is connected to the control unit of the memory unit 224 and the memory unit 244. Word line WL1 is coupled to the control gates of memory unit 226, memory unit 246, and memory unit 250. The word line WL is connected to the control gate of the memory unit 228 and the memory unit 248. As can be seen, each of the meta-lines and the individual anti-strings comprise a row of arrays of memory cells. The word lines (WL3, WL2, WL1, and WL0) include the array of columns, and as described above, each word line connects the control gates of each of the memory cells in the column. Fig. 2B shows an example of an 8 memory cell inverse and string. The extra word lines are shown with WL4SWL7 (for memory cells 222A through 228A) and have similar functionality as word lines WL0 through WL3. Each memory unit can store data (analog or digital). When storing a single element of a digital material, the range of possible threshold voltages of the memory cell is divided into two ranges, which are assigned logical data, 1" and,, 〇,,. In one example of a type of inverted flash memory, the voltage threshold is negative after erasing the memory cell and is defined as a logical "i". After a stylized operation, the threshold voltage is positive and is defined as logic, 〇". When the threshold voltage is negative and a read is attempted, the memory unit will be turned on to indicate the storage logic U - When the threshold voltage is positive and the try-read operation, the memory will not be turned on, and the indication stores the logic zero. A memory unit can also store the information (or, data) multi-level For example, a number of bits of poor material. In the case of multiple levels of stored data, the range of threshold voltages is divided into the number of levels of data. For example, if the four levels of information are stored, there will be four threshold voltage ranges assigned to the data values "1", 10", "01", and "00". In one example of a type-inversion memory, the threshold voltage after a erase operation is negative and is defined as u". The positive threshold voltage is used for, 10,,,,, 〇1,,,, , 〇〇" state. 127626.doc -12- 200849259 Examples of anti-type flash memory and its operation are provided in the following U.S. Patent/Patent Towels, all of which are incorporated herein by reference. U.S. Patent No. 5,570,315 5,774,397, 6,456,528 and 6,522,580. Stylized Interference When stylized-flash memory cells, a stylized voltage is applied to the control _ and the bit line is grounded. Will come from? The electrons of the well are injected into the floating gate. When electrons accumulate in the floating gate, the floating idler is less than π negative and rises to the threshold voltage of the cell. In order to apply the pass voltage to the control gate of the programmed cell, the stylized voltage is applied to the appropriate word line ρ as discussed above, and the word line is also connected to each of the same word lines. String - unit. For example, when the unit of program A is 224%, the stylized voltage is also applied to the control gate of unit 244 because the two units share the same word line. ^ There is a problem with the desire to stylize - the word on the word line and not programmatically connect to other units of the similar line, for example, when you want the stylized unit = 4 instead of unit 244. Since the stylized voltage is applied to the king unit connected to the sub-line, an unselected unit (unprogrammed unit) on the word line may be inadvertently programmed. For example, when stylizing unit 224, Cowley has no intertextualization unit 244. The accidental stylization of unselected cells on the selected word line is called, stylized interference, . The stomach can use several techniques to prevent stylized interference. In a method known as self-extension, the unselected bit lines are electrically insulated during stylization and a pass voltage (e.g., 10 volts) is applied to the unselected word lines. The unselected 127626.doc 200849259 coupler lines are coupled to the unselected bit lines, causing a voltage (e.g., 8 volts) to be present in the channels of the unselected bit lines, with a tendency to reduce stylized interference. Self-boosting causes a voltage boost to be present in the channel and tends to reduce the voltage across the oxide of the tunnel, thereby reducing stylized interference. Figure 2C shows an example of a self boosting technique using a boost channel 252. The hang (but not always) and the string are programmed from the source side to the drain side, for example, from the memory unit 228 to the memory unit 228a. When p the stylized program has been programmed to program the last (or near the last) Lv Yi recall unit, if all or most of the stylized prohibited strings (such as string 2〇4) have been previously A stylized unit has a negative charge in the floating gates of the previously programmed units. Because of this negative charge on these floating gates, the boost potential cannot be high enough, and there may be stylized interference on the last few digit lines. For example, when the unit 222 is programmed, if the units 248, 246, and 244 are programmed, each of the transistors (244, 246, and 248) has a negative charge at its floating gate and will limit itself. The boost level of the program is programmed and may cause stylized interference at unit 242. Local self-boosting (, LSB) and erased area self-boosting (f, EASB, f) The problem of self-boosting discussed above has been solved by two other schemes: 'According to local self-boosting ( , LSB") and erased area self-boost (EASB), both LSB and EASB attempt to isolate the channel of the previously programmed unit and the channel of the suppressed unit. For example, if the unit 224 of Figure 2A (or Figure 2b) is programmed, the LSB and EASB attempt to suppress the stylization in unit 244 by the channel of the isolation unit 2 and the previously programmed units (246 and 248). Using the LSB technique, the bit line of the stylized cell is grounded, and the bit line of the string with the suppressed cell is at VDD. 127626.doc -14- 200849259. The stylized voltage Vpgm (e.g., 20 volts) is driven on the selected word line. The word line adjacent to the selected word line is at zero volts and the remaining unselected word lines are at Vpass. For example, to view view 2A, bit line 202 is at zero volts and bit line 204 is at Vdd. The drain selects SGD at Vdd and the source selects SGS at zero volts. The selected word line WL2 (for the stylizing unit 224) is at Vpgm. The adjacent word lines WL1 and WL3 are at zero volts, and other word lines (e.g., WL0) are at Vpass. For an 8-memory unit inverse and string, the same situation is shown in Figure 2B. The EASB is similar to the LSB, where the example is that only the source side adjacent word line is at zero volts. Figure 2D shows an example of an EASB. When stylizing WL5, WL4 is at zero volts, it is off the channel, and WL3 is at Vpass. In a specific embodiment, the Vpass is 7 to 10 volts. If Vpass is too low, the boost in this channel is not sufficient to prevent stylized interference. If Vpass is too high, the word line will not be programmed. Gate Inductive Drain Leakage (GIDL) Although LSB and EASB provide an improvement in self-boosting, it also appears to be whether to program or erase the source side neighboring cell (the source side adjacent cell of cell 246 system cell 244) ) a question. If the source side neighboring cell is programmed, there is a negative charge on the floating gate of the adjacent cell on the source side. Apply zero volts to the control gate. Therefore, there is a highly reverse bias junction under the negatively charged gate which can cause gate induced drain leakage (GIDL). GIDL involves electrons leaking into the booster channel due to banding (B to B tunneling). GIDL occurs with a large bias voltage in the junction and a low voltage of 127626.doc -15-200849259 or a negative gate voltage, that is, when the source side adjacent unit is programmed and the drain junction is boosted The situation at the time. GIDL will cause the boosted voltage to leak early, resulting in a stylized error. GIDL is more severe with the abrupt and moderately doped junctions required to scale the unit size. If the leakage current is high enough, the boost potential of the channel region will go down and there may be stylized interference. The closer the stylized word line is to the buck, the less charge is present in the boosted junction. Therefore, the voltage in the boosted junction will drop rapidly, causing a stylized disturbance. Even if the leakage current is not high enough, it is easy to inject the GIDL-induced electrons into the floating gate in a high electric field between the gate and the channel. It will also cause stylized interference. Figure 2D shows an example of GIDL when Vpgm is applied to WL5, WL4 is at zero volts, and Vpass is applied to other word lines. It shows that the positive charge has leaked into the p-well and shows that the remaining electrons have been injected into the floating gate.

Ik further shrinks the wordline spacing to achieve smaller grain sizes, and more Q topics will occur in lithography, WL to SG coupling due to noise (coupling between word lines and select gates) and GIDL Some points such as stylized interference. For example, the WL-to-SG coupling capacitance will increase as the word line shrinks. This will cause a longer wait time before the coupled noise fades. At the same time, as the word line shrinks, the electric field concentration will become higher, and the GIDL error will be more prominent when stylized to locate the memory cells at the opposite ends of the string. In a prior approach, the spacing between the select gate transistor (e.g., select transistor 230 in FIG. 2A) and the adjacent memory transistor (eg, memory cell 127626.doc -16-200849259 228) It is wider to alleviate the electric field concentration and reduce the WL to SG coupling noise. However, it makes the length of the reverse string longer and runs counter to the hope of shrinking the grain size. At the same time, due to the sudden line/space change between SG and WL relative to WL to WL, a more severe lithography problem will result. U.S. Patent Publication No. US-2006-0198195-A1 discloses an improved self-boosting method for reducing the GIDL. This technique applies another voltage displayed by the VGP to a memory cell below the stylizing unit. This is shown in Figure 2E, where WL5 is programmed, VGP is applied to WL4 and zero volts is applied to WL3. In this way, the WL voltage (VPGM) around the selected WL is gradually reduced. For example, ¥卩〇]\/1(24¥)-VPASS(10 V)-VGP(4 V)-VISO(0 V). This lowers the GIDL while modulating WL1 through WLN, where N is the last word line. However, this technique fails when staging WL0 because there are no adjacent word lines other than the selected transistor side. Figure 2F shows that the GIDL problem at the end of the string still exists. For example, when Vpgm is applied to WL0, and GIDL still occurs due to tunneling to the band (B to B). U.S. Patent Application Serial No. 11/407,816, filed on Apr. 20, 2006, which is hereby incorporated herein by reference in its entirety in its entire entire entire entire entire entire disclosure A dummy memory cell is inserted between the memory cell at the end of the string and the selected gate at the location. The dummy memory cell will be such that its control gate is coupled to a dummy word line (WL). By controlling the bias voltage of the dummy WL, the GIDL can be lowered in the same manner as disclosed in US_2006-0198195-A1. At the same time, these dummy WLs can protect the noise between SG and WL. In order to reduce the GIDL on the drain side and the GIDL on the source side, 127626.doc 200849259 needs to add two dummy memory cells with two WLs at each end of the string. The dummy memory cells do not store any assets, and this has the disadvantage of further increasing the size of the inverse strings. In contrast, the adaptive memory state of the string is reversed and the type of the flash memory system is organized into a reverse string, wherein each of the chains is a chain of billions of cells, and the selection is made at both ends of the string. The crystal is connected to a possible one or a source line. In particular, memory cells that are immediately adjacent to both ends of the string are susceptible to errors caused by stylized interference.曰 In accordance with the general aspect of the present invention, an adaptive memory state cutting scheme is used to overcome errors at both ends of the inverse and the string. Generally speaking, the memory cells in the string are cut to store one or more pieces of data, and the memory cells of the two bits are stored in close proximity to the other cells. A relatively small number of bits are stored in the memory cells immediately adjacent to the ends of the string to provide sufficient tolerance to overcome such errors. For example, in a memory designed to store two bits per cell, the two bits: the fields are individually stored and stored in two memory cells immediately adjacent to each other. Flash Memory System: A block diagram of a flash memory system that can be used to implement the present invention. The memory cell array 302 is controlled by the row control circuit 304 and the column control circuit 3. The row control circuit and the control circuit 304 are connected to the bit line of the memory cell array 302, which is used to store the memory in the memory unit. 127626.doc -18- 200849259 : During the operation, a state of the memory cell is determined, and a potential level of the bit line is controlled to facilitate the stylization or to suppress the stylization. The dragon battery 6 is connected to the word lines to select the word line, the application read „, and the stylized electric waste combined with the bit line potential level controlled by the line (4) circuit 3〇4, And applying a wipe to remove power. The C-source control circuit 310 controls a common source line connected to the memory cells (labeled as "C_source in Figure 3B, and the vp well control circuit 3〇8 controls the p Well voltage. The data stored in the memory cells is controlled by the row control circuit 3〇4

For reading, the data input/output (4) 312 is output to the external ι/〇 line. The stylized f-storage stored in the memory cells is input to the data input/output buffer 3 12 via the external I/O lines, and is transmitted to the row control circuit 304. These external 1/0 lines are connected to controller 318. The command data for controlling the flash memory device is input to the controller: 18. The command data informs the flash memory what to do. The input: 7 is transmitted to the state machine 3 16, which controls the row control circuit, the column control circuit 306, the c-source control 31, the p_well control circuit, and the data input/output buffer $312. State machine 316 can also output the state of the flash memory, such as READY/BUSY or PASS/FAIL. The bit system & 3 1 8 is connected or connectable to a host system such as a personal computer, a digital camera or a personal digital device. It is in conjunction with a host to initiate, for example, a command to store the batting to or read from the memory array 302, and to provide or receive such material. Controller 318 converts such commands into command signals that can be interpreted and executed by command circuitry 314, 127626.doc -19- 200849259 The command circuits are in communication with state machine 316. Controller 318 typically contains buffer memory for writing to or reading user data from the memory array. An exemplary memory system includes an integrated circuit including a controller 318; and one or more integrated circuit chips each including a memory array and associated control, input/output, and state machine circuits. Of course, the trend is to integrate a system of memory arrays and controller circuits together on one or more integrated circuit chips. The memory system can be embedded as part of the host system or included in a memory card (or other package) that can be movably inserted into the host systems. The card may include the entire memory system (e.g., including the controller) or just a memory array with associated peripheral circuitry (where the controller is embedded in the host). Therefore, the controller can be embedded in the host or included in a portable memory system. Referring to Fig. 3B, an exemplary structure of the memory cell array 3A2 will be described. As an example, the description is directed to flash EEPR〇M, which is cut into ^024 blocks. At the same time, erase the data stored in each block. In one embodiment, the block is the smallest unit of cells that are simultaneously erased. In this example, there are 8,512 rows in each block, which are split into even and odd rows. The bit line 7L is also divided into an even bit line (BLe) and an odd bit line (BL〇). As a paradigm and a string of four memory cells.

Connect to c_source. For example, FIG. 3B shows a series connection to form a reverse one. Although each display includes four cells 127626.doc -20-200849259: during the stylization operation, a page WL2-., which selects the memory cell at the same time, is selected. , 4, 256). The selected memory cells have the same word line (for example, 丄 & the same kind of bit line (for example, even bit line). Therefore, it can take 5: take or privately 532 Bytes of data. Simultaneously read or The stylized byte group material forms a logical page. Therefore, one block can store at least eight stomachs. When each memory unit stores # two-dimensional data (for example, multi-level cells), one area The block stores 16 pages.

The memory unit (4) is erased by raising the well to the erase voltage (for example, the user) and grounding the word line of the selected block. The source and bit ',, the floating erase can be performed on the other memory array, the separate block or the other 70 of the unit; The electron system is transferred from the floating idle to the p-well region, and the threshold voltage becomes negative. In read and verify operations, the selected closed poles (lake and (10)) and unselected word lines (eg, WLG, WLmwL3) are raised to - read through voltage (eg, 4.5 volts) to cause the transistors to be treated as Operate through the gate. The selected word line (eg, milk 2) is connected to the voltage, and a bit of the voltage is specified for each read and verify operation to determine whether the threshold voltage of the memory cell of interest has reached such a bit. quasi. For example, the selected word line WL2 is grounded in the "reading" to (4) whether the threshold voltage is higher than 〇V. In the verify operation, for example, the selected wordline machine 2 is connected to 2.4 V to verify whether the threshold voltage has reached 2·4 v or another threshold level. The source and p well are at zero volts. The f-selected even bit line (BLe) is pre-charged to a level, for example, 〇 7 v. If the threshold voltage is higher than the read (four) level, then because of the non-conductive memory unit, off 127626.doc -21 · 200849259

The potential level of the even bit line (BLe) of the U note maintains the high level. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the even bit line (BLe) of interest is reduced to a low level, for example, less than 〇 because of the conduction memory cell. · 5 V. The state of the memory cell is detected by a sense amplifier connected to the bit line. Whether to erase or program the difference between the memory cells depends on whether a negative charge is stored in the floating gate. For example, if a negative charge is stored in the floating gate, the threshold voltage becomes higher and the transistor can be in an enhanced mode. The above erase, read and verify operations are performed in accordance with techniques known in the art. Therefore, those skilled in the art can verify many of the details explained.

Ar/c is an example of reading and stylizing a multi-state memory. Figures 4A through 4E and 5A through 5E illustrate two examples of multi-bit encoding for a 4-state memory. In a 4-state memory cell, the four states can be represented by two bits. An existing technology uses a 2-pass stylization to program such memory. The first pass stylizes a first bit (the next page bit). The same unit is then programmed in a second pass to represent a desired second bit (upper page bit). In order to not change the value of the first bit in the second pass, the memory state representation of the second bit is treated as the value of the first bit. Figures 4A through 4E illustrate the stylization and reading of *state memory encoded by a conventional 2-bit Gray code. The programmable threshold voltage range (the threshold window) of the memory unit is cut into four zones, representing an unprogrammed %" state, and three other incremental stylized states "A", "B" and "C ". The four 127626.doc -22- 200849259 districts are individually demarcated by the boundary threshold voltages DA, DB and Dc.

Figure 4A illustrates the threshold voltage distribution of the 4-state memory array when the mother uses a two-dimensional data of a conventional Gray code. The four distributions represent the population of the four memory states:, U,,,,, A", "B", and, c". Before staging a memory unit, erase it to its U, or "unprogrammed" state. As the memory unit is gradually programmed, the memory states "A", "B", and "C" are gradually reached. The Gray code uses the (upper element, lower bit) to specify "U,, as (1,1),,,A" is (1,0),,,B,,((〇,〇), Moreover, C" is (〇, 1). Figure 4B illustrates the following page stylization in an existing, 2-pass stylized scheme using the Gray code. For a page of parallel stylized cells, the upper and lower bits will form two logical pages, a logical lower page consisting of the lower bits, and a logical upper page composed of the upper bits. A first pass stylizes only the next page bit of the logic. By proper encoding, a subsequent, second pass stylization of a single page of the same page will program the logical upper page bits without resetting the logical lower page bits. The Gray code is a commonly used code in which only the bit changes when transitioning to the -adjacent state. Because of &, this code has the advantage of not requiring error correction because only one bit is involved. A general scheme for using the 袼Ray code "represents one, unprogrammed, condition: therefore, the erased memory state is caused by (on the previous page, next page 70) 1, 1) Representation. Any unit that stores a first 70th "0" of the next page of the logic, thus shifting its logical state 攸(X,1) to (礓(,〇), Where, X,, represents the upper-level, and does not matter the '' value. However, because A soil is not programmed for the upper-level, for consistency, 127626.doc -23- 200849259 can also "1" indicates "x". The (1, 〇) is logically converted into the record. Before the state is preceded by the (4) unit program, the value of the τ under the bit is represented by the memory = Figure 4Q - use the 袼 code The existing page in the existing 28 programming scheme is programmed. A second pass of the program is executed to store the bits of the logical upper page. It will only be stylized to require "”,, The units. After the first pass, the page in the page can be here in the logic state (1,

Lj υ or (1, 〇). In order to preserve the value of the page in the second pass, you must distinguish between I or "! "Under the bit value. For the transition from (1, 〇) to (〇, 〇), the suffix unit in the discussion is stylized to the memory state Τ. From (1 υ to (〇, 变 change, the memory unit in the discussion is stylized to the memory state) C”. In this way, during the reading, by deciding the stylized in a unit The memory state 'decodes the τ page bit and the previous page bit 0. The privateization is performed by alternately applying a _stylized pulse to the -page of the parallel memory cell. Or stylized verification to determine whether = to complete its task to its target state. When the process, ^ unit, even when continue to apply the stylized pulse to complete the program of the other units in the group When it is changed, it will be blocked or stylized to suppress 'to avoid further stylization. It can be seen from Figure 4Β and 4C······································· (乂verifyA'' indicates) to perform stylized verification. However, for the above page, it is necessary to perform stylized verification with respect to the state, B,, and, C". Therefore, the previous page verification will require, verifyB" and "verifyC," one or two passes 127626.doc 24 * 200 849 259 certificate, the individual phases of the threshold voltage Dc for such boundaries.

U (d) describes the 4 state memory = bit that is encoded by the Gray code: the required read operation. Because by (1, the encoded heart-like evil A) and the "B" encoded by (0,0) have both as their subordinates, when a memory unit is programmed to state &quot "A" or "B", when the lower bit is detected "0". Conversely, when the memory unit is not stylized and in the state "U" or program< to state"c&quot When the time is measured, the lower bit "1" is detected. Therefore, the next page read will require a 2-pass read, individually relative to the boundary threshold voltages DA and Dc. Figure 4E illustrates the The Gray code encodes the read operation required by bit 7G of the 4 state memory. It will require a read of the boundary threshold voltage DkreadB. In this way, it will detect that it has less than the program. Any cell of the threshold voltage is in the memory state ", and vice versa. When the second pass is stylized, the Gray code, 2-pass stylization scheme can become a problem. Example #, the upper page bit The meta is stylized as "〇, and the lower bit is "1" will cause a change from (1, metamorphosis) To (G, D. & requires that the memory unit is gradually programmed from "U" through "A" and "B" to "c". If there is a power interruption before the stylization is completed, then The memory unit will end in the state of the transition memory - for example "A". # When reading the memory unit, ''A' will be decoded into the logic state (丨, 〇). This gives the above and The lower one is not the correct result because it should be (〇, 1}. Similarly, if the stylized interrupt is reached when the "B" is reached, it will correspond to (〇, 〇). The code is correct, but the lower bit is still wrong. In addition, because of the possible unsynchronized state "u" from the 127626.doc -25- 200849259 until the possible change of the most stylized state "c", this code scheme has an emphasis on The effect of the potential difference between the charge levels of adjacent units stylized at different times. Therefore, it also increases the field effect between adjacent floating gates (''Yupin effect π). Figure 5Α to 5Ε illustrate another Logic code ("LM,, code") coded 4 state memory program And reading. This code provides more fault tolerance and mitigates the adjacent unit coupling caused by the Yupin effect. Figure 5A illustrates the 4-state memory array when each memory unit stores the two-dimensional data of the lmm code. The threshold voltage distribution. The LM code is different from the conventional Gray code shown in Fig. 7A, wherein for the state, A,, and, c,,, and so on are inverted. The LM" code has been disclosed in U.S. Patent No. 6,651,891, and it is advantageous to reduce the field effect coupling between adjacent floating gates by avoiding the stylized operation requiring a large change in charge. As will be seen in Figures 5B and 5C, each stylized operation results in a modest change in the charge of the charge storage unit, as is apparent from the modest change in the threshold voltage VT. The code is designed to program and read the lower and upper bits separately. When the lower bit is programmed, the threshold level of the unit may still be in the unprogrammed area, or moved to the middle and lower of the threshold window. The margin of any of the two zones is allowed to advance to a slightly higher level that does not exceed one quarter of the threshold window. Figure 5B illustrates an existing, two-round program using the LM code. The next page is stylized in the scheme. The fault-tolerant LM code basically prevents any upper page stylization from changing through any intermediate state. Therefore, the first round of the next page is stylized 127626.doc -26· 200849259 to make the logic state ( 1, i) transition to an intermediate state (x, 0), such as by stylizing the "unprogrammed" memory state "U" to (x, 〇) specified and having a broad distribution greater than DA but less than One of the stylized threshold voltages between Dc is represented by an intermediate grievance. During stylization, the intermediate state is verified against a boundary DVA. Figure 5C illustrates the existing, 2 rounds in use of the LM code. Stylized on the top page of the stylized scheme. Stylize the upper page bit In the second round p of "〇", if the next page bit is at "1, then by unsorting, the memory state "U" is stylized to the "quote" , the logic state (1, 丨) changes to (〇, 1). If the next page bit is at "〇", the logic state (7), 〇) is stylized from the "middle" state to "Β" Similarly, if the previous page is still in "Γ, and the next page has been programmed to "〇", it will require a transition from the intermediate state to (1,0), as by This, the intermediate "state" is represented by "c". Since the upper page stylization only involves stylization to the next adjacent memory state, there is not a significant amount of charge changing from one round to another. From "U" to a rough, intermediate, state, the page stylization system is designed to save time. Figure 5D illustrates the read operation required to identify the lower level τ of the 4-state memory encoded with the LM code. The decoding will look at whether the previous page has been programmed. If the previous page has been programmed, reading the next page will require a read of readB relative to the cutoff threshold DB. On the other hand, if the previous page has not been programmed, the next page is stylized to the , middle, state (Fig. 5B), and readB will cause an error. Instead, reading the next page will require a read of readA relative to the demarcation threshold voltage DA. In order to distinguish the 127626.doc • 27- 200849259 two cases, a flag ("lm" flag) is written to the previous page when the upper page is stylized. During a read, it is assumed that: The upper page has been programmed, and thus the -readB operation will be performed. If the LM flag is read, the assumption is correct and the read operation is performed. On the other hand, if the first read does not generate a flag Then, it will indicate that the upper page has not been programmed, so the next page will have to be read by a readA operation. Figure 5E illustrates the read required to identify the top state of the 4-state memory encoded with the LM code. Take the operation. As is clear from the figure, the upper page read will require a two-pass read of the coffee dA and readC, individually relative to the threshold voltages DA and Dc. Similarly, if not yet programmed On the previous page, the decoding of the previous page can also be confused by the middle "state. The LM flag will indicate whether the upper page has been programmed. If the upper page is not programmed, the reading will be poor. The material is reset to " 1 ", indicating that the previous page was not programmed. Figure 6A illustrates the effect of a conventional gidl sensing error between various memory cells in a string. This example shows a reverse string with 32 C/§ memory cells in series and associated with word lines WL0 through WL3 1. Each memory single 7G is cut to store one of four possible memory states (represented by 2 bits). Fig. 6A shows the threshold voltage of the four memory states, which is the memory cell of the one of the memory cells and the memory cell. Both of the three locations are adjacent to the select transistors (or gates). In particular, the memory cell that is extremely adjacent to the source of the string has its control gate connected to the word line WL0, and the memory bank 7L that is not extremely adjacent to the string has its control gate connected to the word line WL3. . The remaining memory cells are resident in the core region of the far-and-reverse string and are associated with the word line WL1SWL3〇. 127626.doc -28- 200849259 It will be seen from Fig. 6 that the normal distribution (middle) of the four memory states is given by the memory cells resident in the core regions (WL1 to WL30). However, due to the GIDL effect highlighted at the end of the inverse string, the distribution of the memory cells (WL〇) adjacent to the source selective transistor (bottom map) is shifted to a higher threshold voltage. This can generate an error, as for example, the shifted "01" state can be misread as a "00" state. Similarly, the same error affects the memory cell adjacent to the drain selective transistor ( WL3丨) (see the top figure) Figure 6B illustrates a memory state cut associated with each memory in a typical inverse of the string of Figure 6A. In the direction of the memory array, the given example is one 32-unit inverse and string. One of the memory banks forms a page opposite to the string in the direction of the column. A word line is coupled to all control gates of each memory cell along each column. ;, each reverse string will be presented with a word line nipple to WL31 plus a memory located in the opposite of the string - the second column of the selection transistor selection line SGS and coffee. One page of the memory unit Parallel to program or read. In one embodiment, one (4) page is formed by inter-row-column memory cells, and - (odd) pages are formed by a column of memory cells between odd rows. In another embodiment, a full page is made up of a column or a basin ^The memory unit of the continuous operation of the sickle is formed by 0. In the scheme shown in Fig. 6B, each memory unit is cut to store the four possible memory states - as shown by Figure 4A to the ship. The examples given in Figures 5A through 5E illustrate that the four possible memory states are encoded in two bits. The two logical bits can be represented as -lower bits 127626.doc -29- 200849259 ("L") And an upper bit ("u").囡 , , ,.,At mouth, one and every memory in the string. The early squad is used to store the information of the two bits, that is, "L/U,. Figure 7 illustrates the previous solution for introducing additional memory cells at the end of the memory subtraction in the string. Because these dummy memories are now in close proximity to the end of the selection transistor and the end of the string, it will pass:: Most of the coffee effect (see top and bottom). However, at:

The placement of the units should not be important as they are not used to store any information. At the same time, an intermediate voltage can be applied to the word lines of the dummy cells in a manner similar to the scheme proposed by us_2〇〇6_〇i98i95-Ait to mitigate the GIDL effect. Therefore, the memory cells connected to the boundary 131 to 131 will not be affected (see the middle figure). The month of the month is typical of the memory of each memory cell in the string. The sadness of the memory cell is similar to that of Figure 7A. The normal memory cells (WL0 to WL3丨) in the inverted string are each configured to store both the underlying and upper bits. This extra dummy unit will not be programmed. Fig. 7C illustrates how the memory of each of the memory cells in a typical inverse and the string is cut, wherein the addition of the two dummy cells is similar to that of Fig. 7A. The normal memory cells (WL0 to WL3丨) in the inverted string are each configured to store both the underlying and the upper bits of the two bits. Additional dummy cells at both ends of the memory cell chain will be stylized. Adaptive Memory State Cutting FIG. 8A illustrates a scheme for overcoming the gidl error of a terminal memory cell in accordance with a general embodiment of the present invention. Basically, 127626.doc -30- 200849259 requires a minimal change from the conventional situation shown in Figure 6A. The main difference is that the memory cells at the end of the inverse string are configured to store binary beakers instead of multi-state data. The end memory cells (eg, WL0 and WL32) cut their threshold window in two states, which are more open than the four state condition, so the additional tolerance will allow the two states to be distinguishable, regardless of the inverse 2GIDL sensing error at the end of the string. If the conventional inverse string is specified to have 32 units, each capable of storing one 2-bit data (32x2 = 64 bits per string), then the current scheme only needs to add an additional memory unit to the chain. So the same 64-bit capacitor is now available (31x2+2x1 bits per string;). Figure 8B illustrates a memory state cut of each memory cell in a typical inverse and string using the adaptive memory state cutting scheme of Figure 8A. Normally, the core memory cells (^¥1^1 to 1B 31) in the reverse string are configured to store both the underlying data and the upper bit. The two ends (WL0 and WL32) are each configured to store binary data, which has a greater tolerance than the normal condition. Figure 8C illustrates an alternate preferred scheme using the 2-bit lm encoding described in Figures 5-8E. In the LM encoding described in Figures 5A through 5E, the two bits can be separated by two passes. The first pass is used to program the lower logical bit, and the second pass is used to simultaneously program the bit on the same memory cell. The nature of the LM code causes the lower bit to be cut and has a wider tolerance than the upper bit or the combined two bits. Therefore, compared to the 1 bit, the lower bit is more stable in terms of interference. In order to obtain a minimal change from an existing Z-Study system, preferably, a programmatic use of the binary bits of the key 127626.doc • 31 - 200849259 unit uses the sub-bit (or page) below the code. Stylized. However, it will be appreciated that one of the binary bits is used to represent the bit element below the 2-bit LM code and the other binary bit is used to represent the bit above the 2-bit LM code. Figure 9 is a flow chart illustrating the adaptive memory cutting scheme. Step 300··providing a non-volatile memory having an array-memory-memory cell-charge storage 1 crystal organized into a memory cell having a source and a drain and a charge a storage element and a control gate, each of which has a source terminal and a terminal, and is formed by a series of charge storage transistors. The charge storage transistors are daisy-chained by a unit to The source of the adjacent charge storage transistor is switched to the source terminal by a source selection transistor, and can be switched to the 汲 terminal by a drain selection transistor; Step 310: The memory unit of the string is divided into a first group and a second group, and the memory unit of the second group is adjacent to the source drain selection transistor or the drain selection transistor, and the first a group of memory units is complementary to the second group; step 320 · storing a data of a predetermined number of bits in each memory unit of the first group; and * stepping "Every group of two - memory is stored less than The younger brother has a predetermined number of information on a second predetermined number of bits. In a specific embodiment, the memory system is designed to store two bits per cell, and a unit of the two bits will be: one of the two bits is stored in a memory adjacent to one end of the inverted string The body unit, and the other two of the two bits 127626.doc -32 · 200849259 are stored in another memory unit next to the other one. In another embodiment, the three-bit memory is stored, and the three-bit system is designed to store the second element of the wire unit, and the other _ terminal: =? one end memory unit stores the sigma. One of the bits is stored in the hidden body. All patents, articles, other public notices, documents and contents cited in this article are hereby incorporated by reference in their entirety, and are incorporated herein in their entirety by reference. Mouth, file or content and the basis of this document

The definition or use of terms in this document shall take precedence if there is a misrepresentation or use of any inconsistency or conflict in the term. The present invention has been described with reference to the specific embodiments thereof, however, it will be understood that the invention may be modified and modified without departing from the scope of the invention as defined by the scope of the invention and its equivalents. All references are incorporated herein by reference. [FIG. 1A is a top view of a reversed string. Figure 1B is an equivalent circuit diagram of the inverted string. Figure 1C is a diagram 1A is a cross-sectional view of the string. Figure 2A is a circuit diagram showing the triple-reverse and string. Figure 2B shows a stylized 8-unit inverse and string. Figure 2C shows the -8 unit inverse and string Image 2D of the self-boosting technique shows the GIDL effect of an 8-cell inverse and string. Figure 2E shows the application of the intermediate voltage when staging a memory cell. Figure 2F shows the GIDL effect when the word line WL is programmed. 127626.doc -33- 200849259 Figure 3A is a block diagram of one embodiment of a non-volatile memory system in which various aspects of the invention are implemented. Figure 3B shows an example of organization of a memory array. Figure 4A illustrates when each memory unit The use of a conventional memory state two yuan 4 Gray code data of the temporary memory array threshold voltage distributions. FIG. 4B illustrates the use of a Gray code of the existing, 2-pass under a stylized embodiment in stylized page. /

Figure 4C illustrates the stylization of an existing page using the Gray code. In the 2-pass stylization scheme, Figure 4D illustrates the read operation required to identify the bits below the state memory encoded by the Gray code. Figure 4E illustrates the f-gastric operation required to identify the upper bits of the #state memory encoded with the code. + Figure 5A illustrates the threshold voltage distribution of the 4-state memory array when each memory cell stores the two-dimensional data of the llm code.

Figure 5B illustrates the use of this! The ^^ code is in the existing, 2-round stylized scheme. ^ Figure 5C illustrates the top page stylization in the existing, 2-round stylization scheme using the LM code. Figure 5D, which illustrates the encoded 4-state memory of the encoded 4-state memory, is used to identify the read operations required to add the lower bits by the lm code. Figure 5E illustrates the read operation required to identify the bit in the lm code. Figure 6A illustrates the effect of GIDL sensing errors between various memory cells in a conventional inverse string. Figure 6B illustrates the memory state cut associated with each of the elements in the typical inverse and string of Figure 68. Fig. 7A illustrates a prior solution to the singularity of the singularity of the singularity of the singularity of the singularity of the singularity.卜 “Figures----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

L.J Figure 7C illustrates a typical inverse and a string of At < mother σ 忆 体 早 早 早 早 早 早 早 早 早 早 早 早 早 早 早 早 早 早 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳Figure 8 is a diagram showing a solution to overcome the gidl error of the end memory unit of the string according to one of the general embodiments of the present invention. π Please describe the memory state of each of the memory cells in a typical inverse and the system, using the adaptive memory state cutting scheme of Figure 8. Figure 8C illustrates an alternate preferred scheme for encoding from a 2-bit lm as described in the image. Figure 9 is a flow chart showing the adaptive memory cutting scheme. [Main component symbol description] Transistor Control gate Floating gate

100, 102, 104, 106 100CG, 102CG, 104CG, 106CG, 120CG, 122CG 100FG, 102FG, 104FG, 106FG 120 First selection gate First selection gate 127626.doc -35 122

200849259 126 128 130 , 132 , 134 , 136 , 138 140 142 , 202 , 204 > 206 220 > 230 > 240 > 250 222 > 224 > 226 , 228 > 242 > 244, 246, 248 , 222Α, 224Α, 226Α, 228Α 252 302 304 306 308 310 312 314 316 318

SGD, SGS WLO, WL1, WL2, WL3 bit line source line N+ diffusion layer p well area inverse and string selection transistor memory unit boost channel memory cell array row control circuit column control circuit P well control circuit C source Pole control circuit data input/output buffer command circuit state machine controller select line word line 127626.doc -36-

Claims (1)

200849259 X. The scope of application for patents: 1 · The method of storing data in a non-volatile recording dragon that has been organized into a counter-electrical system, each memory - charge storage transistor 'It has a source and a drain..." Components and - Control Interpoles Each of the inverse strings has a _ source terminal: a storage: extreme and is formed by a series of charge storage transistors, which From the unit's daisy chain to the adjacent charge storage electricity = ..., and can be switched to the source 钿 by a source selective transistor, and the method of selecting a transistor by a drain includes: Wu to 4 And extremes, the - the memory unit of each-reverse string is divided into - the first group and the first body::,: the memory unit of the group and the source selects the electro-crystal (4) Selecting the transistors adjacent to each other, and the memory of the first group is complementary to the group of the 7th group; the X group, and each of the brothers and the body units stores a first predetermined number of bits. Data; and: each memory unit of the second group stores less than the A pre-existing number of data of a second predetermined number of bits. 2. The method of claim 1, wherein the memory is stored in parallel by a memory unit having a common word line between pages A method of 0 to 2, wherein the page of the memory unit is initially removed by removing the electrical: charge storage element. The method of the term 1 of the month, the_predetermined bit The data of the number is 2 127626.doc 200849259 yuan. 5. The method of claim 4, wherein: ~ two memory units, the $1 memory unit of the second group contains w two records w _ data One yuan. _ early 疋 each used to store the two bits 6. The method of claim 4, wherein the name 2 bits 70 data consists of - logic first; The second group contains two first bits, and another - 70, one for storing the logic 7. The half of the request item 6 is used to store the second bit of the logic. Method, where 兮# is a unit, the two memory units are each u" and contain two memory singular bits. A method of storing the 2-bit data, such as the method of claim 1, wherein the first------------------ The memory unit of the two memory groups contains one or two bits of data. - 7 degrees early for storing the three bits. The method of claim 8, wherein: The bit data consists of a logical *--logic third bit; with &兀, - logical second bit and 4 second group containing two memory first digits, and another__Tian Fan' One is used to store the logic element. The method for storing the second and third bits of the logic 11·such as the request item 1〇, /, the second group containing the right A 3 has two memory sheets 127626.doc In 200849259, the two memory units I are used to store one or one logical bit of the 3-bit data. 12. f is a method of storing a poor material in a non-volatile memory having a microstructure and a matrix, each memory = electric storage transistor, having - source and - drain, one a charge storage element and a control gate, each of the reverse strings having a source terminal and a terminal electrode formed by a series of charge (four) transistors, the charge storage solar cells being dipped by a unit The daisy chain is connected to the source of the adjacent charge storage transistor, and can be switched to the source by the source-selective transistor (4) and can be switched to the gate terminal by a drain-selective transistor, the method comprising : The mother and the 5th memory unit of the string are divided into a first group and a first sheep, and the memory cell of the first group and the source selects the crystal, or the gateless selection transistor Having adjacent ones and the memory of the first group is complementary to a group of 5 haidi; configuring each memory unit of the first group to store data of a first predetermined number of bits; And configuring each memory unit of the second group to store less than the first pre- The number of data a second predetermined number of bits. The method of claim 12, wherein the storing is by parallel staging a page of memory cells having a common word line between the corresponding pages of one of the strings. The method of claim 13, wherein the page of the memory cell is initially erased by removing the charge from its charge storage element. 15. The method of claim 12, wherein the data of the first predetermined number of bits is 2-bit data. The method of claim 15, wherein the memory unit of the second group comprises two memory units, each of the two memory units for storing one bit of the two-bit data. 17. The method of claim 15, wherein: the 2-bit data consists of a logical first bit and a logical second bit; and the second group contains two memory cells' The logical first bit is stored, and the other is used to store the logical second bit. 18. The method of claim 17, wherein the 蝼篦_, 宁°海弟-group comprises two memory cells, each of which is for storing a location bit. #存桃W的一逻辑 19·If the method of claim 12, reset the metadata. The data of the predetermined number of bits in the frame is the method of claim 19, wherein the two memory cells, the two memory cells are =, and the memory cells contain data - or two bits. 7 is for storing the 3-bit 21. The method of claim 19, wherein: the bit data is composed of a logical first bit, _, a logical third bit; and a logical second bit and a third element The second group contains two memory unit ones 'and another one for storing the logic, storing the logic, the bait two and the third place 127626.doc 200849259 22. The method of claim 21, The second group contains two memory units, each of which is used to store one or one logical bit of the 3-bit data. 23. A non-volatile memory comprising: an array of memory cells organized into a plurality of memory cells, each memory cell being a charge storage transistor having a source and a pole a charge storage element and a control gate, each of which has a source terminal and a terminal electrode formed by a series of charge storage transistors, wherein the charge storage transistors are connected by a unit (10) to (4) The charge storage transistor is secret, and can be switched to the source source bat by the source selection transistor to the source J.-T, U, , 7 ,, and can be switched to the 藉 by a drain selection transistor. Extremely, and wherein: each of the reverse strings is composed of a memory group of a first group, a group, and a group of the group, wherein the second group is _f, The early 70 series is adjacent to the source selection transistor or the pole and the selection of the Thunder sergeant Lj k, and the first group of the immersed body unit is the opposite of the string. - A complement of a group of brothers of A T; used in the memory of the first group of 4 and eve. a storage means for storing data of a first predetermined number of bits in the unit; and for storing in each of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ One of the pre-existing numbers, the second sub-old, and the storage component of the data of the pre-clamping number. 24. The memory of claim 23, wherein the component used for storage is stored by flattening on one of the opposite sides of the string, and the memory having the common word line between the pages is *page of the * . 25. The memory of claim 24, wherein the page of the body is initially erased by causing the 127626.doc 200849259 to be removed from its charge storage. 2 6 · If you ask for the item 2 3, remember the body, where the first predetermined number of bits f # # 2 bit data. Double Mussels 2 7 · As requested in Item 2 6 ^ L, Body 'where the memory unit of the second group contains two memory units, ~1 yuan ~ two memory units For storing one bit of the two mussels. 28. The memory of claim 26, wherein the two-bit data consists of a logic, and that the two groups of the brothers have two nuances, one for storing the logic 70, and The other is used to store the second bit of the logic. 29. If the memory of claim 28, 1 - ^ 〇 ', the middle group contains two memory cells, and the two memory cells each use a bit. A memory for storing the 2-bit data. The memory of claim 23, wherein the first predetermined Ο 3 bit data. The memory of the U number is 31. The memory of the request item 3, wherein the memory of the second group... has two memory units, and the two records are one or two bits of the metadata. . L body early - each for storing the 3 bits 32. The memory of claim 30, wherein the 3 bit data is composed of a logic element, a bit, a logic, a logical third bit And a 7L and the second group contain two memory units, the first bit, and the other is used to store the logic for storing the second and third bits of the logic 127626.doc 200849259. 33. As requested in Item 32, Gan Yi. " "The second group of Lieutenant contains two memory singles, which are used to store the 3-bit data. Two logical bits. A variety of non-volatile memory, including: an array of memory cells organized into inverse and strings, each memory cell system - Thunder Chong six η How to store a transistor having a source pole, a charge storage element, and a control gate, each of the reverse strings having a source terminal and - not extreme and formed by a series of charge storage transistors, the charge storage The transistor is daisy-chained to the source of the adjacent charge storage transistor by a cell, and can be switched to the source terminal by a source selection transistor, and can be switched by a gate selection transistor. Up to the extreme, and wherein: each-reverse string consists of a --group and a second group of memory cells, wherein the second group of memory cells and the source-selective transistor Or the bungee selection transistor is adjacent, and the memory of the first group The unit is complementary to the second group of the string. The memory unit of the first group is configured to be programmable to one of a first predetermined number of memory states; and the second group The memory unit is configured to be programmable to a second predetermined number of memory states - the second predetermined number is less than the first predetermined number. < 35. The memory of claim 34, wherein In contrast, the _ corresponding page has 127626.doc 200849259 and read. 36. If the memory of the item 35, the bean " version of the Τ 己 己 体 兀 兀 兀 兀 该 该 该 该 该How to remove it from its charge component and be erased initially. 37. Memory 2 bit data as claimed in item 34. The data of the first predetermined number of bits is 38. The memory of claim 37, wherein the memory unit of the second group contains two memory cells, and the two memory cells store the two bits respectively One dollar of the data. 39. The memory of claim 37, wherein: a logical second bit of the binary data consists of a logical first bit; and the second group contains two memory cells, one of which The first bit of the logic is stored, and the other is used to store the second bit of the logic. 40. The memory of claim 39, wherein the second group contains two memory cells, each of which is used to store a logical bit of the 2-bit data. 41. The memory of claim 34, wherein the first predetermined number of bits of data is 3-bit data. 42. The memory of claim 41, wherein the memory unit of the second group comprises two memory units, each of the two memory units for storing one or two bits of the three-bit data. 43. The memory of claim 41 wherein: the 3-bit data consists of a logical first bit, a logical second bit, and a logical third bit; and 127626.doc 200849259 the second group The group contains two memory cells, one for storing the first bit of the logic and the other for storing the second and third bits of the logic 0. 44. The memory of claim 43, wherein the second The group contains two memory cells, each of which is used to store one or two logical bits of the 3-bit data. 127626.doc