TW200849259A - NAND flash memory cell array and method with adaptive memory state partitioning - Google Patents

NAND flash memory cell array and method with adaptive memory state partitioning Download PDF

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Publication number
TW200849259A
TW200849259A TW096149041A TW96149041A TW200849259A TW 200849259 A TW200849259 A TW 200849259A TW 096149041 A TW096149041 A TW 096149041A TW 96149041 A TW96149041 A TW 96149041A TW 200849259 A TW200849259 A TW 200849259A
Authority
TW
Taiwan
Prior art keywords
memory
bit
group
bits
data
Prior art date
Application number
TW096149041A
Other languages
English (en)
Chinese (zh)
Inventor
Farookh Moogat
Teruhiko Kamei
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/618,498 external-priority patent/US7489548B2/en
Priority claimed from US11/618,482 external-priority patent/US7489547B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200849259A publication Critical patent/TW200849259A/zh

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
TW096149041A 2006-12-29 2007-12-20 NAND flash memory cell array and method with adaptive memory state partitioning TW200849259A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/618,498 US7489548B2 (en) 2006-12-29 2006-12-29 NAND flash memory cell array with adaptive memory state partitioning
US11/618,482 US7489547B2 (en) 2006-12-29 2006-12-29 Method of NAND flash memory cell array with adaptive memory state partitioning

Publications (1)

Publication Number Publication Date
TW200849259A true TW200849259A (en) 2008-12-16

Family

ID=39277290

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096149041A TW200849259A (en) 2006-12-29 2007-12-20 NAND flash memory cell array and method with adaptive memory state partitioning

Country Status (5)

Country Link
EP (1) EP2304733A1 (enrdf_load_stackoverflow)
JP (1) JP2010515199A (enrdf_load_stackoverflow)
KR (1) KR20090106461A (enrdf_load_stackoverflow)
TW (1) TW200849259A (enrdf_load_stackoverflow)
WO (1) WO2008082888A1 (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100953065B1 (ko) 2008-03-14 2010-04-13 주식회사 하이닉스반도체 불휘발성 메모리 소자
JP5710474B2 (ja) * 2008-07-01 2015-04-30 エルエスアイ コーポレーション フラッシュ・メモリにおける読み取り側セル間干渉軽減のための方法および装置
JP5259481B2 (ja) 2009-04-14 2013-08-07 株式会社東芝 不揮発性半導体記憶装置
JP2013164888A (ja) 2012-02-10 2013-08-22 Toshiba Corp 半導体記憶装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3679970B2 (ja) * 2000-03-28 2005-08-03 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US7023739B2 (en) * 2003-12-05 2006-04-04 Matrix Semiconductor, Inc. NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
JP4398750B2 (ja) * 2004-02-17 2010-01-13 株式会社東芝 Nand型フラッシュメモリ
US7180775B2 (en) * 2004-08-05 2007-02-20 Msystems Ltd. Different numbers of bits per cell in non-volatile memory devices

Also Published As

Publication number Publication date
KR20090106461A (ko) 2009-10-09
JP2010515199A (ja) 2010-05-06
WO2008082888A1 (en) 2008-07-10
EP2304733A1 (en) 2011-04-06

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