TWI352404B - Providing local boosting control implant for non-v - Google Patents

Description

IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to non-volatile memory. [Prior Art] Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Electrically erasable and programmable read only memory (EEPROM) and flash memory systems are among the most popular non-volatile semiconductor memories. In the case of flash memory (also a type of EEpR 〇 M), the contents of the entire memory array or a portion of the memory can be erased in one step as compared to conventional full characterization EEPROMs. Both conventional EEPROM and flash memory utilize floating gates that are positioned above and insulated from the channel regions in the semiconductor substrate. The floating gate is positioned between the source region and the pole region. The control gate is provided on and insulated from the floating gate. The threshold voltage (Vth) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate to allow conduction between the source and the drain of the transistor before the transistor is turned on is controlled by the charge level on the floating gate. Some EEPROM and flash memory devices have two ranges of floating gates for storing charge' and thus, the memory elements can be programmed between two states (eg, erased state and stylized state). / Erase. Since each of the hidden components can store a data bit, the flash memory device is sometimes referred to as a binary flash memory device. 124970.doc 1352404 Multi-state (also known as multi-level) flash memory devices are implemented by identifying multiple distinct allowable/effectively programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value of the set of data bits encoded in the memory device. For example, when each memory element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the element can store two data bits. Typically, the stylized power applied to the control gate during the stylization operation is applied as a series of pulses whose magnitude increases over time. In a method _, the magnitude of the pulse is increased by a pre-step length (e.g., 0.2-0.4 V) with each successive pulse. The VPGM can be applied to the control gate of the flash memory component. The verification operation is performed during the period between the stylized pulses. That is, the programmed level of each of the components in a group of components that are programmed in parallel is read between consecutive stylized pulses to determine whether the programmed level is equal to or greater than the verification that the component is programmed. Level. For multi-state flash memory device arrays, a verification step can be performed for each state of the component to determine if the component has reached its data association verification level. For example, a multi-state memory element capable of storing data in four states may need to perform a verify operation for three comparison points. In addition, when programming an EEPROM or flash memory device (such as a NAND flash memory device in a NAND string), VpGM is typically applied to the control gate and the bit it is grounded, thereby enabling the cell or memory. When the electrons of the channel of the component (for example, the storage component) are injected into the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory 7L rises, so that the threshold voltage of the memory 7L is increased. The memory component is considered to be in the process 124970.doc 1352404. U.S. Patent No. 6,859,397, entitled "Source Side Self Boosting Technique For Non-Volatile Memory," and U.S. Patent Application Publication No.; "Detecting Over Programmed Memory" More information about this stylization can be found in 5/〇〇24939; the full text of both is incorporated herein by reference. However, due to the proximity of the non-volatile storage elements to each other, various forms of stylized interference have been experienced during stylization. In addition, this problem is expected to worsen with further scaling of NAND technology. Stylized interference occurs when the threshold voltage of a previously stylized non-volatile storage element is shifted due to subsequent stylization of other non-volatile storage elements. The boost technique attempts to solve the problem of boosting the channel region of the inhibited stylized NAND string to a high potential by connecting the channel region of the NAND string containing the storage element to be programmed to a low potential (such as 〇V). This problem. For example, the erase region self-boost (EASB) technique does not apply one of the NAND strings between the stylized region and the erase region while applying a high pass voltage (such as 8 V) on other unselected word lines. Apply a low enough voltage (usually 〇v) to the selected word line to isolate the boost channel. The modified EASB (REASB) is similar to the EASB, but applies a small voltage (such as 2·5 V) to the adjacent isolated word line. However, as the size is scaled down, stylized interference is still a serious problem even in the case of boosting, because the high electric field induced by the boosting band induces a tunnel leakage and/or gate induced buckling leakage ( GIDL). SUMMARY OF THE INVENTION The present invention addresses the above and other problems by providing a non-volatile storage system 124970.doc 1352404 system and method for reducing stylized interference. In one embodiment, a non-volatile storage system includes a substrate and at least one NAND string formed at least partially on the substrate. The substrate has a shallow ion implant implanted into the substrate along at least one NAND length, and at least one of the first spacers along the length of the at least one NAND string has a depth implanted into the substrate that is deeper than the shallow ion implantation Deep ion implantation. For example, at least a portion of the first interval can be adjacent to a select gate of at least one NAND string. Additionally, the second spacing in the substrate along the length of the at least one NAND string can have deep ion implantation. In this case, the first interval and the second interval may be adjacent to the first selection gate and the second selection gate of the at least one NAND. The substrate can have a p-type region in which ions are implanted. Deep ion implantation provides reduced channel boosting in the substrate (eg, due to higher channel capacitance), and deep ion implantation can be provided close to the need for boost reduction to prevent gate induced buckling leakage ( GIDL) and selective gate with tunneling (BTBT). In another aspect, a non-volatile storage system includes at least one NAND string at least partially formed on a substrate. At least one NAND string is in communication with a plurality of word lines extending between a first select gate and a second select gate of at least one NAND string. Additionally, the first portion of the substrate has a region raised implant ion level and at least one word line extends over the first portion and at least one other word line does not extend over the first portion. In another aspect, a non-volatile storage system includes a substrate, and the first portion of the substrate has a region raised implant ion level. Additionally, a collection of storage elements is formed at least partially on the substrate such that a 124740.doc 丄 - subset of the storage elements is formed at least partially on the first portion and other storage elements in the collection are not formed on the first portion. In another aspect, a method for reducing stylized interference in a non-volatile storage system includes: implanting a shallow ion implant along a length of a region of the substrate; and at least one of a length along a region of the substrate The first spacer implants the forehead into the substrate, which allows additional ions to be implanted into the substrate deeper than shallow ion implantation. The method further includes forming at least a portion of the NAND string at least partially over the area of the substrate such that at least the first portion 2 of the -NAND string is formed on the first interval. In this way, the regional ion level is provided in the first interval. For example, at least a portion of the first interval can be adjacent to a select gate of at least one NAND string. In another example, a method for reducing interference in a non-volatile storage system includes: implanting a region in a first portion of the substrate to raise an ion level; and forming at least partially on the substrate at least - NAND string. At least one NAND string is in communication with a plurality of word lines extending between at least one of the first select gates and the first select gate. In addition, at least one word line ^ extends on the first portion and at least one other word line does not extend in the first portion, and a method for reducing the "interference" in the non-volatile storage system includes: in the first part of the substrate The implanted region raises the ion level; and at least partially forms a collection of storage elements on the substrate. The first subset of the storage element is formed at least partially on the first portion. The square = step comprises at least partially Other storage elements in the collection are formed on a portion of the substrate that does not include the first portion. 124970.doc -9- 1352404 [Embodiment] The present invention provides a non-volatile storage system and method for reducing stylized interference. Providing deep ion implantation in a substrate near the end word line of the NAND string to selectively control boosting in the substrate near the end word line. An example of a memory system suitable for implementing the present invention uses NAND fast A flash memory structure comprising a plurality of transistors arranged in series between two select gates. The series connected transistors and select gates are referred to as NAND strings. A top view of a NAND string is shown in Fig. 2. The equivalent circuit is shown in Fig. 2. The NAND string depicted in Fig. 1 and Fig. 2 includes four transistors 1〇〇, 1〇2, 1〇4, and 106' which are connected in series and sandwiched. Between the first selection gate 120 and the second selection gate ι 22. The gate 120 is gated to the NAND string connection of the bit line 126. The NAND string connection of the gate 122 gate to the source line 128 is selected. A suitable voltage is applied to the control gate 120CG to control the selection gate 120. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a Control gate and a floating gate. The transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 1〇4 includes a control gate 104CG and a floating gate. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to (or is) the word line WL3, the control gate 102CG is connected to the word line WL2, and the control gate 104CG is connected to the word line WL1. 'And control gate 106CG is connected to word line WL0. In an embodiment 'electric The crystals 100, 102, 104, and 106 are each a storage element (also referred to as 124970.doc • 10·memory unit). In other embodiments, the storage element may include multiple transistors or may differ from FIG. 1 and The storage element depicted in 2. The selection gate 120 is connected to the selection line SGD. The selection gate 122 is connected to the selection line SGS. Figure 3 is a circuit diagram depicting three NAND strings. One of the flash memory systems using a NAND structure A typical architecture will include several NAND strings. For example, three NAND strings 320, 340, and 360 are shown in a memory array with more NAND strings. Each of the NAND strings includes two select gates and four storage elements. Although four storage elements are illustrated for simplicity, modern NAND strings can have up to, for example, 32 or 64 storage elements. For example, NAND string 320 includes select gates 322 and 327 and storage elements 323-326, NAND string 340 includes select gates 342 and 347 and storage elements 343-346, NAND string 360 includes select gates 362 and 367 and storage Elements 363-366. Each NAND string is connected to the source line by its select gate (e.g., select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. The various NAND strings 320, 340, and 3 60 are connected to respective bit lines 321, 341, and 361 by selecting transistors in the gates 322, 342, 362, and the like. These selective transistors are controlled by the anode selection line SGD. In other embodiments, the select lines do not necessarily need to be co-located within the NAND string; that is, different select lines can be provided for different NAND strings. Word line WL3 is coupled to the control gates of storage elements 323, 343, and 63. Word line WL2 is coupled to the control gates of storage elements 324, 344 and 364. Word line WL1 is coupled to control gates 124970.doc 1352404 of storage elements 325, 345, and 365. The pole line WL0 is coupled to the control gates of storage elements 320, 346, and 366. It can be seen that each bit line and each NAND string contains a storage element array J J or a set person + / 仃. The word lines (WL3, WL2, WL1, and WL0) contain an array. ° " Columns Each control node of each storage element in the pre-wire connection column • 16 or 'Control gate can be provided by the word line itself. For example, word line • j provides control gates for storage elements 324, 344, and 364. In practice, there can be thousands of storage elements on a word line. Every: storage components can store data. For example, when storing a digital bit:, the range of possible threshold voltages of the storage element is divided into two ranges, which are assigned logical information "and,,". In NAND-type flash memory - Example 10, Vth is negative after erasing the memory element, and is defined as 1 series "". The Vth after the stylization operation is positive and is defined as the logic VTH When negative and attempting to read, the storage element will be turned on to indicate that the logic "1" is being stored. When the VTH is positive and an attempt is made to read the operation, the storage element will not be turned on and the indication logic "0" is stored. The storage element can also store • multiple information levels', for example, multiple digital data bits. In this case, the range of VTH values is divided into the number of data levels. For example, if four information levels are stored, there will be four VTH ranges, which are assigned to the data values. ^,, ',, and '^' type memory. Example 2: Second divide operation: After The VTH is negative and is defined as 'u'. Positive V-values are used: 01" and _’00" The particular relationship between the material that is programmed into the storage element and the threshold wire of the component is considered to be the data encoding mechanism used to store the component. For example, the four countries' patents No. 6'222,762 and the US special shot (4) public case (10) describe the various data encoding mechanisms used in the multi-state flash storage element by 124970.doc 1352404, the full text of which is The manner of reference is incorporated herein. Examples of NAND type (4) memory and its operation are provided in U.S. Patent Nos. 5'386,422, 5,522, 5,576,315, 5,774'397, 帛6,46,935, 帛6,456,528. And each of these patents is incorporated by reference into a stylized (four) storage element, applying a staging voltage to the control gate of the storage element and grounding the bit line associated with the storage element. The electrons from the channel are injected into the floating gate. When electrons accumulate in the floating open, the floating gate becomes negatively charged and raises the Vth of the storage element. To apply a programmed voltage to the control gate of the memory element being programmed, a stylized voltage is applied to the appropriate word line. As discussed above, one of the storage elements in each of the NAND strings shares the same word line. Example

Application No. 6,522,580, in this article. In the meantime, when the storage element 324 of Figure 3 is programmed, the programmed voltage is also applied to the control gates of the storage elements 344 and 364. However, 'stylized interference can occur at the suppressed NAND string during the stylization of other NAND strings' and sometimes at the stylized nand string itself. For example, if NAND string 320 is suppressed and NAND string 3 40 is being programmed, stylized interference can occur at NAND string 320. By way of example, s '^' pass voltage VPASS is low, then the channel of the suppressed NAND string is not properly boosted, and the selected word line of the unselected NAND string can be unintentionally programmed. In another possible scenario, the boost voltage can be reduced by GIDL or other leakage mechanisms, resulting in the same problem. Other effects such as shifting of charge stored in a stylized storage element due to capacitive coupling between storage elements may also be problematic. Figure 4 depicts a cross-sectional view of a NAND string showing a stylized area and an erased area. This view is simplified and not to scale. The boost technique attempts to reduce the channel region of the inhibited stylized NAND string to a high potential by connecting the channel region of the NAND string containing the storage element to be programmed to a low potential (such as ΟV). The incidence of stylized interference. For example, the erase region self-boost (EASB) technique does not apply one of the NAND strings between the stylized region and the erase region while applying a high pass voltage (such as 8 V) on other unselected word lines. Apply a low enough voltage (usually Ο V) to the selected word line to isolate the boost channel. The modified EASB (REASB) is similar to the EASB, but applies a small voltage (such as 2.5 V) to the adjacent isolated word line. However, as the size is scaled down, stylized interference is still a serious problem even in the case of boosting, because the high electric field induced by the boosting band induces a tunnel leakage and/or gate induced buckling leakage ( GIDL). The NAND string 400 includes a source side select gate 406, a drain side select gate 424, and eight storage elements 408, 410, 412, 414, 416, 418, 420, and 422, all of which are at least partially formed. On a substrate 490, the substrate may include an insulating layer. Another source side select gate 402 for another NAND string is provided on the left side of the NAND string 400, and another drain side select gate 428 for another NAND string is provided on the right side of the NAND string 400. In one embodiment, the NAND strings on the right and left sides of NAND string 400 include storage elements that are programmed along with the storage elements on NAND string 400. A source supply line 404 having a potential Vsource is provided between 124740.doc -14 - select gates 402 and 406, and a bit line 426 having a potential Vdd (bit line) is provided to select gates 424 and 428 between. During programming, the programmed voltage VPGM is provided to the selected word line (e.g., the word line associated with one or more of the storage elements (in this case, storage element 420) to be programmed). In addition, it is recalled that the control gate of the storage element can be provided as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 may extend via control gates of storage elements 408, 410, 412, 414, 416, 418, 420, and 422, respectively. In the example provided, EASB is used to program NAND string 400, in which case 0 V is applied to the source side word line of the selected word line, ie, with storage element 418 (referred to as an isolated storage element). Associated with WL5 (known as the isolated word line). The pass voltage VPASS is applied to the remaining word lines associated with NAND string 400. Voltage VSGS = 0 V is applied to select gates 402 and 406 to keep it closed, and voltage VSGD (such as 2.5 V) is applied to select gates 424 and 428 to keep them open. Assuming that the staging of the storage elements along the NAND string proceeds from the storage element 408 to the storage element 422, when the storage element 420 is being programmed, the storage elements 408-418 will have been programmed and the storage element 422 will not be programmed. Chemical. Thus, depending on the stylized mode, all or some of the storage elements 408-418 will have electrons that are programmed into and stored in their respective floating gates, and the storage element 422 can be erased or partially programmed. Chemical. For example, a storage element may have been previously programmed in the first step of a two-step stylization technique. When the NAND string 400 is currently a suppressed NAND string, due to the VPGM applied to the word line WL6 associated with the storage element 420 and 124970.doc called 404 VPASS applied to other word lines, the potential of the channel of the substrate 49〇 Will be boosted. In particular, in a stylized situation, because the storage elements in the erased area 46 are still erased, the area of the channel associated with the still erased storage element (eg, erased area 460) is The stylized area 45〇 will experience a relatively high boost. In addition, the high boost region will be bordered by an isolated storage element (e.g., storage element 418) and a drain side select gate 424. In the case of EASB, a sufficiently low voltage is applied to the source side neighbors of the selected word line to isolate the stylized channel region and the erase channel region in the substrate. This technique is successful in effectively boosting the erase channel area. However, the high boosting channel with a small capacitance increases the electric field at the junction edge 472 of the storage element 418 associated with the isolated word line WL5. In addition, this phenomenon is stronger when the isolated word line is selected from the drain side of the gate closer than the source side select gate. Thus 'GIDL and BTBT can occur at junction 472, as further detailed below in connection with Figure 5. GIDL and BTBT may also occur at other locations 'such as the edge 474 of the drain side select gate 424 located at the other end of the high boost erase region 460. In addition, GDIL and BTBT can occur at the edge 470 of the source side select gate, especially when the LM data on WL1 is used to program the word line (e.g., wl〇) near the source side select gate. The storage element with LM data has undergone the first step of a two-step stylization process (see, for example, the threshold voltage distribution 2150 of Figure 21B). LM refers to the medium and low threshold voltage. GIDL and BTBT can also occur with other boost modes. Figure 5 depicts the occurrence of GIDL and Band-to-Band Tunneling (BTBT) in a NAND string channel near an isolated word line. The NAND string 400 and 124970.doc -16 - 1352404 portion 490 of FIG. 4 are shown in more detail, which includes storage elements 414, 416, 418, and 420, a private area 450, and an erase area 460. Additionally, details of the reliant component 414 include control gate 440, dielectric 442, floating gate 444, and insulator 446. WL3, WL4, WL5, and WL6 extend through the control gates of storage elements 414, 416, 41 8 and 420, respectively. A source/drain region is provided between the storage element and the select gate, including source/drain regions 430, 432, and 434. An example of GIDL and BTBT that may occur during a boost mode (such as EASB) and cause stylized interference. When the boost channel potential is high, the zeta field (E field) at the isolation storage element 418 (which has 0 V applied to its control gate) results in GIDL and BTBT at junction 472. In detail, an electronic hole pair is created as indicated by the example electron (represented by a small circle with a "" symbol) and a hole (represented by a small circle with a " symbol). Some of the generated hot electrons are accelerated by the high vertical field caused by VpGM and then injected into the floating gate of storage element 42. In addition, the program is closer to the lower word line of the source side selection gate than when the higher word line of the gate is selected near the drain side and via the memory element between the two terminals. Stylized interference induced by high electric fields may be worsened when storing components. At higher word lines, since the boosting efficiency is greatly improved due to the small channel capacitance and the boost is primarily controlled by the stylized voltage (VPGM), the high boost potential below the isolated storage element will cause GIDL induced heat. Carriers are injected into adjacent word lines. At the lower word line, the same happens under the source side select gate, which is typically biased to 〇Ve during stylization, as in the case of two passes through the stylization process. After the first step is partially stylized with wu associated with the storage element 410 of 124970.doc 17 1352404 (see, for example, Figure 21 ugly), the WLO is isolated from the upper channel region due to the closeness of the 1^1 being cut off. . Therefore, the channel region associated with WL〇 is boosted by VPGM. Figures 6 through 13 relate to a process for implanting additional ions in a substrate to control the boost. One aspect of the invention includes: subsequently forming on a substrate

In the NAND string, additional ions are deeply implanted into selected regions of the substrate close to the selected gate of the nand string. In detail, this additional ion implantation is mitigated by mitigating certain regions where additional ions are implanted. Boost to control the boost of the higher and/or lower word lines. In particular, after initial shallow ion implantation for controlling the threshold voltage of the storage element, only a selected area of the substrate near where the selected gate is to be formed is exposed by the lithography process. Next, additional ions are implanted deep into the substrate (e.g., shallower implants/wood for threshold voltage control) to increase the substrate below the higher and lower wordlines during boosting.

Channel capacitance. Additionally, ions diffuse laterally by subsequent thermal processes, such as annealing that is not a self-aligned process. When a string is formed on the substrate, a number of end word lines near the end of the NAND string (e.g., adjacent to the source side select gate and the gate side select gate) are located on the region having the region raised ion level. Thus, in one embodiment, the technique only provides reduced boost to the higher and lower word lines without affecting other word lines. Figure 6 depicts the implantation of a shallow ion implant in a substrate. The shallow ion implantation 61〇 is provided in the substrate 600, which may be (for example, a repellency type. The ion implantation may include, for example, side ions or indium ion H receptor type impurities are effective for suppressing the pressure increasing system. 纟-method The proposed implanting process is part of the p-well formation. In this case, the 'receptor type impurity is used for (9). It can also be used to enter the deep η well of 124970.doc •18· 1352404 (not shown in the figure) Well implanted deep into the dish or god. In one method, the crucible is implanted through an insulating oxide layer 620 (such as 'Si〇2) formed on the substrate. The insulating oxide layer 620 is implanted before. The shallow ion implant is used to control the threshold voltage of the storage element. Figure 7 depicts the formation of a photoresist structure on a substrate. In a possible method, photolithography can be used to form an example photoresist structure. 71〇 and 712. For example, an anti-(four) coating can be provided on the substrate-area, followed by a photolithography tool to pass a selected area to be implanted by deep ion implantation. The cover is exposed to light. The resist is then developed to remove the exposed areas. An ice ion implantation process is performed to provide deep ion implantation "ο, 820 (Fig. 8) in the substrate 69. Figure 8 depicts deep ion implantation in selected regions of the substrate. An approximate 80-150 keV can be used for additional Ion implantation provides boron implantation and a storage element height of approximately 150-300 001. Note that the implant energy can vary with the height of the storage element and should be expressed high enough to avoid affecting the threshold voltage of the storage element, but low enough to A compromise between the energies that affect the boost, that is, the ions should be implanted deep enough to affect the threshold voltage of the storage element, but shallow enough to affect the depth of the boost. Experiments to determine the optimal energy/depth. In one embodiment, the additional ions that provide the region-increased implant ion level are deeply implanted into the substrate than the shallow ion implants used to control the threshold voltage of the storage element. The threshold voltage is defined under relatively low bias conditions (such as during read/verify operations) so additional ion implantation should not affect this. On the other hand, the high voltage makes the depletion layer Deeply extending into the substrate, so high voltage operation 124970.doc -19· 1352404 (such as 'boost) can be affected by deep ion implantation β then remove photoresist structures 710 and 712, and perform other conventional processes, including Annealing the substrate 690 and forming a storage element on the substrate. For example, the storage element can be provided in a plurality of NAND strings that communicate with word lines extending across the NAND strings. Only an extra is required during formation of the p-well Masking step and ion implantation. Figure 9 depicts a top view of the substrate of Figure 8 showing a region with deep ion implantation. In one possible approach, photoresist structures 71 and 712 may extend across the substrate in the wordline direction. Under this condition, deep ion implantation 81〇 and 82〇 also extend in the interval in the word line direction along the length of one of the regions of the substrate. Figure 10 depicts a cross-sectional view of the substrate of Figure 8 showing a region with deep ion implantation and a NAND string formed on a substrate. An example string 1000 and partial views of the NAND strings 1〇1〇 and 1020 are provided. In practice, many NAND strings can extend in the bit line direction (shown) and in the word line direction. Again, this example provides a NAND string of eight storage elements. In practice, additional storage components can be provided in the NAND string. These strings of ^^^) are formed such that a number of end word lines are located on the deep ion implant. In this example, the control gate of the storage element can be provided as part of the word line (see also Figure 4). The control gate/word line is indicated by the shaded area of the storage element in Figure ι〇. The substrate has ions implanted along the length of the NAND string due to shallow implantation, except for one or more intervals along the length of the NAND string that have deep implanted ions to provide a region to increase the implant ion level. Additionally, at least a portion of the orbits having deep implanted ions are adjacent to the selected gates of the strings. In addition, a plurality of word lines extend across the NAND string such that a spacing of 124970.doc -20 - 1352404 deep implant ions extends under at least one of the word lines adjacent to the select gates of the nand string. For example, the end word line 1030 from the NAND string 1010 and the end word line 1〇4 from the NAND string 1〇〇〇 are formed on the deep ion implant 810. The end word line 1〇5〇 from the NAND string 1000 and the end word line 1〇60 from the NAND string 1020 are formed on the deep ion implantation 820. End word line 1040 can include WL0, WL1, and WL2 (see also FIG. 4), while end word line 1050 can include WL5, WL6, and WL7. In contrast, storage elements 1042 and 1044 and associated word lines in NAND string 1000, for example, are not formed on deep ion implantation. Thus, the individual first and second intervals in the substrate (provided by deep ion implants 810 and 820, respectively) extend below the end word lines 1 〇 40 and 1050, respectively, and the end word lines are adjacent to the nand string 1000, respectively. The source side selects the gate 1 〇〇6 and the drain side selects the gate 丨〇24. The first and second intervals in the substrate also extend below a subset of the storage elements of the NAND string 1 , which are associated with the end word lines 1〇4〇 and 1〇5〇, respectively. In addition, the selection gates 1002 and 1006 and the source supply terminal 1〇〇4 extend over the deep ion implantation 810, while the selection gates 1〇24 and 1〇28 and the bit line terminal 1026 are on the deep ion implantation 820. extend. Although the selection of the gate does not necessarily extend over deep ion implantation, this method facilitates the fabrication of the memory device. If the fabrication technique allows for more targeted ion implantation, then deep ion implantation just below the end word line is sufficient. In this example, a collection of three end word lines and corresponding storage elements are formed on regions of the substrate having regions of elevated ion levels. Therefore, as discussed, the channel capacitance of the end word line and the substrate below the corresponding storage element will increase by 124970.doc 1352404, and in other areas of the substrate that are not formed on the deep ion implanted word line or the sitter element The 'boost' will be reduced to mitigate the stylized interference attributed to gidl and BTBT. The channel capacitance refers to the capacitance between the channel of the substrate and the entire substrate. The number of end word lines formed on the deep ion implant can be one or more, and it can be optimized for a particular memory device based on, for example, an experiment. In addition, the number of source side end word lines formed on the deep ion implantation may be different from the number of the drain side end word lines formed on the deep ion implantation. Another variation is only for the source side or the drain side end word line to be formed on the deep ion implant. Figure 11 depicts a top view showing a substrate with a region of deep ion implantation. In this example, photoresist structures 11A, 11〇2, and 11〇4 are provided, and deep ion implants 1110 and 1112 extend between the photoresist structures in the word line direction. Figure 12 depicts a cross-sectional view of the substrate of Figure 11 showing a region with deep ion implantation and a NAND string formed on a substrate. Substrate I 〗 % includes deep ion implants 1110 and 1112» providing an example n AND string 1200 and partial views of NAND strings 12 10 and 1220. This example provides a NAND string of sixteen storage elements. The NAND strings are formed such that a number of end word lines are located on the deep ion implant. For example, end word line 1230 from NAND string 1210 and end word line 1240 from NAND string 1200 are formed on deep ion implant 1110. The end word line 1250 from NAND string 1200 and the end word line 1260 from NAND string 1220 are similarly formed on deep ion implant 1112. In contrast, the intermediate word line group 1245 and the storage elements between the end word lines 1240 and 1250 are not formed on deep ion implantation. For example, in NAND string 1200, end word line 1240 can include WL0, WL1, and WL2, and end 124970.doc • 22· 1352404 end word line 1250 can include WL13, WL14AWL15. The intermediate word line group -1245 may include WL3.WL12. The control gate/word line is indicated by the shaded area of the storage element. Figure 13 depicts (iv) a flow chart for the process of implanting additional ions in the substrate to control boost. Referring also to Figures 6 through 12, at step 13A, shallow ion implantation (Fig. 6) is performed in the substrate. At step 131, a photoresist is applied to the substrate at step 1320, removing portions of the photoresist, leaving (9) the structure of FIG. For example, a portion of the photoresist can be exposed to UV light in any situation where the photoresist material is to be removed, such that the exposed portion becomes more soluble in the developer. Note that this is an example of a lithography process that can be used to selectively implant ions into a substrate. Other methods are also possible. Deep ion implantation is performed at a selected interval of the substrate defined by the opening between the photoresist structures (Fig. 8) at step 1330. At step (10), a NAND string is formed on the substrate and the resulting traces and storage elements of the NAND string are placed on the deep ion implanted regions. Or it is possible to provide deep ion implantation after forming the nand string and the word line. Also, it is possible to provide shallow ion implantation after deep ion implantation, or to provide deep ion implantation and shallow ion implantation simultaneously or in a continuous process. Figure 14 illustrates an example of an array 1400 of NAND storage elements, such as the elements shown in Figures i and 2. Along each row, the bit line is connected to the no-extreme 1426 of the gateless select gate of the NAND string 1450. Each source column of the ^nand string can be connected to all source terminals of the source select gate of the NAND string. An example of an array of ΝΑΝ〇 124970.doc -23- 1352404 architectures and their operation is found in U.S. Patent Nos. 5,57,315, and MMM35. Dividing the array of storage elements into a large number of systems is common, and the block is a single block. For a flash block containing a minimum number of storage elements that are erased, the parent block is divided into a number of pages. In the example of the page & general, the individual pages can be divided into sections, and the minimum number of days in which the stylized operation is performed - the number of writes can be included. A data page is usually stored in a storage element column. One page can store = multiple or multiple sectors... sectors include user data and consumption data. The sub-materials usually include the calculations of the self-contained data. (4) Error correction 2 (10) The controller-part (described below) calculates the ECC when the data is programmed into the array, and when reading the f-material from the array Also check the coffee. Or 'restore ECC and/or other (4) materials on pages different from the user's profile to which they belong or even in different blocks. One of the sectors of the user profile is typically 512 bytes, which corresponds to the size of one of the sectors in the disk drive. The consumption data is usually an additional 16_2〇 bytes. The big page forms a block from any number of up to 32, 64, 128 or more pages from, for example, 8 pages. In some embodiments, a NAND string contains a block. In one embodiment, the P well is raised to an erase voltage (eg, '20 V) for a sufficient period of time while the source line and the bit line are floated, and the word line of the selected block is grounded. Erase the memory storage element. The unselected sub-line, the bit line, the select line, and the common source (c_s〇urce) are also raised to a significant portion of the erase voltage due to the capacitive face. Therefore, a strong electric field is applied to the tunneling oxide layer of the selected memory, and the data of the selected storage element is erased as the electrons of the floating gate are emitted to the substrate side (usually by the Buddha) Fowler-Nordheim tunneling mechanism). As the electrons move from the floating open pole to the p-well region, the threshold voltage of the selected storage element decreases. Erasing can be performed on the entire memory array, in a separate block, or on another unit of the storage element. Figure 15 is a block diagram of a non-volatile memory system using a single column/row decoder and a read/write circuit. The figure illustrates a memory device 1596 having read/write circuits for reading and programming a page of storage elements in parallel, in accordance with an embodiment of the present invention. Memory device 1596 can include one or more memory dies 1 598. The memory die 598 includes a two-dimensional storage element array 1400, a control circuit 151, and a read/write circuit. In some embodiments, the array of storage elements can be three-dimensional. The memory array 14 can be addressed by the column decoder 1530 via the word lines and via the row decoder 156. The fetch/write circuit 丨 565 includes a plurality of sensing blocks 1 $(9) and allows a storage element page to be read or programmed in parallel. Typically, the controller 1550 is included in the same memory chip 598 as the memory chip 598 In the memory device 1596 (eg, a removable memory card), the commands and data are transferred between the host and the controller 1550 via line 1520, and the controller and the memory die 1598 are via line 1518. The control circuit 15 10 cooperates with the read/write circuit 1565 to perform an S memory operation on the memory array 1400. The control circuit 1510 includes a state machine 1512, an on-chip address decoder 15 14 and power control. The module 1516. The state machine 1512 provides wafer level control of the hidden operation. The on-chip address decoder 1514 provides 124970.doc • 25-1352404 for the address used by the host or the memory controller to be decoded by the decoder 1530. And hard used by 1 56G Address interface between addresses. Power control module 1516 controls the power and voltage supplied to the word lines and bit lines during memory operation. In some embodiments, certain components of Figure 15 may be combined. In the design, one or more of the components (except storage element array 1400) may be considered as a management circuit. For example, one or more management circuits may include control circuitry 151, Any one or combination of state machine 1512, decoder 1514/1560, power control 1516, sensing block 15A, read/write circuit 1565, controller 1550, etc. Figure 16 is a dual column Block diagram of a non-volatile delta-recall system of a row decoder and a read/write circuit. Here, another configuration of the memory device 1596 shown in FIG. 5 is provided. In a symmetric manner in the array Access to the memory array 14 by various peripheral circuits is performed on the opposite side such that the density of the access lines and circuits on each side is reduced by half. Therefore, the column decoder is divided into column decoders 1530A and 1530B. And the row decoder is divided into a row decoder 156 a and 1560B. Similarly, the read/write circuit is divided into a read/write circuit 1565 connected from the bottom of the array 14 to the bit line and connected to the bit line from the top of the array 14 The read/write circuit 1565B. In this manner, the density of the read/write module is substantially reduced by half. The device of Figure 16 may also include a controller for the device of Figure 15 as described above. Figure 17 is a block diagram depicting one embodiment of a sensing block. The individual sensing blocks 1500 are divided into a core portion (referred to as sensing module 1580) and a common portion 1590. In one embodiment, there will be a 124970, d〇« • 26· 1352404 individual sensing module 1580 for each bit line and a common part 1590 for a collection of multiple sensing modules 1580 » In one example, the sensing block will include a common portion 1590 and eight sensing modules 1580. Each of the sensing modules in the group will communicate with the associated common portion via a data bus 1572. For other details, refer to the title "Non-Volatile" published on June 29, 2006.

U.S. Patent Application Publication No. 2/6/014, 0007, the disclosure of which is incorporated herein by reference. A sensing circuit 1570 is included that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. The sensing module 1580 also includes a bit line latch 1582 for setting The voltage condition on the connected bit line. For example, the predetermined state latched in the bit line latch 1582 will cause the connected bit line to be pulled to indicate a stylized suppression state (eg, Vdd). 〇Common part 1590 contains - processor 1592, a data latch set

And an I/O interface 1596 coupled between the data latch 1594 set and the data clearing block 152. Processor 1592 performs the calculations. For example, the function is to determine the data stored in the sensed storage element and store the determined data in the data latch set. The data latch 1594 set is used to store the data bits determined by the processor (10) during the read operation. It is also used to store the data bits entered from the data bus 1520 during the stylization operation. , ^ Moxibustion inferiority 兀 indicates the written data intended to be programmed into the memory. H 1594 & 1/0 interface 丨 596 provides data latch 1594 and asset bus 152 〇 124970.doc -27. 1352404

During operation during reading or sensing, the operation of the system is controlled by state machine 丨5丨2, which controls the supply of different control gate voltages to the addressed storage elements. As it steps through various predetermined control gate voltages corresponding to various memory states supported by the memory, the sensing module 158 can trip under one of the voltages and output The sensing module 1580 is provided to the processor 1592 via the busbar 1572. At this time, the processor 1592 determines the resulting memory state by considering the tripping event of the sensing module and the information about the control gate voltage applied from the state machine via the input line 丨593. The leaf is then used for the binary encoding of the memory state and the resulting data bits are stored in the data latch 1594. In another embodiment of the core portion, the bit line latch 1582 serves a dual purpose, both as a latch for latching the output of the sense module 1580 and as a bit line as described above. Latches.

It is contemplated that some embodiments will include multiple processors. In one embodiment, each processor 1592 will include an output line (not depicted in Figure 7) such that each of the output lines is wired-OR. In some = example, the line is reversed before it is connected to the line or line. This configuration allows for a decisive determination during the stylized verification process when the stylization process has completed, since the receive line or state machine can determine when all of the stylized bits have reached the desired level. For example, when each bit has reached its desired level, the logical zero of that bit will be sent to the line or line (or one by one inverted). When all bits output data (or reversed data), then the state machine knows to terminate the stylization process. Because each processor communicates with eight sensing modules, the state machine needs to read lines or lines eight. 124970.doc •28·

1352404 times, or adding logic to processor 1592 to accumulate the result of the associated bit line, such that the state machine only needs to read the line or line once. Similarly, by logically selecting the logical level, the global state machine can detect when the first bit changes its state and change the algorithm accordingly. During stylization or verification, the data to be programmed is stored in the data latch 1594 set from the data bus 1520. The stylized operation controlled by the state machine includes a series of stylized voltage pulses applied to the control gates of the addressed storage elements. "Each stylized pulse is followed by a readback (verification) to determine if the storage element has been programmed. To the desired memory state. Processor 1592 monitors the readback memory state relative to the desired memory state. When the two states coincide, processor 1592 sets bit line latch 1582 to cause the bit line to be pulled to indicate a stylized suppression state. Even if the stylized pulse appears on the (4)j gate of the storage element, the storage element that is difficult to connect to the bit line is further stylized. In other embodiments, the processor is initially loaded into bit line latch 1 582 and the sense circuit sets it to a suppressed value during the verify process. The data latch stack 1594 contains a data latch stack corresponding to the sense module. In one embodiment, there are three data latches per sensing module 158. In some embodiments (but not required), the data latch is implemented as a shift register 'converts parallel data stored therein to serial data for data bus 1520' and vice versa . In a preferred embodiment, all of the data latches corresponding to the read/write blocks of the m storage elements can be linked together to form a block shift register so that it can be transferred by serial transfer. Enter or output a data block. In particular, r reads / 124970.doc • 29· 1352404 writes the group of modules so that each of its data latch sets shifts the data sequentially into the data bus or out of the data stream. Rows, as if the data latches are part of a shift register for the entire read/write block.

Additional information regarding the structure and/or operation of various embodiments of non-volatile storage devices can be found in (1) published under the heading "Non-Volatile Memory And Method With Reduced Source" on March 25, 2004. U.S. Patent Application Publication No. 2004/0057287, filed on Jun. 10, 2004, entitled "Non-Volatile Memory And Method with Improved Sensing"20〇4/0109357; (3) US Patent Application No. 11/015,199, entitled "Improved Memory Sensing Circuit And Method For Low Voltage Operation", filed on December 16, 20, 2004; (4) 2005 The application titled "Compensating for Coupling During Read Operations of Non-Volatile Memory" is US Patent Application No. 11/099, 133; and (5) December 28, 2005, the title of the application is " Reference Sense Amplifier For Non-Volatile Memory " US Patent Application Serial No. 11/321,953. All of the five patent documents listed directly above are incorporated herein by reference. FIG. 18 illustrates a memory array to block for all bit line memory architectures or for parity memory architectures. An example of an organization. An illustrative structure of the array of storage elements 1400 is described. As an example, a NAND flash EEPROM that is divided into 1,024 blocks is described. The data stored in each block of 124970.doc •30· 1352404 can be erased at the same time. In one embodiment, the block is the smallest unit of the storage element that is simultaneously erased. In this example, there are 8,512 rows corresponding to the bit lines BL0, BL1, ..., BL8511 in each block. In an embodiment referred to as an All Bit Line (ABL) architecture (Architecture 1810), all of the bit lines of a block can be selected simultaneously during read and program operations. The storage elements along a common word line and connected to any of the bit lines can be programmed simultaneously. In the example provided, 'four storage elements are connected in series to form a _- NAND string. Although shown as including four storage elements in each NAND string, more or less than four (e.g., 16, 32, 64, or another number) may be used. One terminal of the NAND string is connected to a corresponding bit line via a drain select gate (connected to the select gate drain line SGD), and the other terminal is connected to the select gate source via a source select gate The pole line SGS) is connected to a common source. In another embodiment, referred to as an odd-even architecture (architecture 1800), the bit line is divided into even bit lines (BLe) and odd bit lines (BL〇 in odd/even numbers • 16-element line structure order) Stylized along the common word line and connected to the storage elements of the odd bit lines, and another programized along the common word line and connected to the storage elements of the even bit lines. The data can be programmed into different blocks at the same time. Data is read from different blocks. In this example, there are * 8,512 rows in each block, which are divided into even rows and odd rows. In this example, the displays are connected in series to form a NAND string. Four storage elements. Although shown to include four storage elements in each NAND string, more or less than four storage elements can be used. In the configuration of the read and program operation, select 4,256 at the same time. Stores 124970.doc -31 · 1352404 Save components. The selected storage elements have the same word line and the same class of bits such as even or odd. Therefore, 532 data bytes forming a logical page can be simultaneously read or programmed, and the memory-block can store at least eight logical pages (four word lines, each having an odd page and an even page) . For multi-state storage elements, when each storage element stores two data bits (where each of these two bits is stored on a different page), the block stores sixteen logical pages. Blocks and pages of other sizes can also be used. For an ABL or parity architecture, the storage element can be erased by raising the p-well to an erase voltage (e.g., 20 V) and grounding the word line of the selected block. The source line and the bit line are moving. Erasing can be performed on the (4) domain array, the individual block, or another unit that is part of the memory device. The floating gate of the electronic self-storage element is transferred to the p-well region, causing the VTH of the storage element to become negative. In the read and verify operations, the select closed (SGD and (10)) is connected to a voltage in the range of 2.5 V to 4.5 V, and the unselected word lines are made (eg, when WL2 is the selected word line) The selected word line is WL(), nipple, and machine 3) raised to a read pass voltage vPASS (typically in the 45 volt range) to operate the transistor as a pass gate. The selected word line WL2 is coupled to a voltage '(4) per-read and verify operation to specify the level of the voltage to determine if the Vth of the storage element of interest is above or below this level. For example, the selected word line WL2 can be grounded in a read operation for a two-bit quasi-storage element such that Vth is detected to be higher than 〇v. In the verify operation for the two quasi-storage elements, the selected word line is connected to 124970.doc -32· 1352404 (:) ο·8 ν' to verify that Vth has reached at least ^ 8 v. Source and P charge to:; will select the heart, for example). The position of "" is higher than the reading or verification of the word line and connected to the non-conductive storage element, and the potential level of the 70-line (BLe) is maintained at a high level with the storage element of interest. On the other hand, in reading or verifying the level, the conductive storage element causes the bit to decrease to a low #, less than G·5 V) at the potential level of the bit 4 (BLe) of interest. The state of the storage element can thus be tested by connecting a twisted comparator comparator sense amplifier. The above = verification operation is performed according to techniques known in the art. Therefore, many of the details explained can be changed by the familiar one. Other erasing, reading and verification techniques known in the art can also be used. = Instance set of riding threshold voltage distribution. For the case where each of the storage elements stores two bits, (4) an instance of the memory array is placed on the voltage knife. Providing the first threshold voltage distribution E for erasing the storage element is also the three thresholds of the stylized storage element, a, b, and C. In the embodiment t, the threshold voltage in the E distribution is negative. And the threshold voltage in the A, b & c distribution is positive. The per-differential threshold voltage range corresponds to a predetermined value of the set of data bits. The special relationship between the data stored in the library component and the storage component, and the data encoding mechanism used as the storage component is exemplified by the example 5, and the full text is cited by reference. U.S. Patent No. 6,222,762, issued December 16, 2004, and U.S. Patent Application Serial No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. mechanism. In one embodiment, Gray code assignment is used to assign data values to the threshold voltage range, • such that if the threshold voltage of the floating gate is erroneously shifted to its neighboring entity state, then only One yuan will be affected. An instance assigns "u " to the threshold voltage range E (state E), assigns "10" to the threshold voltage range a (state A), and assigns "〇〇 to the threshold voltage range B (state B) 'and will, 〇丨' is assigned to the threshold voltage range C (state C). However, in other embodiments, the Gray code is not used. Although four states are shown, the invention may also be used Other multi-state structures 'including those that include more or less than four states. For example, two read reference voltages Vra, Vrb, and Vrc are used for reading data from the storage element. Whether the threshold voltage of the storage component is higher or lower than Vra, Vrb and Vrc, the system can determine the state of the storage component. In addition, two verification reference voltages Vva, Vvb and Vvc are provided. When the storage and storage 7G program is stored When the state A is reached, the system will test whether their storage elements have a threshold voltage greater than or equal to Vva. When the storage element is programmed to state B, the system will test whether the storage element has a threshold voltage greater than or equal to Vvb. When staging storage elements to state C The system will determine if the storage element has its threshold voltage greater than or equal to Vvc. In an embodiment referred to as full sequence stylization, the storage element can be directly programmed from the erased state E to the stylized state Λ, B or Any of C. For example, the population of storage elements to be programmed may be erased first such that all storage elements in the population are in an erased state. Then, such as by Figure 124970.doc • 34- 1352404 23 A series of stylized pulses depicted by the control gate voltage sequence are used to program the storage elements directly into state A, B, or C. When some storage elements are being programmed from state E to state A, the other storage elements are State E program

Transition to state B and/or from state E to state C. When staging from state E to state C on WLn, the amount of charge on the floating gate below WLn is changed compared to the voltage change from state E to state A or from state E to state B. Maximum, so the amount of host coupling to the adjacent floating gate below WLn·1 is maximized. When staging from state E to state B, the amount of coupling to the adjacent swell gate decreases, but is still significant. When staging from state E to state A, the amount of coupling is even further reduced. Therefore, the amount of correction required to subsequently read each state of WLn-1 will vary depending on the state of the adjacent storage elements on WLn.

Figure 20 illustrates an example of a two-pass technique for multi-state storage elements that programmatically store data for two different pages (lower page and upper page). Four states are depicted: state E (ll), state A (1 〇), state B (〇〇), and state C (〇l). For state E, both pages store "i". For state a, the lower page stores "0" and the upper page stores "丨". For state B, both pages store "〇". For state C, the lower page stores "丨" and the upper page Save "〇". Note that although a specific bit pattern has been assigned to each of these states, different bit patterns can also be assigned. In the first stylized pass, according to the program to be programmed To the bit in the lower logic page to set the threshold voltage level of the storage element. 1 bit is logic 1 'and the threshold voltage is not changed because it is in the proper state because it has been erased earlier. As indicated by arrow 1100, if the bit to be programmed 124970.doc • 35- is 2404 〇 logical 〇 ", the threshold of the storage element is increased to state A. This causes the first stylization to end. The first stylization passes the setting of the temporary dust level of the storage element according to the position to be programmed into the upper logic page. If the upper logical page bit will store the logic "", no stylization occurs. Because the lower page Depending on the stylization of the element, the storage element is in one of the states E or A, and both states carry the upper page bit "". If the upper page bit will be logical, the threshold voltage is shifted. The first pass causes the storage element to remain in the erased state E, as depicted by arrow 2〇2〇, staging the storage element in the second phase, causing the threshold voltage to increase to state C. If the storage element is due to the first Stylized through and programmed into state A, as depicted by arrow 2010, the storage element is further programmed in the second pass, causing the threshold voltage to increase to state B. The result of the second pass is that 7 C pieces will be stored. Stylize to the state indicated to store the logic "〇 of the upper page without changing the information on the lower page. In both Figures 19 and 20, the amount of coupling to the floating gate on the adjacent word line depends on the final state. In an embodiment, the system can be configured to perform a full sequence of writes when sufficient data is written to fill the entire page. If insufficient data is written for the full page, the stylization process can program the lower page that is stylized with the received data. When subsequent data is received, the system will then program the upper page. In yet another embodiment, the system can begin writing in the mode of the programmed lower page, and if sufficient data is subsequently received to fill the entire (or large) knife storage element, the system can switch to full Sequence stylized mode. The title published on June 15, 2006 is "Pipelined 124970.doc • 36 - 1352404

Further details of this embodiment are disclosed in the U.S. Patent Application Publication No. 2006/0126390, the entire disclosure of which is incorporated herein by reference. 21A-21C disclose another process for programming non-volatile memory that is written to a particular page for a particular page by writing to a neighboring storage element for a particular page. Store components to reduce the effects of floating gates to floating poles. In an exemplary embodiment, the non-volatile storage element uses four data states to store two data bits for each storage element. For example, assume that state E is the erase state and states A, C are stylized. State E stores data 11. Status Α Stores data 01. Status Β Health data 1 〇. State c stores the data. This is an instance of non-Gray coding because the two bits change between adjacent states. It is also possible to use the data to other codes of the entity (4) state. Each storage element stores two data pages. These data pages are referred to as upper and lower pages for reference purposes; however, such pages may be given other indicia. Referring to state A, the upper page stores bit 0 and the lower page stores bits! . Referring to state b, the i page stores bit i and the lower page stores bit 〇. According to the reference agency, both pages store bit data. The stylization process is a two-step process. In the first step, the next page is stylized. If the lower page holds the data, the storage element state remains in state E. If the data is programmed to 〇' then the power-on threshold of the storage component is incremented so that the storage component is programmed to state B. Figure 21 shows the stylization of the health condition from state E to state B'. State B, which is the intermediate state 124970.doc • 37- 1352404 Therefore the 'verification point is depicted as Vvb, which is lower than Vvb. In one embodiment, after the storage element is programmed from state E to state, the adjacent storage elements (WLn+丨) in the nand string are then programmed with respect to the lower page of the storage element. For example, referring back to Figure 2, after the page below the stylized storage element 106, the lower page of the storage element 104 will be stylized. After the stylized storage element 1〇4, if the storage element 104 has a threshold voltage from state E to state B, the coupling effect of the floating gate to the floating gate will make the storage element 1〇6 look The threshold voltage is rising. This will have the effect of widening the threshold voltage distribution of state 至 to the distribution described as the threshold voltage distribution 125 图 of Figure 21B. This apparent widening of the threshold voltage distribution will be corrected when the upper page is programmed. Figure 2 1C depicts the process of stylizing the upper page. If the storage element is in the erased state E and the upper page remains 丨, the storage element will remain in state E. If the storage element is in state E and its upper page data is to be programmed to 〇, then the threshold voltage of the storage element will rise, causing the storage element to be in state A. If the storage element is at the intermediate threshold voltage distribution 215 and the upper page data will remain at 1, the storage element will be programmed to final state B. If the storage element is at the intermediate threshold voltage distribution 215 and the upper page data will become data 〇, then the threshold voltage of the storage element will rise 'so that the storage element is in the state depicted in Figures 21A-21C to reduce the floating gate to The coupling effect of the floating gates, because only page programming on top of adjacent storage elements will have an effect on the apparent threshold voltage of a given storage element. An example of an alternate status code is: when the upper page data is 丄, the self-distribution 215 is moved to the state C ’ and when the upper page data is 〇, the state b is moved. 124970.doc -38 - 1352404 Although Figures 21A-21C provide examples of four data states and two profile pages', the concepts taught can be applied to have more or less than four states and are different from two pages. Other embodiments. Figure 22 is a flow chart depicting one embodiment of a method for staging non-volatile memory. In one embodiment, the storage elements are erased (in blocks or other units) prior to programming. In step 22, the "data load" command is issued by the controller and received by the control circuit 15 1〇. In step 2205, the address data representing the page address is input from the controller or host to the decoder 1514. In step 2210, a stylized data page of the addressed page is entered into a data buffer for stylization. The data is locked in the appropriate set of latches. In step 2215, the "stylized" command is issued by the controller to state machine 1512. Triggered by the "stylized" command, the stepping pulses 231, 232, 233, 234, 235, etc. applied to Figure 23 of the appropriate word line will be locked in step 2210 The stored data is programmed into selected storage elements controlled by state machine 1512. In step 222, the programmed voltage VpGM is initialized to a start pulse (e.g., 12 V or other value) and will be maintained by state machine 1512. The program counter PC is initialized to 0. In step 2225, a first ^^(^ pulse is applied to the selected word line to begin programming the storage element associated with the selected word line. If the logic "〇" is stored in the indication corresponding storage In the specific data latch where the component should be programmed, the corresponding bit line is grounded. On the other hand, the right logic "1" is stored in a specific latch indicating that the corresponding storage element should remain in its 1J data state for the current month. , then connect the corresponding bit line to vdd to suppress stylization. 124970.doc •39- 1352404

In step 2230, the status of the selected storage element is verified. If it is determined that the target threshold voltage of the selected storage 7C has reached the appropriate level, the data stored in the corresponding data latch is changed to logic "1". If (4) the threshold voltage has not reached the appropriate level Quasi' does not change the data stored in the corresponding data latch. In this way, there is no need for the programming tool (4) to store the bit line of the logical τ in the corresponding data latch 11 of the bit line. The registers all store logic ''1', when the state machine (via the line or type mechanism described above) knows that all selected storage elements have been programmed. In step 2235, it is checked if all data is latched H storage logic "Bu Ruru &, the stylization process is completed and successful, because all selected storage elements are programmed and verified. In step 2240, report "pass" status. If it is determined in step 2235 that not all data latches are determined Store logic 1 to continue the stylization process. In step 2245, compare the program limits.

The value PCmax is used to check the program counter pc. An example of a program limit is 20; however, other numbers can be used. If the program counter pc is not less than PCmax, the stylization process fails and a "fail" status is reported in step 225, if the program leaf PC is less than PCmax', then VPGM is incremented by step size and the program counter pc is made in step 2255. Increment. After step 2255, the process returns to step 2225 to apply the next vPGM pulse. Figure 23 shows a voltage waveform 23A comprising a series of stylized pulses 2310, 2320, 2330, 2340, 2350 applied to a word line selected for programming, and the like. In one embodiment, the stylized pulses have a voltage Vpgm 'which starts at 12 V and increases incrementally (eg, '0.5 V) for each successive stylized pulse until a maximum of 21 V is reached 124970.doc -40- 1352404 There are verification pulse sets 2312, 2322, 2332, 2342, 2352, and so on. In some embodiments, there may be a verify pulse for each state to which the data is programmed. In other embodiments, there may be more or fewer verification pulses. The verify pulses in each set may have amplitudes of, for example, Vva, Vvb, and Vvc (Fig. 20). In a tenth embodiment, the data is stylized along the common word line to the storage element. Therefore, one of the word lines is selected for stylization prior to applying the stylized pulses. This word line is called the selected word line. The remaining word lines of the block are referred to as unselected word lines. The selected word line can have one or two adjacent word lines. If the selected word line has two adjacent word lines, the adjacent word lines on the drain side are referred to as the drain side adjacent word lines, and the adjacent word lines on the source side are referred to as the source side phases. The adjacent word line, for example, if WL2 of FIG. 3 is the selected word line, WL1 is the source side adjacent word line and WL3 is the drain side adjacent word line. Each block of the storage element includes a set of bit lines forming a row and a set of word lines forming a column. In one embodiment, the bit lines are divided into odd bit lines and even bit lines. As discussed in connection with FIG. 18, one time stylizes the storage elements along the common sub-line and connected to the odd bit lines, and the other stylizes the odd/even stylized storage elements along the common word line and connected to the even bit lines) . In another embodiment, the storage element is programmed along a word line for all of the bit lines in the block ("All Bits Threaded"). In other embodiments, bit lines or blocks may be divided into other groups (e.g., left and right, more than two groups, etc.). The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Many modifications and variations are possible in light of the above teachings. The embodiments described are chosen to best explain the principles of the invention and the practice of the application in the The present invention is preferably utilized. It is intended that the scope of the invention be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a NAND string. Figure 2 is an equivalent circuit diagram of a NAND string.

3 is a block diagram of an array of NAND flash memory elements. Figure 4 depicts a cross-sectional view of a NAND string showing a stylized area and an erased area. Figure 5 depicts the occurrence of gate-induced j: and pole leakage (GIDL) and band-to-band tunneling (BTBT) in the NAND string channel near the isolated word line. Figures 6 through 13 relate to a process for implanting additional ions in a substrate to control the boost.

Figure 6 depicts the implantation of a shallow ion implant in a substrate. Figure 7 depicts the formation of a photoresist structure on a substrate. Figure 8 depicts deep ion implantation in selected regions of the substrate. Figure 9 depicts a top plan view of the substrate of Figure 8 showing a region with deep ion implantation. Figure 10 depicts a cross-sectional view of the substrate of Figure 8 showing a region with deep ion implantation and a NAND string formed on a substrate. Figure 11 depicts a top view showing a substrate with a region of deep ion implantation. Figure 12 depicts a cross-sectional view of the substrate of Figure 11 showing a region with deep ion implantation and a 124970.doc - 42 · 1352404 NAND string formed on a substrate. Figure 13 depicts a flow diagram of a process for implanting additional ion feed pressure in a substrate. Figure 14 is a block diagram of an array of NAND flash memory elements. Figure 15 is a block diagram of a non-volatile memory system using a single column/row decoder and a read/write circuit. Figure 16 is a block diagram of a non-volatile memory system using a dual column/row decoder and a read/write circuit.

17 is a block diagram depicting one embodiment of a sensing block. Figure 18 illustrates an example of organization for all bit line memory architectures or memory array to blocks for a parity memory architecture. " Figure 19 depicts a collection of examples of threshold voltage distributions. Figure 20 depicts an example set of threshold voltage distributions. Figures 21A-21C show various threshold voltage distributions for the process of programming non-volatile memory. Figure 22 is a flow chart depicting an example of a process for programming non-volatile memory. Control switch for components Figure 23 shows an example waveform applied to a non-volatile storage during stylization. [Key Symbol Description] 100 Transistor 100CG Control Gate 100FG Floating Gate 102 Transistor 124970.doc -43· 1352404

102CG control gate 102FG floating gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 106CG control gate 106FG floating gate 120 first selection gate 120CG control gate 122 second selection gate 122CG control gate 126 bit line 128 source line 320 NAND string 321 bit line 322 select gate 323 storage element 324 storage element 325 storage element 326 storage element 327 select gate 340 NAND string 341 bit line -44- 124970.doc 1352404

342 Select Gate 343 Storage Element 344 Storage Element 345 Storage Element 346 Storage Element 347 Select Gate 360 NAND String 361 Bit Line 362 Select Gate 363 Storage Element 364 Storage Element 365 Storage Element 366 Storage Element 367 Select Gate 400 NAND String 402 source side select gate 404 source supply line 406 source side select gate 408 storage element 410 storage element 412 storage element 414 storage element 416 storage element 418 storage element 124970.doc -45 - 1352404

420 storage element 422 storage element 424 drain side select gate 426 bit line 428 drain side select gate 430 source/drain region 432 source/drain region 434 source/drain region 440 control gate 442 Dielectric 444 Floating Gate 446 Insulator 450 Stylized Area 460 Erase Area 470 Edge 472 Bonding Edge / Bonding 474 Edge 490 Substrate 600 Substrate 610 Shallow Ion Implant 620 Insulating Oxide Layer 690 Substrate 710 Resistive Structure 720 Photoresist Structure 124970.doc -46- 1352404 * 810 deep ion implantation. 820 deep ion implantation 1000 NAND string. 1002 select gate 1004 source supply terminal 1006 select gate 1010 NAND string 1020 NAND string 零 zero 1024 drain side select gate Pole 1026 bit line terminal 1028 select gate 1030 end word line 1040 end word line 1042 storage element 1044 storage element lu 1050 end word line 1060 end word line 1090 substrate * 1100 photoresist structure • 1102 photoresist structure 1104 photoresist structure 1110 Deep ion implantation 1112 deep ion implantation 1200 NAND string 124970.doc -47- 1352404 • 1210 NAND string 1220 NAND string • 1230 end word line 1240 end word line 1245 middle word line group 1250 end word line 1260 end word line 1290 substrate reference 1400 storage element array 1404 source line 1406 bit line 1426 no terminal 1428 source terminal 1450 NAND string 1500 sensing block 1510 control circuit stomach 1512 state machine 1514 on-chip address decoder • 1516 power control module • 1518 line 1520 line / data bus 1530 column decoder 1530A column decoder 1530B column decoder 124970. Doc -48- 1352404 - 1550 controller, 1560 line decoder • 1560A line decoder 1560B line decoder 1565 read/write circuit 1565A read/write circuit 1565B read/write circuit 1570 sense circuit reference 1572 Data Bus 1580 Sensing Module 1582 Bit Line Latch 1590 Common Part 1592 Processor 1593 Input Line 1594 Data Latch 1596 Memory Device / 1/0 Interface Stomach 1598 Memory Die 1800 Parity Structure 1810 All Bits Meta-line architecture 2300 voltage waveform 2310 stylized pulse 2312 verification pulse set 2320 program A set of verify pulses 2322 pulses 124970.doc -49- 1352404

2330 Stylized Pulse 2332 Verification Pulse Set 2340 Stylized Pulse 2342 Verification Pulse Set 2350 Stylized Pulse 2352 Verify Pulse Set BLO, BL1, BL2, Bit Lines BL3, BL4, BL5, BL8510, BL8511 BLeO, BLel, BLe2, Even Number Yuan line BLe4255 BLoO, BLol, BLo2, odd bit line BLo4255 SGD drain select line SGS source select line Vra, Vrb, Vrc read reference voltage Vva, Vvb, Vvc verify reference voltage WLO word line WL1 word line WL2 word line WL3 word line 124970.doc -50-

Claims (1)

ί 096135788 Patent Application Method, which includes: The side of stylized interference in a non-volatile storage system Into a shallow ion implantation; length and planting in the first and second intervals Medium; and One of the NAND strings and a first portion is formed directly on the first portion. The second portion is formed directly on the second spacer. 2. The method of claim 1, wherein: at least a portion of the [beta] interval is adjacent to one of the NAND strings. The method of claim 1, wherein: the plurality of word lines extend across the ΝΑΝΙ φ, the first interval being at least one of the plurality of word lines adjacent to one of the NAND _ select gates It extends directly below. 4. The method of claim 1, wherein: the plurality of non-volatile storage elements extend across the NAND string, the first interval being in the plurality of non-volatile storage elements adjacent to one of the NAND string selection gates The at least one non-volatile storage element extends directly below. 124970-1 〇〇〇7 i2.d〇, 1352404 丨0 修正Replacement page 5. The method of claim 1, further comprising: • implanting a deep ion implant along the length of the region of the substrate Into a second interval, the deep ion implantation system in the third interval is implanted deeper into the substrate than the shallow ion implantation, and a second portion of the NAND string is directly formed in the first Three intervals. 6. The method of claim 5, wherein: the first interval and the third interval are separated by the first interval along a length of the NAND string; and at least a portion of the first interval is adjacent to the NAND string One of the first selection gates, and at least a portion of the third interval is adjacent to the second selection gate of the NAND string, wherein the first and second selection gates are located at opposite sides of the NAND string β 7 The method of claim 1, further comprising: forming an additional NAND string on the substrate, the additional NAND string and the Nand string formed at least partially along the length of the region of the substrate being edge-to-edge configured And wherein the first interval is at (a) one of the additional Nand strings associated with the selected gate; and (b) at least partially along the length of the region of the substrate to form an associated select gate of the NAND string directly below extend. 8. A non-volatile storage system, comprising: a NAND string at least partially formed on a first and a second portion of a substrate, the NAND string and a first select gate and a second at the NAND string Selecting a plurality of word line communications between the gates, the first portion of the substrate having an area raised implant ion level, the second portion of the substrate 124970-1000712.doc 9. 10. 11. 12. 13 14. 15. ~ I-January fine-correction replacement page does not have a region raised implant ion level, at least - the word line of the plurality of word lines extends over the portion, and the plurality of words At least one other word line in the line extends over the second portion. The non-volatile storage system of claim 8, wherein: the at least one word line is adjacent to the first selection gate. The non-volatile storage system of claim 9, wherein: the first selection gate is located at one of the source sides of the string. A non-volatile storage system as claimed in claim 9, wherein: the first selection gate is located at one of the drain sides of the NAND string. The non-volatile storage system of claim 8, wherein: the first portion of the "hidden substrate" has a higher channel capacitance than the second portion of the substrate. A non-volatile storage system of claim 8 wherein: a plurality of word lines of the plurality of word lines extend over the first portion of the substrate. The non-volatile storage system of claim 8, further comprising: to > a plurality of additional Nand strings partially formed on the substrate, each of the plurality of NAND strings being communicated with the plurality of word lines The portion of the substrate extends below the plurality of additional NAND strings. The non-volatile storage system of claim 8, further comprising: a third portion of the substrate, the Nand string portion being formed on the third #刀[the third portion having a region raising the implanted ion position Preferably, at least one of the plurality of word lines extends over the third portion, the first portion being separated from the third portion by the second portion. 124970-1000712.doc 丄力2404 申:: 丨: July of the year 畑 Amendment replacement page 丨 16. The non-volatile storage system of claim 15 of the first and third portions of the substrate than the substrate The second part has a higher channel capacitance. 17. The non-volatile storage system of claim 15, wherein: the at least one other word line is adjacent to the second selection gate. 1 8. The non-volatile storage system of claim 17, wherein: the first select gate is located at one source side of the NAND string, and the second select gate is located at one of the drain sides of the NAND string At the office. • e 19. The non-volatile storage system of claim 8, wherein: the s-thoracic implant ion comprises at least one of a boron ion and an indium ion. 20. The non-volatile storage system of claim 8, wherein: the NAND string comprises a plurality of multi-level non-volatile storage elements. 21. The non-volatile storage system of claim 8, wherein: the first and second portions of the substrate have a shallow ion implantation. 22. The non-volatile storage system of claim 8, wherein the region increases the implanted ion level into the 怂A 卞伹 卞伹 卞伹 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于 基于One of the plurality of non-volatile storage elements is compromised between the threshold voltages and implanted to one of the depths of the first partial substrate. 23. The non-volatile storage system of claim 8, further comprising - an additional NAND string formed at least partially on the substrate, the additional NAND string and the 6 ho NAND string being configured in an edge-to-edge manner, the μ fairy string comprising A related selection pole, the additional N·string containing a related selection 124970-I0007l2.doc • 4· 1352404 _ hour) month / 3⁄4 correction replacement page • gate, and the first interval is completely related to the NAND string The select gate - and the associated select gate of the additional NAND string extend below. 124970-1000712.doc