TWI378456B - Method and system for reducing program disturb in non-volatile storage - Google Patents

Description

IX. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to a technique for non-volatile storage. [Prior Art] Semiconductor memory devices have become more and more popular for use in various electronic devices. For example, 'non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. It can erase the most popular non-volatile semiconductor memory of programmable read-only memory (EEPR0M) and flash memory system. Many types of EEPROM and flash memory utilize a floating gate that is over and insulated from a channel region within a semiconductor substrate. The floating gate is located between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge held on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate to allow conduction between its source and drain before the transistor is turned on is controlled by the charge level on the floating gate. An example of a flash memory system uses a NAND structure that includes a plurality of transistors arranged in series and sandwiched between two select gates. The series transistor and the select gate are called NAND strings. Figure 1 shows a top view of a NAND string. Figure 2 is an equivalent circuit thereof. The NAND strings shown in Figures i and 2 include four transistors 1 in series and sandwiched between a first (or drain) select gate 12A and a second (or source) select gate 122. 1, 2, 1, 4, and 1. Gate 120 is selected to connect the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. Select gate 12 I I24908.doc 1378456 is controlled by applying an appropriate voltage to select line SGD. The selection gate 122 is controlled by applying an appropriate voltage to the selection line SGS. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. For example, the transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. It should be noted that although Figures 1 and 2 show four memory cells within a NAND string, the use of four transistors is only an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings include 8 memory cells, 16 memory cells, 32 memory cells, and the like. The discussion herein is not limited to any particular number of memory cells within a NAND string. A typical architecture for a flash memory system using a NAND structure includes several NAND strings. Each NAND string is connected to the source line by its source select gate controlled by a select line SGS and is connected to its associated bit line by its drain select gate controlled by a select line SGD. . Each of the bit lines and the individual NAND strings connected to the bit line via a bit line contact include the rows of the memory cell array. A plurality of NAND strings share a bit line. In general, the bit lines are routed on top of the NAND strings in a direction perpendicular to the word lines and are coupled to one or more sense amplifiers. 124908.doc 1378456 These word lines (WL3, 7 columns. WL1 and WL0) contain memory cells of the memory array that can store digital data (called binary memory single binary digits) ° when storage - bit " 〇,,... In two ranges, the system assigns logical data and 0. In the case of the -NAND type flash dodge 1 and c, in the case of the technique ro-, the negative is a negative number and is defined as a logic "body early" - applying a negative volt to the control closed-pole and using a _ 衧 When trying to read, the memory unit will be turned on for 4 days without storing the general a _ —. (4) Tasting 4 When the read operation is performed, the memory unit will not be turned on, and the indication stores the logic zero. > - The body unit can also store multiple levels of information (referred to as a multi-state 5 memory) Unit). In the case of storing a number of Kangyin Zuyue and Houshixiu early Gongga, the range of possible threshold voltages is divided into the number of data levels. For example, if four levels of information are stored, the assignment is made. The four threshold voltage ranges are given to the data values "η","ι〇·,, 01", and "00" »in the -NAND type memory example, the threshold voltage is negative after an erase operation And defined as "u, the positive threshold voltage is used for "10", "01" and "00"NAND-type flash memory and related examples of its operation are provided in the following U.S. patents/patent applications, which are incorporated herein by reference: U.S. Patent No. 5,570,315, U.S. Patent No. 5,774,397, U.S. Patent No. No. 6,046,935, U.S. Patent No. 6,456,528, and U.S. Patent Publication No. US 2003/0002348, the disclosure of which is hereby incorporated by reference in its entirety in its entirety, in its entirety, in its entirety, its its its body. When staging a flash memory cell, apply a stylized voltage to the control gate and ground the bit line. Since the voltage difference between the channel of the flash memory cell and the floating gate 'from the channel region under the floating gate is injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell rises. To apply a stylized voltage to the control gate of the stylized unit, a stylized voltage is applied to the appropriate word line. The word line is also connected to a memory cell within each string of other NAND strings that utilize the same word line. A problem arises when it is desired to program a unit on a sub-line without programmatically connecting to other units of the same word line. Because the stylized voltage is applied to all of the memory cells connected to a word line connection, unselected memory cells (without stylized memory cells) on the same word line may be inadvertently programmed. The unexpected stylization of unselected memory cells on the selected word line is called "program disturb,. A number of techniques can be employed to prevent program interference. In a method called "self-boosting", the unselected NAND strings are electrically isolated from the corresponding bit lines and pass a voltage during stylization. (eg, 7 to 1 volt, but not limited to this range) is applied to the unselected word lines. The unselected word lines are coupled to the channel regions of the unselected NAND strings, causing a voltage (e.g., 6 to 10 volts) to be present in the channels of the unselected NAND strings, thereby reducing program disturb. Self-pressurization causes a boost voltage to be present in the channel, which reduces the voltage difference across the tunneling compound, thereby reducing program disturb. It should be noted that the boost channel voltage can vary to a large extent because the boost channel voltage depends on the value of the transfer voltage and also on the state of the memory cell when all memory cells in the 124908.doc 1378456 NAND string are erased. In the state, the boost is most efficient (the most channel voltage). Figures 3 and 4 depict nAND strings that are programmed and disabled using a self-boosting method. Figure 3 depicts a stylized NAND string. The NAND string of Figure 3 includes eight memory cells 304, 306, 308, 310, 312, 314, 316 and

318. Each of the memory cells of the eight memory cells includes a floating gate (FG) and a control gate (CG). A source/nomogram region 330 between the floating gates of the floating gates. In some embodiments, there is a p-type substrate (e.g., germanium), a -N well within the substrate, and a p-well within the well (not all described to increase the readability of the patterns). It should be noted that p-well can be used as a so-called channel implant, usually a p-type implant that determines or helps determine the threshold voltage and other characteristics of the memory #元. The source/drain regions 330 are formed in the n+ diffusion region in the p-well.

A gate 324 is selected on the one-drain side of one of the NAND strings. The drain select gate 324 connects the nand string to the corresponding bit by the bit line contact 334. The line selects the closed end 322 at the other end of the NAND string. A source select gate 322 connects the NAND string to a common source line 332. During programming, the memory cells selected for stylization receive a stylized voltage Vpgm on their associated word lines. The stylized electric avpgm can generally vary between up to volts. In a specific embodiment, the stylized voltage signal is a set of pulses whose amplitude is incremented with each new pulse. A (four) voltage of approximately 8 volts is a -transfer voltage) Vpass is applied to the control gate of the memory cell that is not selected for programming. The source select gate 322 is in an isolated state (four)' at the money pole (G) receiving G volts... low power plus 124908.doc 1378456 to the common source line 332 〇 This low voltage may be zero volts. However, the source voltage may also be slightly less than zero volts to provide better isolation characteristics of the source side select gate. A voltage Vsgd is applied to the drain side selection gate 324, which is typically in the range of the supply voltage Vdd (e.g., 2.5 volts). Zero volts is applied to bit contact 334 via the corresponding bit line to enable programmatic selection of memory cell 312. Channel 340 is at or near zero volts. Due to the voltage difference between the channel and the floating gate of the sigma cell 312, electrons tunnel through the gate oxide to the floating gate through a gate oxide (also commonly referred to as a tunneling oxide) by Fowler-Nordheim tunneling. Inside. The NAND string of Figure 4 describes the prohibition of stylizing one of the NAND strings. The NAND string includes eight memory cells 35, 352, 354, 356, 358, 360, 362, and 364. The NAND string also includes a drain select gate 366 that connects the NAND string to the corresponding bit line via the bit line contact 374 and a source select gate for connecting the NAND string to the common source line 332. . A source/drain region 370 between each of the floating gate stacks of the floating gate stacks. The NAND string of FIG. 4 has Vsgd applied to the gate of the drain select gate 366, volts applied to the gate of the source side select gate 368, and zero volts at the common source line 332 (or one) The slightly higher voltage p-bit line contact 374 receives the supply voltage vdd via the corresponding bit line to disable the stylized memory unit 358. When vdd is applied, the drain select transistor 366 will initially be in a conducting state 'so' The channel area underneath the NAND string will be partially charged to a potential (between volts and is generally equal to or nearly equal to Vdd). This charge is precharged. Precharge will be at the channel potential. Has arrived at 124908.doc -11· 1378456

Vdd or a lower potential (given by Vsgd-Vt) automatically stops, with % equal to the threshold voltage of the drain select gate 366. In general, during pre-charge, Vsgd is selected in such a way that Vsgd-Vt > Vdd, so that the channel region under the NAND string can be precharged to Vdd. After the channel has reached this potential, the gate electro-optic system is selected to be non-conducting or not conducting by lowering VSgd to a value similar to Vdd (e.g., 2.5 volts). Then 'the voltages Vpass and Vpgm are raised from zero volts to their individual final values (not necessarily simultaneously), and since the drain side select gate transistor 366 is in a non-conducting state', the channel potential will be due to the words The capacitive coupling between the line and the channel region begins to rise. This phenomenon is called self-pressurization. The channel region below the NAND string of Figure 4 is more or less uniformly boosted to a boost voltage. Since the voltage difference between the floating gate and the channel of the memory cell 358 has been reduced, stylization is prohibited. More information on stylized NAND flash memory, including self-pressurization techniques, can be found in U.S. Patent 6,859,397 ' "Source-side self-boosting technology for non-volatile memory" The entire content is incorporated herein by reference. It should be noted that Figure 4 shows a region 3 80' which includes a channel region on the surface of the substrate and a depletion layer below the region of the voltage-increasing channel (having an area of increased electric field due to channel boosting to a high voltage). The channel region is present below each of the floating gate/control gate stacks and between the source/drain regions 37A. Another attempt to resolve program interference is to erase the area self-boosting ("EASB"). The EASB attempts to isolate the channel of the previously stylized unit from the channel of the disabled memory unit. In the EASB method, the selected NAND string pass 124908.doc 1378456 track area is divided into two areas: a region that can contain a number of stylized (or erase unit) memory cells on the source side of the selected word line and the cells therein An area that is still erased or at least not in the final stylized state on the drain side of the selected word line. The two regions are separated by biasing to a word line of a lower isolation voltage (typically zero volts). Due to this separation, the two regions can be boosted to different potentials. In almost all cases, the drain side region of the selected sub-wire will be boosted to a higher potential than the source side region. Since the highest boost zone has the area of the eraser unit, this boosting method is called the erase zone self-boosting. Another boosting scheme (called the revision erase zone self-boosting (ReaSB)) is similar to EASB. A word line that receives an intermediate voltage (between Vpass and the isolation voltage) is received by a line between the word line receiving the isolation voltage and the selected word line. Although the above boosting method has reduced program disturb, it has not ruled out the problem. As the scaling of memory devices becomes faster and faster, the effects of program interference become larger. In addition, multi-state flash memory devices that require tight threshold voltage distribution may experience widening of such distributions. Certainly, the word line close to the select gates (especially close to the source select gate) may be affected by program disturb. An effect system gate initiation and pole leakage (GIDL) that may occur in a memory cell near the source select gate (eg, the memory cell TC 350 is close to the source select gate 368 of FIG. 4), which is also referred to as Tunneling between belts. GIDL causes electrons to be generated at the source select gate when the channel under the stylized NAND string is disabled (boost to a high voltage). Subsequently, the generated electrons are brought closer to the source gate in a stronger transverse electric field. ; The floating position of the memory unit is extremely fast. 124908.doc 1378456 speed. Some of the electrons of the electrons are energized to implant into the tunneling oxide under the floating gate or within the floating gate itself, thereby modifying the threshold voltage of the corresponding memory cell. Figure 5 shows a portion of the NAND string of Figure 4 with an amplification of the gate of the source select gate and a portion of the channel of the memory cell 350. Since a NAND string is boosted during a program inhibit operation (e.g., while other NAND strings are being programmed), a high voltage system is present in the channel region of the boosted nand string. This high voltage is also present at the junction region between the source select gate 368 (typically at 0 V) and the memory cell 35A near the source select gate 368. This bias condition may cause an electron hole pair, also known as GIDL. The borehole will reach the p-well zone 3 84. These electrons will move to the boost channel area. Generally, there is a lateral power % in the junction region between the source selection gate and the memory cell adjacent to the source side selection gate, because part of the junction (drain/source) is Depletion, due to the large voltage difference between the channel region below the memory cells and the channel region below the select gate. The electrons are accelerated in the electric field and gamma is capable of obtaining sufficient energy to implant a floating gate within the oxide or possibly even to the memory cell of the memory cell adjacent the source side select gate. In both cases, the threshold voltage of the corresponding memory cell will vary due to the presence of injected electrons' thereby thereby experiencing a risk of error in reading the memory cell near the source select terminal. : To reduce the effects of these GIDLs, the boost voltages νρ can be reduced to reduce the number of channels that are boosted during the inhibit operation. However, this may cause program disturbances due to insufficient grinding (as described above). Therefore, the choice of 124908.doc 1378456 when the voltage is used for Vpass is extremely important. SUMMARY OF THE INVENTION Techniques for reducing program disturb are described herein that include applying different boost voltages to unselected memory cells. A specific embodiment includes boosting a group of unselected non-volatile storage elements (or at least a portion of the unselected non-volatile storage elements) and applying one when adding the non-selected non-volatile storage element groups, groups Program signals to a specific # volatile storage component. The boosted unselected non-volatile storage S-piece group includes the particular non-volatile storage element, a set of non-volatile storage elements that have not been fully programmed due to a final erase procedure for the group, and others Non-volatile storage element. The increment includes applying one or more higher boost signals to the set of non-volatile storage elements and applying one or more different increaser signals to the other non-volatile storage elements, wherein the one or more The boost 彳s number is greater than the one or more different boost signals. Another embodiment includes applying a boost signal during a stylizing operation. • an unselected group of non-volatile storage elements and applying a program signal to the target unselected non-volatile storage element during the stylizing operation, The S* unselected non-volatile storage elements are not programmed due to the boost signal. The unselected non-volatile memory element group is on a common side of the target non-volatile memory element. One of the cohort adjacent non-volatile storage 7C pieces is adjacent to the target unselected non-volatile storage element. The target unselected non-volatile storage element and the unselected non-volatile storage element are all in series with each other. Applying a boost signal to the group includes applying a special boost I signal to the adjacent non-volatile storage element and applying a different boost 124908.doc -15· 1378456 signal to other non-volatile storage elements of the group . The particular rolling signal is higher than the different boosting signal. Other non-volatile storage elements of the group will not be stylized due to the last erasure of one of the groups. Another embodiment includes locally staging the non-volatile (four) memory elements connected to the -first word lines and localizing the non-volatile storage = elements connected to a second word line. The first word line is adjacent to the second word line with respect to a word line group, the word line group being associated with a non-volatile storage element=group. The non-volatile storage element group includes a connection to the The non-volatile storage elements of the first word line and the non-volatile storage elements connected to the second word line. Stylizing the non-volatile storage elements connected to the first word line, including applying a stylized signal to the first word line, applying a -first pass signal to the second word line, and applying one or more It = pass signals to other word lines of the word line group. The staging of the non-volatile storage elements connected to the first word line is performed after the non-volatile storage elements connected to the second word line are partially programmed. Another embodiment includes Applying a program signal to a selected word line for a non-volatile storage element group, applying a first transfer signal to a group of unselected word lines for the non-volatile storage element group, and applying a _ high pass The signal of the heart is transmitted to an adjacent word line (relative to the selected word line). The adjacent word line is used to complete the non-volatile storage element group of the non-volatile storage element group. . A second exemplary embodiment includes a plurality of non-volatile storage elements in communication with the non-volatile storage ones (four) (eg, word lines, 124908.doc • 16·1378456 70 lines or other control lines) And a circuit, including one or more voltage supply circuits, which are connected to the protection device, the sacred control line to provide a signal to the group of non-volatile storage elements, The programs described. [Embodiment] An example of a memory system suitable for implementing the present invention uses a NAND fast = memory structure. Other types of non-volatile storage devices can also be made. For example, a so-called tan〇s structure can also be used with the present invention.

(from -TaN.Al2 on m) (composed of a stacked layer of VSiN siQ2), which basically uses a memory cell within the nitride layer (rather than a floating closed-pole) for flashing. Another type of memory cell of the EEPR〇M system uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. Such units are described in Chan et al. , titled "Real Single-Crystal Oxide Nitride Oxide EEPR0M Device", IEEE Transactions on Electronic Devices, 胤 _ 8 Volume 'No. 3 ' March 1987, pp. 93-95. , 矽 and 矽 (ONO") form a three-layer dielectric sandwich and a conductive control gate and a half-conducting substrate surface on the memory cell channel by means of electrons from the cell The channel is implanted into the nitride internal programming unit to capture and store the electrons in a restricted region in the nitride. The stored charge then uses a detectable manner to change the threshold voltage of a portion of the cell channel. Hole is injected into the nitride to erase the unit See also Nozaki et al., "1-Mb EEPR〇M with Memory Units for Semiconductor Disc Applications" (IEEE Solid State Circuits, Vol. I, No. 4, April 1991, 497-5) 〇1 page), which illustrates a similar unit configured with a split gate 124908.doc 1378456, in which a doped polysilicon dream gate extends over a portion of the memory monopole channel to form a separate select transistor. The entire content of the article is incorporated herein by reference. In Section 12 of WilHam DB η 幻 Ε 如. Edited by the Institute: Nonvolatile I Conductor Memory Technology " Yangqiu Press, 1998) The stylized techniques mentioned are also described in this section for application to dielectric charge trapping devices. Other types of memory cells can also be used. Figure 6 illustrates a memory device 396 having read/write circuits for parallel read and stylized-page memory cells in accordance with an embodiment. Memory device 396 can include one or more memory dies 398. The memory crystal 398 includes a two-dimensional memory cell array 4A, a control circuit 41A, and a read/write circuit 465. In some embodiments, the memory cell array may be two dimensional. The memory array 4 can be addressed by a word line via column decoder 43 and a bit line via row decoder 460. The read/write circuit 465 includes a plurality of sensing blocks 5 〇〇 and allows parallel reading or programming of a memory unit page. A controller 45A can be included in the same memory device 396 (e.g., a removable memory card) as the one or more memory dies 398. Commands and data are transferred between the host and controller 450 via line 420 and between the controller and one or more memory dies 398 via line 4 1 8 . Control circuit 410 cooperates with read/write circuit 465 to perform memory operations on memory array 400. The control circuit 4 includes a state machine 412, an on-chip address decoder 414, and a power control module 416. The state machine 4121⁄4 is used for wafer level control of memory operations. The on-chip address decoder 124908.doc .〇 1378456 provides an address interface between the address used by the host or a memory controller and the hardware address used by decoders 43 and 460. Power control module 416 controls the power and voltage supplied to the word lines and bit lines during memory operation. In one embodiment, the power control module includes one or more voltage supply circuits that can receive a substrate voltage (e.g., a Vdd power supply or other voltage) and generate any of the voltages described herein. An example of a voltage supply circuit is a charge pump. Some components of the components of Figure 6 may be combined in some embodiments. In various designs, one or more of the components (alone or in combination) of the components of Figure 6 can be considered a management circuit in addition to the memory cell array. For example, a management circuit can include any of control circuit 41, state machine 412, decoder 414/460, power control 416, sensing block 5, read/write circuit 465, controller 450, and the like. Or a combination. FIG. 7 illustrates another configuration of the memory device 396 of FIG. The peripheral memory access memory arrays 4 are implemented in a symmetrical manner on opposite sides of the array such that the density of access lines and circuitry on each side can be halved. Therefore, the column decoder is divided into column decoders 43a and 43B and the row decoder is divided into row decoders 460A and 460B. Similarly, the read/write circuits are divided into a read/write circuit 465A connected from the bottom to the bit line and a read/write circuit 465B connected from the top of the array 400 to the bit line. In this way, the density of the read/write modules is substantially halved. The apparatus of Figure 7 can also include a controller as described above with respect to the apparatus of Figure 6. Figure 8 is a block diagram of a different sensing block 5, which is divided into a core portion of 124908.doc 1378456 (referred to as a sensing module 480) and a common portion 490. In one embodiment, there is a separate sensing module 48 for each bit line and a common portion 49 for one of the plurality of sensing modules 480. In one example, a sensing block will include a common portion 49A and eight sensing modules 480. Each of the sensing modules within a group will communicate with an associated common portion via a data bus 472. For further details, please refer to the U.S. Patent Application Serial No. 11/26,536, filed on Dec. 29, 2008, entitled "Non-Volatile Memory and Common Processing Methods for Sensing Amplifier Sets", The entire content is incorporated herein by reference. Sensing module 480 includes sensing circuitry 47 that determines whether a conduction current in a connected bit line is above or below a predetermined threshold level. Sensing module 480 also includes a bit line latch 482 for setting a voltage condition on the connected bit line. For example, a pre-asserted state latched in bit line latch 482 will cause the connected bit line to be pulled to a specified stabilizing state (e.g., Vdd). The common portion 490 includes a processor 492, a set of data latches 494, and an I/C) interface 496 coupled between the board data latch 494 and the data bus 420. Processor 492 performs the calculations. For example, one of its functions is to determine the data stored in the sensing memory unit and store the determined data in the data latch of the group. The set of data latches 494 is used to store the data bits determined by the processor 492 during a read operation. It is also used to store data bits that are imported from the data bus 42 during a stylized operation. The data bits that are imported represent the write data that is attempting to be programmed into the memory. The I/O interface 496 provides an interface between the data latch 494 and the data bus 42 124 124908.doc -20· 1378456. During 5 sell or sense, the operation of the system is controlled by state machine 412, which supplies different control gate voltages to the address unit. Along with it, the various sensing threshold voltages corresponding to the various memory states supported by the memory, the sensing module 48A will trip at one of the voltages and pass through the bus 472. Sensing module 48 provides an output to processor 492. At this point, processor 492 determines the resulting memory state by taking into account the (equivalent) trip event of the sense module and information regarding the applied control gate voltage from the state machine via input line 493. It then calculates the binary code for the memory state and stores the generated data bits in the data latch 494. In another embodiment of the core portion, bit 7C line latch 482 serves a dual task while acting as a latch for latching the output of sensing module 480 and also as the bit line described above. Latches. It is contemplated that some embodiments will include multiple processors 492. In one embodiment, each processor 492 will include an output line (not depicted in Figure 8) such that the output lines of the output lines are wired or wired (R). In some embodiments, the output lines are reversed prior to being connected to the line or line. This configuration makes it quick to determine when the stylized program has completed during the stylized verification process because the receive line or state machine can determine when all stylized bits have reached the desired level. For example, when each element has reached its required level, a logical zero for one of the bits will be sent to the line or line (or reverse one data one when all bits turn out a data 〇 (or one inverse) In the case of data 1), the state machine knows to terminate the program sequence 124908.doc 1378456. In a specific embodiment where each processor communicates with eight sensing modules, the state machine needs to be on the line or The line is read eight times, or logic can be added to processor 492 to accumulate the result of the associated bit line such that the state machine only needs to read the line or line once.

During stylization or verification, the data to be stylized is stored in the data latch 494 from the data bus 420. The stylized operation controlled by the state machine includes a series of stylized voltage pulses (with increasing amplitude) that are applied to the control of the addressed memory cells (4). Each stylized pulse is followed by a verification procedure to determine that the memory unit has been programmed to the desired state. The processor 492 monitors the status of the desired memory state - a · » has a hidden state. When the two states are met, the processor 492 sets the bit line latch 482 causing the bit line to be pulled to a reduced program disabled state. This prohibits the unit that is integrated into the bit line from being further stylized' even with stylized pulses on its control gate. In other embodiments, the processor initially carries a bit line latch M2, and the sensing circuit sets it to a disable value during the verification process. The data latch stack 494 includes a data latch stack corresponding to the sense module. In the particular embodiment, there are three data latches per sense group 480. In some embodiments (but not required), the data latches are implemented as a -shift register to cause parallel data stored therein to be converted into serial data for data bus 420, and vice versa. In the eight-body embodiment, the read/write area of the corresponding memory unit = all data latches can be linked to form a block shift register so that it can be transmitted by serial To input or output a data block. 124908.doc -22· 1378456 The specific r's read/write module library is adapted such that each data latch of the #data latch group sequentially shifts data out/out of the data bus. As with its system - part of the shift register for the entire read/write block. Additional information regarding the structure and/or operation of various embodiments of the non-volatile storage device can be found in (1) U.S. Patent Application Publication No. 2004/0057287, issued March 25, 2005, "non-volatile memory Method for reducing the bias of the source line bias"; (2) US Patent Application Bulletin No. 2004/0109357, published on June 1st, 2, 4, "Non-volatile memory and improvement Method of sensing|,; (3) U.S. Patent Application Serial No. 11/015,199, filed on Dec. 16, 2004, the disclosure of Raul_Adrian Cemea; (4) 2()() U.S. Patent Application Serial No. 11/99,133, filed on Apr. 5, 2005, entitled "Coupling Compensation During Non-Volatile Memory Read Operations" , inventor, 丨Chen Chen; and (5) U.S. Patent Application Serial No. 11/321,953, filed on December 28, 2005, entitled "Reference Sense Amplifier for Non-Volatile Memory", Invention People Siu Lung Chan and Raul-Adrian Cernea. All five patent documents of the patent documents listed above are hereby incorporated by reference in their entirety. Figure 9 depicts an exemplary structure of a memory cell array 4A. In a specific embodiment, the array of memory cells is divided into a plurality of memory cell blocks. Like the flash EEPROM system, the block erases the unit. That is, each block contains a minimum number of memory cells that are erased together. Each block is generally divided into several pages. One page is a stylized unit. In one embodiment, a 124908.doc • 23 page can be divided into a plurality of segments and the minimum number of cells written at a time during the slice operation is stored in a column of memory cells. The one-segment includes user data and management H management data—typically including the error correction code (ECC) that has been calculated from the user data of the segment. Control " Sickles (as described below) are calculated when the data is programmed into the array and are also checked when reading f material from the array. Or these

ECC and/or other management materials are stored on pages or even different blocks from the user data to which they belong. A section of user data is typically 512 bytes, corresponding to the size of a section in the drive. Management Data - General - Extra 16 to 2 Bytes... A larger number of pages form a block, for example from 8 pages up to 32, 64, 128 or more pages, wherever they are.

Segments can be included in a basic stylized ° usually one or more pages of data can be stored in one or more sections. As an example, a NAND flash EEPR 〇M is described in Figure 9, which is divided into 1,024 blocks. In this example, 8,512 rows in each block correspond to bit lines BL0, BL1, ... BL8511. In one embodiment, all of the bit lines of a region can be selected simultaneously during reading and stylizing operations. Memory cells along a common word line and connected to any bit line can be programmed simultaneously. In another embodiment, the bit lines are divided into even bit lines and odd bit lines "in an odd/even bit line structure, along a common word line and connected to the odd bits The memory cells of the meta-line are stylized at one time, while the memory cells along a common word line and connected to the even bit lines are stylized at another time. 124908.doc -24- 1378456 Figure 9 shows four memory cells connected in series to form a NAND string. Although it is shown that each NAND string includes four cells, more or less than four (e.g., 16, 32, 64, or another number or memory cells may compete on a NAND) may be used. One terminal of the NAND string is connected to a corresponding bit line via a > and a pole selective closed pole (connected to the selected gate drain line SGD), and the other terminal is connected via a source select gate (connected Connect to the c source to select the gate source line SGS). At the end of a successful stylized program (with verification), the memory sheets, if appropriate, should be in one or more distributions of threshold voltages for programmed memory cells or Used within the distribution of the threshold voltage of the erased memory cell. Figure 10 illustrates an exemplary threshold voltage distribution for a memory cell array when each memory cell stores a binary material. However, his specific embodiment may use more or less than two bits per memory unit. Figure 1G shows the ____ threshold voltage distribution 用于 for the erased memory cell. Three threshold voltage distributions A, Β, and C for the programmed memory cells are also described. In a particular embodiment, the threshold voltage in the Ε distribution is negative and the threshold voltage in the A, Β, and C distributions is positive. The different threshold voltage ranges of the map correspond to predetermined values for the set of data bits. The relationship between the data programmed into the memory unit and the threshold voltage level of the unit depends on the data encoding scheme employed by the units. For example, U.S. Patent No. 6,222,762, and U.S. Patent Application Publication No. 2, 4, 255, 255, "Tracking Unit for Memory Systems," filed on June 13, 2003. Various data encoding schemes for multi-state flash memory cells, both of which are incorporated herein by reference. 124908.doc -25- U/8456 In a specific embodiment, a Gray code is used to assign data The value is assigned to the threshold voltage range such that if the threshold voltage of a floating gate is erroneously shifted to its neighboring physical state, only one bit is affected. An example assignment "u" to the threshold voltage range E (State E), "1〇" to the threshold voltage range a (state A), 临 to the threshold voltage range B (state B) and "〇1" to the threshold voltage range c (like 1C) However, Gray code is not used in other embodiments. Although Figure 11 shows four states, the invention can also be used with other multi-state structures, including those having more or less than four states. Figure ίο shows three read reference voltages Vra, Vrb and Vrc for the slave record The system reads the data. By testing whether the threshold voltage of a given memory unit exceeds or falls below Vra, Vrb, and Vrc, the system can determine the state of the memory unit. Three verification reference voltages Vva, ¥讣, and 乂 are displayed. When the hidden unit is programmed to state A, the system will test whether the memory unit has a threshold voltage greater than or equal to Vva. When the memory cells are programmed to state B, the system will test whether the memory cells have a threshold voltage greater than or equal to Vvb. When the memory cells are programmed to state C, the system will determine such Whether the memory cell has a threshold voltage greater than or equal to Vvc. In a specific embodiment (full sequence programming), the memory cells are directly programmed from the erase state E to the stylized states a, 8 Or ^. For example, you can erase a group of stylized memory cells so that all the hidden cells are in the erase state. Although some memory files are being stylized from state E. To state A, but other The memory unit is programmed from 124908.doc • 26-1378456 state E to state B and/or from state E to state c. The full sequence stylization is graphically depicted by the three curved arrows of Figure 10. Figure 11 illustrates a stylization An example of a two-pass technique for a multi-state memory cell. The multi-state memory cells store data for two different pages: a lower page and an upper page. Four states are described: state Ε (11), state Α (10), state Β (00) and state C (01) e for state E, both pages are stored ^1 "1" For state A, the lower page stores a "〇" and the upper page stores a ";1". For state B, both pages are stored "0". For state c, the lower page stores ''1" and the upper page stores '〇". It should be noted that although a particular bit pattern has been assigned to each state of the states, different bit patterns can also be assigned at In a stylization, the threshold voltage level of the unit is set according to the bit to be programmed in the lower logical page. If the bit is a logic "1 ", the threshold voltage will not change because It is in an appropriate state because it has been erased earlier. However, if the stylized bit is a logical "〇||, then the threshold of the unit is increased to state A, as indicated by arrow 53〇 In the second pass stylization, the threshold voltage level of the unit is set according to the bit to be programmed in the upper logical page. If the upper logical page bit will store a logic 1, then it does not occur. Any stylization, due to the stylization of the lower page bit, the unit is in a strong position p AA々_. From Λ* .....

Once stylized, it has been programmed to state A, and the order of the single 7〇 is made as shown by the threshold. If the unit is further programmed in the second pass of the 124908.doc -27-1378456 due to the second step, the threshold voltage is added to the state B as indicated by the arrow 532. The result of this second pass is to program the unit to specify the state of the storage "0" for the upper page without changing the data for the lower page. ° In one embodiment, if enough data is written to fill a word line, a system can be set to perform a full sequence of writes. If insufficient data is written, the stylized program can use the received data to program the lower page. When the follow-up data is received, the system will then program the upper page. In another embodiment, the system can start writing in the mode of the programmed lower page and convert to a full sequence if the subsequent received sufficient data to fill the memory unit of an entire (or most) word line. Mode. Further details of such specific embodiments are disclosed in U.S. Patent Application Publication No. 2006/0126390, filed on Dec. 14, 2004, by the inventor Sergy Anat 〇 vi vi vi , , , , , , , , , , , , , , , , , , , The use of non-volatile memory pipeline stylization of previous data is incorporated herein by reference. 12A-C disclose another procedure for programming non-volatile memory by writing to a particular page after writing to an adjacent memory cell for the previous page for any particular memory cell. Into this particular memory cell reduces the effect of floating gate to floating gate coupling. In the example of one of the embodiments of the teachings of Figures 12 to (10), the non-volatile memory cells use four data states, each of which stores two-bit data. For example, assume that state E is a wipe. In addition to the state, states A, B, and ^ are stylized states. State E stores data u ^ state A stores data 〇 1. State B storage resources 124908.doc • 28- 1378456 material ίο _ C storage data (10). Examples of non-Gray coding are: - change between adjacent states and Β. Other data can be used to record the physical data status. Jiuyin _ _ ^ ^ each memory stores two pages of data. The reference page is called the upper page and the lower page; however, it can be given other marks. Referring to the state A for the program of the figure and C, the upper page stores the bit 0 and the lower page stores the bit. Element 1. Reference state B, the upper page stores bit 1 and the lower page stores bit 〇. Reference state c, two pages of storage bit data 〇. The stylized program of Figures 12A to c is a two-step program. Stylize the lower page in the step. If the lower page wants to keep the data 1, The memory cell state remains in state E. If the data is to be programmed to 〇, the threshold of the voltage of the memory cell is raised to program the memory cell to state B'. The memory cell is programmed from state E to state B. The state b shown in Figure 12A is an intermediate state B; therefore, the verification point is described as Vvb', which is less than Vvb. In the example 'after staging a memory cell from state E to state B', then it is then programmed relative to its lower page to its adjacent memory cell (WLn+1) in the NAND string. For example, in stylized Will be used after a page connected to the lower part of the memory cell of WL0, will be programmed for a memory cell on the same NAND string but connected to WL1 (next page of the adjacent memory cell. After the adjacent memory unit, if the earlier memory unit has a rising state E to a state B, the threshold voltage 'the floating gate to floating gate coupling effect will rise earlier. Apparent threshold voltage of the memory unit. This will It has the effect of widening the threshold voltage distribution for state B' of 124908.doc -29· 1378456, as shown in Figure 2b. This apparent widening of the threshold voltage distribution will be fixed when the upper page is programmed. 12C describes the program of the stylized upper page. If the memory unit is in the erase state E and the upper page is to remain in the 丨, the memory unit will remain in the state E if the memory unit is in the state In the case where the upper page data is to be programmed to 0, the threshold voltage of the memory unit is raised such that the memory unit is in state A. If the memory unit is within an intermediate threshold voltage distribution 550 And if the upper page data is to remain at 1, the memory unit will be programmed to the final state B. If the memory cell is within an intermediate threshold voltage distribution 550 and the upper page data is to become data 则, then the threshold voltage of the memory cell is raised such that the memory cell is in state C. The procedure shown in Figures 12A through C reduces the coupling effect between the floating gates because only the top page stylization of adjacent memory cells will affect the apparent threshold voltage of a given memory cell. Although Figures 12A-C provide an example with respect to four data states and two data pages, the concepts taught by Figures 12A-C can be applied to more or less than four states, other embodiments than two pages and/or Or other material code. Figure 13 is a table showing one of the specific embodiments of the sequence of staging memory cells using the stylized methods of Figures 12A-C. For the memory cell unit connected to the word line WL0, the lower page forms a page and the upper page forms a page 2. For the memory cell connected to word line WL1, the lower page forms page i and the upper page forms page 4. For the memory cells connected to word line WL2, the lower page forms page 3 and the upper page forms page 6» for memory 124908.doc • 30· cells connected to word line WL3, the lower page forms page 5 and the upper page forms page 7. The memory unit is programmed from page 0 to page 7 according to the page number. In other embodiments, other stylized sequences may also be used. In some embodiments, the data is programmed to a hidden unit along a common word line. Thus, one of the word lines is selected for stylization prior to application of the stylized pulses #f. This word line will be referred to as the selected word line. The remaining word lines of a block are referred to as unselected word lines. The selected word line can have one or two adjacent word lines. If the selected word line has two adjacent word lines, the adjacent lines on the drain side are referred to as the non-polar side adjacent word lines and the adjacent word lines on the source side are referred to as the source side phases. Neighbor word line. For example, if WL2 is a selected word line, then WL1 is the source side adjacent word line and WL3 is the drain side adjacent word line. In some embodiments, a block of memory cells is programmed from the source to the drain side. For example, first programmatically connect to the memory cell of WL〇, then program the memory cell on WL1, then program the memory bank 7G on WL2, etc. As described above, Figure 13 depicts in this order. A small change is still typically programmed from the source side to the drain side. Figure 14 is a flow diagram showing one of the stylized procedures for staging a memory cell connected to a selected word line. Thus, the program of FIG. 14 is used to implement the full sequence of FIG. 10, one of the two-pass programming techniques of FIG. 10 (first pass or second pass) or the second step stylization techniques of FIGS. 12A to C and 13 One pass (first pass or second pass). Since a stylized program can include stylizing a plurality of pages, the stylized program can include executing the program of Figure 14 multiple times. In one embodiment of the process of Figure 14, the memory cells are erased (by block or other unit) prior to programming (step 64). In a specific embodiment 124908.doc •31 · the memory unit is maintained by raising the well to a wipe voltage (eg, 20 volts) for a sufficient period of time and when the source and bit lines are floating The word line of a selected block is grounded to be erased. Due to capacitive coupling, the unselected word line, bit 7L line, select line, and C source also rise to a significant portion of the erase voltage. Thus, a strong electric field is applied to the tunneling oxide layer of the selected memory cell and the selected memory is erased as the electrons of the sweat gates are generally emitted to the substrate side by Fowler-Nordheim randomization. Unit information. The electron system is transferred from the floating gate to the p-well region, and the threshold voltage of the selected single-turn is reduced. "Erasing can be performed on the entire memory array, the separation block or other unit units to erase the memory unit. The blocks can be followed by stylized or partially programmed various memory cells as described herein. It should be noted that the erasure performed at step 040 is not necessarily performed prior to stylizing the word lines of a block. Indeed, the block can be erased and the word lines can then be programmed without being erased between the stylized word lines. At step 642, a soft stylization is performed to narrow the distribution of the erase threshold voltages for the erased memory. Some memory cells are in a deeper state than necessary due to the erase procedure. The soft stylization can apply a smaller stylized pulse to move the threshold voltage of the erased memory cells closer to the erase verify level. In step 650, a "data load" command is issued by controller 450 and input to state machine 412. At step 652, address data specifying the page address is provided to the decoder. At step 654, one of the page program data for the addressed page is entered for stylization. For example, in one embodiment, 528 bytes of data can be entered. The data is latched into the appropriate register/latch 124908.doc -32-1378456 for the selected location line. In some embodiments, the data is also latched for use in the selection. One of the bit lines is in the second register for use in the verify operation. At step 656, the -"program" command is received by controller 450 and provided to state machine 412. After being triggered by the "program" command, the data latched in step 654 is applied to the appropriate word line. The pulse is programmed into the selected memory cells controlled by state machine 412. At step 658, the programmed voltage signal Vpgm (eg, a series of pulses) is initialized to a starting magnitude (eg, ~i2v or another A suitable level) and one of the program counters pc maintained by state machine 412 is initially zero. At step 660, one of the program signals $Vpgm is applied to the select line. Storing the logic "0" in a specific data latch, indicating that the corresponding memory cell should be stylized, then grounding the corresponding bit line. On the other hand, if the logic "丨" is stored in a specific latch indicating that the corresponding memory single TL should remain in its current data state, the corresponding bit line is connected to Vdd to disable stylization. At step 662, the appropriate target level set is used to verify the status of the selected memory, as described above. If it is detected that the threshold voltage of a selected unit has reached the appropriate target level, the bedding stored in the corresponding data latch becomes -logic"1". If it is detected that the threshold voltage has not reached the appropriate target level, the data stored in the corresponding data latch is not changed. It is not necessary to stylize a bit line stored in its corresponding data latch with __logic "丨". When the right side of the %' Tianm has a Gonggao latch in the storage logic "Γ, the state machine knows that the programmed π-W has been selected early ^ In step 664, check all data latches 9 § 熹 疋 疋 储存 储存 储存 储存 储存 储存 储存 储存 。 。 。 。 。. If so, then 124908.doc •33- The stylized program has completed and succeeded because all selected memory units have been programmed and tested 5a to their target state. In step 666, report __ II through " It should be noted that in some embodiments +, in step 664, it is checked whether at least a predetermined number of data latches are storing a logic "丨"\ this predetermined number may be less than the number of all data latches, thereby allowing The stylized program stops before all memory cells have reached their proper verify level. During the reading process, error correction can be used to correct unsuccessfully programmed memory cells. Right at step 664, it is determined that not all data latches are storing logic 1, and the stylized program continues. At step 668, the program counter pc is checked for a stylized limit. However, an example of a stylized limit is 20; however, other values may be used in various implementations. If the program counter pc is not less than the stylized limit, then in step 669 it is determined whether the number of memory cells that have not been successfully programmed is equal to or less than a predetermined number. If the number of unsynchronized memory cells is equal to or less than the predetermined number, then the stylized program is marked as passed and a pass status is reported in step 671. In many cases, error correction can be used during the reading process to correct unsuccessfully programmed memory cells. However, if the number of unsynchronized memory cells is greater than the predetermined number, then the stylized program is marked as failed in step 670 and a failure status is reported. If the program counter PC is less than the stylized limit (eg, 20)', then in step 672, the magnitude of the Vpgm pulse is incremented by step size (eg, 〇.2 to 0.4 volt step size) and the program counter PC is incremented. . After step 672, the program loop returns to step 660 to apply the next Vpgm pulse, 124908.doc • 34-1378456. During such verify operations (eg, verify operations performed during step 662 of FIG. 14) and during read operations, the selected word line is coupled to a voltage whose level is designated for each read and verify operation. Determine the threshold voltage of one of the relevant memory cells; ^ has (four) this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the voltage applied to the word line is turned on to turn on the memory cell. If the measured conduction current is greater than a particular value, it is assumed that the memory cell is turned "on" and the voltage applied to the sub-line is greater than the threshold current of the memory cell. If the measured conduction current is not greater than the specific value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured based on the rate of discharge or charge of a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or does not allow) the NAnd string including the memory cell to release the corresponding bit line charge. The voltage on the bit line is measured after a period of time to see if it has been discharged. It has been observed that the program disturbing boundary on the selected word line depends on the WL 特别 (closed to the word line at the end of the NAND string relative to other word lines). The state of adjacent memory cells. If the adjacent memory cell is in the erased state, then the channel region underneath the adjacent memory cell during the boosting process (during stylization prohibition) should be in a conducting state. However, if the adjacent memory unit is partially programmed (eg, in intermediate state 550, as shown in B of Figures 12A-c, or another J24908.doc-35-1378456 is not expected to be finalized), then The channel area underneath the adjacent memory cell can become less conductive in the off state or in the case of its partial stylization. In this latter case t, it will be different than would be expected to boost the channel area underneath the memory block connected to the selected word line and may not be sufficiently boosted to avoid program disturb. Thus, the optimum value of Vpass used to obtain a suitable reduction in program disturb depends on the state of the adjacent memory cells. In order to remove this data dependency, a higher boost voltage is applied to the adjacent memory cells than the boost voltage applied to other unselected memory cells. Thus, the channel area underneath adjacent memory cells will be in its proper conduction state independent of the data stored in adjacent memory cells. Figure 15 depicts a NAND string that is biased by applying a higher boost voltage to an adjacent a memory cell as proposed, and is not intended to be stabilized during one of the steps 660 of the process. Since the voltages are applied as described in Figure 15, at least a portion, if not all, of the NAND strings are boosted, stabilizing. The NAND string of Figure 15 includes eight memory cells 75A, 752, 754, 756, 758, 760, 762, and 764. Memory cells 750 and 764 are at the end of the NAND string relative to other memory cells. Each of the memory cells of the eight memory cells includes a floating gate (FG) and a control gate (CG). The floating gates of the floating gates are between the source/drain regions 77〇. In some embodiments, there is a P-type substrate (e.g., germanium), a N-well in the substrate, and a p-well in the well (not all shown to increase readability). It should be noted that the P well may comprise a so-called channel implant, which is typically a P^ implant' that determines or helps determine the threshold voltage and other characteristics of the memory cells. The source/pole regions 77G are formed in the N+ diffusion region of the P well 124908.doc -36-1378456. A gate 766 is selected on one of the drain sides of the NAND string. The drain side select gate 766 connects the nAnd string to the corresponding bit line via bit line contact 774. A source select gate 768 is coupled to the other end of the NAND string. Source select gate 768 connects the NAND string to a common source line 772. During stylization, it is connected to the selected word line (for example, the memory single-charge memory unit receives the stylized voltage at its control gate via the selected word line. Voltage Vpgm. Apply a boost voltage vpass of approximately 8 to 9 volts to no Selecting control gates for staging memory cells (eg, 'memory cells 754, 756, 758, 760, 762, and 764), except for adjacent memory cells. A higher boost voltage VpassH is via Word line WL1 is provided to the control gate of adjacent memory cell 752. VpassH is a voltage higher than Vpass. In a specific embodiment, VpassH is 1 to 4 volts higher than VpassH, or may be for a specific embodiment Another difference is applied where appropriate. In one embodiment, VpassH is one higher than Vpass, which is equal to the difference between state £ and state B, (see Figure 12B). It should be noted that making VpassH too high may be receiving Program noise is caused by the memory unit of VpassH. Depending on the data to be stored, the adjacent memory unit can be partially or unprogrammed. For example, if you want to store the data system, the memory unit will In erasing state E. If you want to store the data system "〇", the memory unit may have been moved to the intermediate state B (Fig. 12A to c threshold voltage 550). Source selection gate 768 system In an isolated state, it receives 0 volts at its gate (G). A low voltage is applied to the common source line 772. This low voltage can be 124908.doc • 37-1378456 volts. However, the source voltage is also It may be slightly higher than 〇V to provide better isolation characteristics of the source side selection gate. The gate 766 is applied to the drain side to apply a voltage Vsgd which is usually in the range of the power supply voltage Vdd (for example, 25 volts). The bit line applies volts to the bit line contacts to enable programming of the selected memory cell 750. Due to the boost voltage, the channel region of the NAND string is boosted (as described above) due to the memory cell. The voltage difference between the floating gate and the channel of 750 has been reduced, so stylization is prohibited. Figure 15 shows a region 780 that includes a boost channel region 781 on the surface of the substrate (between source/drain regions 77〇) And below the floating gate/control gate stack) a depletion layer below the region of the booster channel (a region that increases the electric field due to pressurization to a high voltage channel). Figure 16 is a timing diagram of the description of one of the steps 660 of Figure 14 for repeated processing. An example of the timing of applying the various signals shown in Figure 15 for an unselected NAND string. Figure 16 shows that the bit line voltage VBL from t2 to t6 is at Vdd (e.g., '2_5 volts'' thereby inhibiting correlation with the particular bit line. The nand string is selected. The gate voltage VSGD (the voltage at the control gate of the selected transistor SGD) is raised to volts at tl, then lowered to 2.5 volts at t2 (eg, Vdd) 'here it remains until T6. The Vsgd between 5 and volts is optionally used to increase the precharge voltage level of the NAND string. The voltage on the unselected dice line Vuwl is raised to Vdd at t1 to allow pre-charging' then raised to approximately Vpass at t2 to boost the NAND strings associated with the unselected positioning elements. The pass voltage vpass will remain at the unselected word line until approximately t5 » It should be noted that in the particular embodiment of Figure 5, VUWL is applied to all word lines except the adjacent word line. The voltage Vnuwl on the unselected adjacent word line 124908.doc -38· 1378456 (in Figure 15 WL1 (corresponding to memory unit 752)) is raised to 11 in vdd to allow pre-charging and then at t2 liters. Up to about VpassH to help boost the nand string associated with the unselected positioning elements. The pass voltage VpassH will remain on the unselected adjacent word lines until approximately t5. The voltage vSWL on the selected word line (e.g., WLO ' corresponds to memory cell 750 in Figure 15) is raised to vdd at ti to allow for pre-charging. A stylized pulse is applied at t3' until t5. In one example, the stylized pulses can vary between 12 volts and 20 volts. It should be noted that the control gate of the source side select gate (vSGS) is always volts and the source voltage Vs is ramped up to and maintained until t6 before 11. It should be noted that the exact timing of the various signals described above may vary depending on the particular implementation. It should be noted that Fig. 15 corresponds to the state of the voltage signals at time t4 of Fig. 16. In some embodiments 'Vuwl, Vswl and Vnuwl are connected to Vdd (or another voltage > 〇 v) during t1 to t2. In other embodiments, Vuwl, Vswl, and Vnuwl are 〇 V during the time interval tl to t2. Figures 1 and 16 pertain to the use of a higher boost voltage for an unselected phase of the word line when WL0 is selected. However, the techniques described in this article are also part of the case of choosing other word lines for stylization. For example, Figure 17 shows the situation in which the stylized NAND string is disabled when a word line (e.g., WL3) connected to the memory cell 756 is selected. In this case, the word line (e.g., WL4) near the selected word line will receive High transfer voltage VpassH. More specifically, Figure I? shows the target but the unselected memory unit 756 is receiving Vpgm. Adjacent memory unit 758 receives VpassH. The memory cells 750, 752, 754, 760, 762, and 764 receive Vpass. Due to the application of the boost voltage, the channel region 781 at the surface of the region 124908.doc • 39· 1378456 780 is boosted and completely disabled. Memory unit 756. The signal timing described in Figure 17 is similar to the signal timing of Figure 16. Figure 17 shows only an example, and applying VpassH to neighbors can be used when selecting other word lines for stylization. It should be noted that in some alternatives, the memory cells on the source side of the memory cells receiving the stylized voltage may receive a transfer voltage that is higher than Vpass "eg, memory cells 750, 752, and / Or 754 can receive Vpass, VpassH, or VpassO 'where VpassO may be higher, lower, or similar to VpassH or Vpass. Figure 15 shows that memory cells 754, 756, 758, 760, 762, and 764 each receive the same signal Vpass. Similarly, Figure 17 shows that memory cells 750, 752, 758, 760, 762, and 764 all receive the same signal Vpass. However, in some embodiments, the memory cells do not necessarily receive exactly the same voltage. For example, the voltages can vary by word line as long as they (or a subset) are less than VpassH. Both Figure 15 and Figure 17 describe the techniques used to modify the self-voltage boosting scheme described above. However, the proposed technique can also be used to modify other boosting schemes. Figure 18 depicts a NAND string when a word line other than WL0 is selected for programming and using the proposed technique to modify the EASB boosting scheme. The target but unselected memory unit 756 receives Vpgm. Adjacent memory unit 758 receives VpassH. Memory unit 750, 752, 760, 762 and 764 receive

The Vpass»memory unit 754 receives an isolated voltage (e.g., volts) "by applying the dedicated boost voltage, a higher boost channel region and a lower boost channel region are created. For example, Figure 18 depicts a region 782 that includes a higher pressurized channel region 783 on the surface of the substrate table 124908.doc 40-1378456 and a depletion layer below the region of the higher pressurized channel. Figure 18 also shows a region 784 comprising a lower pressurized channel region 785 on the surface of the substrate and a depletion layer below the lower pressurized channel region. This higher boost channel region causes a complete disable of the stylized memory unit 756. The signal timing described in Figure 18 is similar to the signal timing of Figure 16. Figure 18 shows only an example ' and can use VpassH to the neighbor when selecting other word lines for stylization. It should be noted that if WL〇 is selected for stylization' then the proposed technique is applied to the EASB boosting scheme as shown in Figure 15, since the difference between self-boosting and EASB is based on the source side and is used in selecting WLO. There is no source side when stylized. Figure 19 depicts a NAND string when a word line outside the WLO is selected for programming and using the proposed technique to modify the REASB boost scheme. The target but not selected memory unit 756 receives Vpgm. Adjacent memory unit 758 receives VpassH. Memory cells 750, 760, 762, and 764 receive Vpass. Memory unit 752 receives an isolation voltage (e.g., volts). Memory unit 754 receives an intermediate voltage Vgp (e.g., 2 to 5 volts) via its connected word line. A higher boost channel region and a lower boost channel region are created by the application of the boost voltages. For example, Figure 19 depicts a region 788 that includes a higher pressurized channel region 789 on the surface of the substrate and a depletion layer below the region of the higher pressurized channel. Figure 19 also shows a region 790 comprising a lower pressurized channel region 791 on the surface of the substrate and a depletion layer below the lower pressurized channel region. This higher boost channel region causes the program bus memory unit 756 to be completely disabled. The signal timing described in Fig. 19 is similar to the signal timing of Fig. 16, and Vgp has a timing similar to Vpass. Figure 19 shows only one example, and 124908.doc •41 · 1378456 can be used to apply VpassH to neighbors when selecting other word lines for stylization. It should be noted that if WLO is selected for stylization, as shown in Figure 15, the proposed technique is applied to the rEASB boosting scheme, since the difference between self-boosting and EASB is based on the source side and is used in the selection of wl There is no source side when stylized. Figure 20 depicts a NAND string when a word line outside of WL is selected for programming and using the proposed technique to modify an alternative boosting scheme. The target but unselected memory unit 758 receives Vpgm. Adjacent memory unit 760 receives

VpassH. Memory unit 75〇, 756, 760, 762, 766, ... receive

Vpass ° As described above, the techniques described herein can use NAND strings that are longer than eight memory cells. Figure 20 shows a portion of a NAND string having more than eight memory cells. Memory cells 752 and 764 receive the isolation voltage via their connected word lines. The memory unit 754 receives the intermediate voltage Vpg via its connected word line. Due to the application of the boosted voltages, a higher boost channel region and an intermediate boost channel region and a lower boost channel region are created. For example, Figure 20 depicts a region 794 that includes a higher pressurized channel region 795 at the surface of the substrate and a depletion layer below the region of the higher pressurized channel; a region 798' that includes a region of the pressurized channel in the middle of the surface of the substrate. 799 and a depletion layer located below the lower pressurized passage region; and region 796 comprising a lower pressurized passage region 797 on the surface of the substrate and a depleted layer below the lower pressurized passage region The compressed channel region causes the program memory unit 758 to be completely disabled. The signal timing described in Figure 20 is similar to the signal timing of Figure 16, and Vgp has a timing similar to vpass. Figure 20 shows only an example ' and can be used when selecting other word lines for stylization. 124908.doc -42 - 1378456

VpassH to the neighbor. In some embodiments, the system can partially program more than one memory early element of a NAND string prior to completing programming of a currently selected memory unit. For example, the stylized program of Figures 12A through C can be modified to perform a first pass/step for three word lines before continuing to complete the stylization on the first sub-line. In an example in which three data pages are stored in a memory unit, data is written in the following order: (1) writing the lower page data to WLn '(2) writing the lower page data to WLn+1, (3) Write intermediate page data to WLn, (4) Write lower page data to wLn+2, (5) Write intermediate page data to WLn+1, and (6) Write lower page data to WLn to complete Write all 3 pages to WLn. Other methods/schemes can also be used. In these examples, there are two word lines (depending on the data to be stored) that have been partially programmed and can receive VpassH during the staging of the first word line. Figure 21 shows an example of the VpassH. More specifically, memory unit 750 coupled to a selected word line (e.g., WLO) receives a stylized voltage Vpgm at its control gate via the selected word line. The boosting voltage Vpass is applied to the control gates of the unselected 己5 memory cells 756, 758, 760, 762 and 764. The hinge boost voltage VpassH is supplied to the control gate of the body unit 752 via the word line WL1 and to the memory bank 754 via the word line WL2. It should be noted that although FIG. 21 shows two received memory cells, because the two memory cells may or may not be partially programmed due to the final erase process of the NAND string, other embodiments may include more than one. The memory cells of the VpassH are received because the memory cells may or may not be partially programmed by 124908.doc -43. 1378456 due to the final erase program for the NAND strings. It should be noted that in a particular embodiment where more than one word line receives a higher boost voltage, it may not all receive exactly the same VpassH. The word lines that receive the relatively boosted voltage can receive different VpassH variations. In a specific embodiment, each VpassH change is greater than Vpass. Consider an example when using the program of Figures 12A through C to program a memory cell block. According to the graph of Fig. 13, the memories connected to the WLO will be partially programmed (see Fig. 12A) such that the lower page has data. These memory cells connected to WL1 will then be partially localized (see Figure 12A) such that the lower page has data. At this point, since the block was previously erased (see step 640 of Figure 14), the dedicated 6-message early connected to WLO and WL1 has not been fully programmed. Subsequently, the memory cells connected to WL0 will complete their stylization (see Figure 12C) so that their upper page also has data. When the stylization for WL〇 (eg, 'programming the upper page') is performed, the various word lines of the Nand strings are biased as shown in FIG. 15. These concepts can be extended to other word lines, as shown in FIG. 20. In addition, the various word lines of the NAND strings can be biased as shown in Figure 15 when the lower page is programmed. The foregoing detailed description of the invention has been presented for purposes of illustration It is not intended to be exhaustive or to limit the invention to the precise form disclosed. In the light of the above teachings, many modifications and variations are possible. The specific embodiments are chosen to clearly illustrate the principles of the present invention and its practical application. The invention is best utilized with various modifications that are suitable for the particular use contemplated.希 124908.doc -44- 1378456 The scope of the invention is defined by the scope of the accompanying patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top view of a NAND string. Figure 2 is an equivalent circuit diagram of one of the NAND strings. Figure 3 depicts a NAND string and a set of voltages applied to the NAND string during a stylized operation. Figure 4 depicts a NAND string and a set of voltages applied to the NAND string during a stylized operation. Figure 5 depicts a portion of a NAND string. Figure 6 is a block diagram of a non-volatile memory system. Figure 7 is a block diagram of a non-volatile memory system. Figure 8 is a block diagram depicting one embodiment of a sensing block. Figure 9 is a block diagram depicting one embodiment of a memory array. Figure 10 depicts an exemplary set of threshold voltage distributions and illustrates the procedure for programming non-volatile memory. Figure 11 depicts an exemplary set of threshold voltage distributions and illustrates the procedure for programming non-volatile memory. Figures 12A through C show various threshold voltage distributions and illustrate a procedure for programming non-volatile memory. Figure 13 is a table depicting the order in which non-volatile memory is programmed in a particular embodiment. Figure 14 is a flow chart showing a specific embodiment of a program for staging non-volatile memory. Figure 15 depicts a NAND string and a set of ink applied to the 124908.doc • 45-1378456 NAND string during a stylization operation. Figure 16 illustrates a timing diagram of the behavior of a particular signal during a stylized operation. Figure 17 depicts a NAND string and a set of voltages applied to the NAND string during a stylized operation. Figure 18 depicts a NAND string and a set of voltages applied to the NAND string during a stylized operation.

Figure 19 depicts a NAND string and a set of voltages applied to the NAND string during a stylized operation. Figure 20 depicts a NAND string and a set of voltages applied to the NAND string during a stylized operation. Figure 21 depicts a NAND string and a set of voltages applied to the NAND string during a read operation.

[Main component symbol description] 100 transistor 100CG control gate 100FG floating gate 102 transistor 102CG control gate 102FG floating gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 124908.doc -46- 1378456

106CG control gate 106FG floating gate 120 first (or drain) select gate 122 second (or source) select gate 126 bit line contact 128 source line 304 memory unit 306 memory unit 308 memory Body unit 3 10 memory unit 312 memory unit 3 14 memory unit 316 memory unit 318 memory unit 322 source select gate 324 drain side select gate 330 source / > and polar region 332 common source Line 334 bit line contact 340 channel 350 memory unit 352 memory unit 354 memory unit 356 memory unit 124908.doc -47- 1378456 358 memory unit 360 memory unit 362 memory unit 364 memory unit 366 汲Pole selection gate/drain selection transistor 368 source side selection gate 370 source/drain region 374 bit line contact 380 region/boost channel 384 P well region 396 memory device 398 memory die 400 Two-dimensional memory cell array 410 control circuit 412 state machine 414 on-chip address decoder 416 power control module 418 line 420 line 430 column decoder 430A Column Decoder 430B Column Decoder 450 Controller 460 Row Decoder 124908.doc -48- 1378456 Row Decoder Row Decoder Read/Write Circuit Read/Write Circuit Read/Write Circuit Sensing Circuit Data Busbar sensing module bit line latch common part processor

460A

460B 465

465A

465B 470 472 480 # 482 490 492 493 Input line 494 496 500 530 532 534 550 750 752 754 756 758

Data Latch I/O Interface Sensing Block Arrow Arrow Arrow Intermediate Threshold Voltage Distribution / Intermediate Status Memory Unit Memory Unit Memory Unit Memory Unit Memory Unit 124908.doc •49· 1378456

760 762 764 766 768 770 772 774 _ 780 781 782 783 784 785 788 789 790 791 794 795 796 797 798 799 129 124908.doc Memory unit memory unit memory unit drain side select gate source select gate source / bungee area common source line bit line contact point booster channel area higher boost channel area lower boost channel area higher boost channel area lower boost channel area higher boost Channel area area lower pressure channel area intermediate pressure channel area -50-

Claims (1)

1378456 No. 96135〗 No. 41 Patent Application Patent Application Fan Park·· Chinese Application Patent Fan Gu Replacement (〇 April 2001) A method of performing a staging (s), (4) execution, which includes: Group of pressurized-non-volatile storage elements, = group of non-volatile storage elements includes a specific non-volatile storage element, a plurality of non-volatile storage elements, and - or a plurality of non-volatile eight-pieces The group - the last erase process begins but has not yet completed full programming - the one or more non-volatile storage elements include - one of the first side adjacent to and located on the first side of the particular non-volatile storage element An adjacent non-volatile storage element, the non-volatile storage element group further comprising other non-volatile storage elements that have not been programmed since the last erasing procedure of the group, the dusting comprising applying - or a plurality of comparisons Highly dusting signals to the one or more non-volatile storage elements and applying - or differently increasing signals to the other non-volatile storage elements, the voltage values of the one or more higher boost signals being higher than the One or The voltage value of the different augmented house signals is at least - based on the voltage offset of the difference between the erased state of the first adjacent non-volatile storage element and an intermediate stylized state; The group: group when 'apply a program signal to the particular non-volatile storage element. 2. The method of claim 1, wherein: the step of boosting the group and applying the program signal is part of a stylized program, and the silking (4) begins with the specific non-volatile storage element and ends with In the order of one of the group's final non-volatile storage elements, 124908-1010413.doc 1378456 H, 1; positively applies the program signal β. 3. The method of claim 2, wherein: the non-volatile storage element group The component is a part of a NAND string. 4. The method of claim 1, wherein: the non-volatile storage element group is a portion of the NAND string, the specific non-volatile storage element is adjacent to a source of the NAND string Connecting components. 5. The method of claim 1, wherein: the one or more non-volatile material elements and other non-volatile storage elements are on the same side of the particular poetic element; and the non-volatile storage element group The groups are connected in series. The storage elements are partially stylized. The method of claim 1, wherein: the one or more non-volatile The non-volatile storage elements are on the bit line side with respect to the characteristic storage element. The method of claim 7, wherein: a portion of a NAND string, the source side; and a non-volatile The isolated non-volatile storage element is separated from the specific non-volatile storage element by the proximity of the specific non-volatile storage element to the specific non-volatile storage I24908-I01〇413.doc on the 378456 牟 曰 曰 正 正 替 替The component is on the source side with respect to the specific element; 4 dusting includes applying - the first transfer (four) to the plurality of volatile storage elements; ', he does not pressurize including applying a first value of Cheng Xue Dissipating the component; summing the voltage to the adjacent non-volatile storage; the second transfer voltage is greater than the first transfer voltage and the first voltage is greater than the isolation voltage. 9. The method of claim 7, Wherein: the one or more non-volatile storage elements are composed only of an adjacent non-volatile storage element adjacent to the vital storage element;: increasing: including applying an intermediate voltage to the specific non-volatile member One or more intermediate non-volatile storage elements on the second t and one of the sexual storage elements are adjacent to the particular non-volatile charge including applying-isolation voltage to the one or more volatile health Separate component a non-volatile storage component; 8 the boosting includes applying a first transfer voltage to the plurality of the volatile storage elements; 〃 non-pressure includes applying a second transfer voltage to the adjacent non-volatile storage element, The one or more higher boost signals are only composed; and the first transfer voltage is greater than the sequel-V*, Λ «Β, , 5-, and the voltage system is greater than the intermediate electrical waste. And the first pass 10. The method of claim 7, wherein: 124908-1010413.doc 137845 days of riding a page "or a plurality of non-volatile faulty elements are only adjacent to the adjacent non-volatile storage element Non-volatile storage element composition, the pressurization includes applying-intermediate electricity to an intermediate non-volatile storage element, the intermediate non-volatile (4) being close to the specific element and relative to the specific non-volatile storage element «The pressurization on the pole side includes applying-isolated the electric fort to the non-volatile storage element adjacent to one of the intermediate non-volatile storage 7C pieces; the pressurization includes applying a first transfer charge to the plurality of other non-volatiles a volatile storage element; the boosting includes applying a second transfer voltage to the adjacent non-volatile storage element; the boosting includes applying the first transfer power to one of the adjacent non-volatile storage 7C pieces Determining a non-volatile storage element; the pressurization comprising applying the isolated electrical energy to a non-volatile storage element adjacent to the given non-volatile storage element; and the second transfer voltage is greater than the first transfer charge 11. The method of claim 1, wherein: the one or more non-volatile storage elements are only adjacent to a non-volatile adjacent one of the non-volatile storage elements. The storage element is configured and the adjacent non-volatile storage element has not been programmed prior to the step of increasing. 12_ The method of claim 1, wherein: the program signal is applied to the particular non-volatile storage element一控]24908- ] 0 ] 04) 3 -doc -4- 尸 j 口 哆〇 々 饮 饮 η 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. The portion of the voltage pulse. 14. The method of claim 1, wherein: = non-volatile storage element group (four) flash memory 15 method as claimed, wherein · 16 = volatilization 14 storage & Multi-state flash memory device. 16. A non-volatile storage system comprising: a set of control lines; a non-volatile storage element 'which communicates with the control lines, the set of non-volatile Storage component, storage component fish-m set of one or more non-swing One or more non-volatile storage elements of a subset, "+-- or a plurality of non-volatile storage elements including - located adjacent to and located on a first side of the particular non-volatile storage element a first adjacent non-volatile storage element; and::: a circuit comprising one or more electrical ones/channels in communication with the set of control lines to finally erase the first one from the group A subset of - or a plurality of non-volatile storage elements have begun but have not yet completed a full program: a state of the order provides a signal to the set of non-volatile storage elements, the one or more electrical house providing circuitry to provide boosted power Volatile storage elements to the first subset and one or more non-components of the second subset comprising one or more non-volatiles providing one or more higher boost voltages to the first subset The storage element and the one or more I24908-I010413.doc 1378456 ftOTTTS year/month #王 replacement page does not cap voltage to the second subset, the one or more higher boost voltages are higher than the one or more Different boost voltages of at least one based on the first adjacent non-volatile storage An electrical offset (v〇Uage 〇 ffset) of a difference between an erased state of the component and an intermediate stylized state, wherein the plurality or plurality of voltage providing circuits are boosting one or more of the first subset The volatile storage element and the one or more non-volatile storage elements of the second subset provide a stylized signal to the particular non-volatile storage element. 17. The non-volatile storage system of claim 16, wherein: the management circuit applies the stylized signal to the non-volatile group from the particular non-volatile storage element to an opposite non-volatile storage element. Store components. 18. The non-volatile storage system of claim 16, wherein: the particular non-volatile storage element is adjacent to a source connection. 19. The non-volatile storage system of claim 16, wherein the set of non-volatile storage elements is a portion of a NAND string and the particular non-volatile library element is relative to the set of non-volatile storage elements. At one source side of the NAND string. 20. The non-volatile storage system of claim 16, wherein: the one or more non-volatile storage elements of the first subset and the non-volatile storage element of the second sub- One of 70 pieces of volatile storage on the same side; and 隹! ::: One or more non-volatile storage elements of the set are in series with one or more non-volatile storage elements of the second subset. 21. The non-volatile storage system of claim 16, wherein: I24908-I010413.doc 1378456 the management circuit local program is provided before the one or more higher voltages are supplied to the non-volatile storage 7L piece. One or more non-volatile storage elements of the first subset. ', 22. The non-volatile storage system of claim 16, wherein: the set of non-volatile storage elements is a portion of a nand string. The NAND string has a bit line side and a source side. 23. The non-volatile storage system of claim 22, wherein: the one or more voltage providing circuits of the stomach apply-isolated voltage to isolate the non-volatile storage element from one of the particular non-volatile storage elements. 24. The non-volatile storage system of claim 22, wherein: the one or more voltage providing circuits apply an intermediate electrical house to the intermediate non-volatile storage element adjacent to the particular non-volatile storage element; and the - or A plurality of voltage providing circuits apply an isolation voltage to isolate the non-volatile storage element from one of the intermediate non-volatile storage elements. 25. The non-volatile storage system of claim 22, wherein: Φ the +th set or plurality of non-volatile storage elements are only by adjacent non-volatile storage relative to the particular non-volatile (four) piece The component composition; and the one or more higher boost voltages consist only of a higher transfer voltage. 26. The non-volatile storage system of claim 16, wherein: the set of non-volatile storage elements has a floating gate. 27. The non-volatile storage system of claim 16, wherein: the control lines are connected to a word line of a control gate region of the non-volatile storage element such as a plug. 124908-1010413.doc 1378456 if-f\日修正好&贝_ _ ---' 28. The non-volatile storage system of claim 16, wherein: a set of non-volatile storage elements are flash memory Device. 29. The non-volatile storage system of claim 16, wherein: a set of non-volatile storage elements is a multi-state flash memory device 124908-1010413.doc