WO2008039667A3 - Reducing program disturb in non-volatile storage - Google Patents
Reducing program disturb in non-volatile storage Download PDFInfo
- Publication number
- WO2008039667A3 WO2008039667A3 PCT/US2007/078842 US2007078842W WO2008039667A3 WO 2008039667 A3 WO2008039667 A3 WO 2008039667A3 US 2007078842 W US2007078842 W US 2007078842W WO 2008039667 A3 WO2008039667 A3 WO 2008039667A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- volatile storage
- program disturb
- reducing program
- programmed
- volatile
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
Abstract
A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile storage elements that may be partially programmed.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/535,628 | 2006-09-27 | ||
US11/535,634 US8184478B2 (en) | 2006-09-27 | 2006-09-27 | Apparatus with reduced program disturb in non-volatile storage |
US11/535,628 US8189378B2 (en) | 2006-09-27 | 2006-09-27 | Reducing program disturb in non-volatile storage |
US11/535,634 | 2006-09-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008039667A2 WO2008039667A2 (en) | 2008-04-03 |
WO2008039667A3 true WO2008039667A3 (en) | 2008-06-05 |
Family
ID=39230870
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/078842 WO2008039667A2 (en) | 2006-09-27 | 2007-09-19 | Reducing program disturb in non-volatile storage |
Country Status (2)
Country | Link |
---|---|
TW (1) | TWI378456B (en) |
WO (1) | WO2008039667A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7848144B2 (en) * | 2008-06-16 | 2010-12-07 | Sandisk Corporation | Reverse order page writing in flash memories |
JP6895002B1 (en) | 2020-05-27 | 2021-06-30 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor storage device and readout method |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107658A (en) * | 1997-02-27 | 2000-08-22 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
DE10164149A1 (en) * | 2000-12-28 | 2002-07-18 | Samsung Electronics Co Ltd | Programming non-volatile semiconducting memory involves applying voltage sequence to trough regions, programming voltage to word lines as trough area biased by coupling voltage |
US20020126532A1 (en) * | 2001-03-06 | 2002-09-12 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
US20040080980A1 (en) * | 2002-10-23 | 2004-04-29 | Chang-Hyun Lee | Methods of programming non-volatile semiconductor memory devices including coupling voltages and related devices |
US20050174852A1 (en) * | 2004-02-06 | 2005-08-11 | Hemink Gerrit J. | Self-boosting system for flash memory cells |
WO2005104135A1 (en) * | 2004-04-13 | 2005-11-03 | Sandisk Corporation | Programming inhibit for non-volatile memory based on trapped boosted channel potential |
WO2007078793A1 (en) * | 2005-12-19 | 2007-07-12 | Sandisk Corporation | Method for programming non-volatile memory with reduced program disturb using modified pass voltages |
WO2007089370A2 (en) * | 2005-12-28 | 2007-08-09 | Sandisk Corporation | Self-boosting method for flash memory cells |
-
2007
- 2007-09-19 WO PCT/US2007/078842 patent/WO2008039667A2/en active Application Filing
- 2007-09-20 TW TW96135141A patent/TWI378456B/en not_active IP Right Cessation
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107658A (en) * | 1997-02-27 | 2000-08-22 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
DE10164149A1 (en) * | 2000-12-28 | 2002-07-18 | Samsung Electronics Co Ltd | Programming non-volatile semiconducting memory involves applying voltage sequence to trough regions, programming voltage to word lines as trough area biased by coupling voltage |
US20020126532A1 (en) * | 2001-03-06 | 2002-09-12 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
US20040080980A1 (en) * | 2002-10-23 | 2004-04-29 | Chang-Hyun Lee | Methods of programming non-volatile semiconductor memory devices including coupling voltages and related devices |
US20050174852A1 (en) * | 2004-02-06 | 2005-08-11 | Hemink Gerrit J. | Self-boosting system for flash memory cells |
WO2005104135A1 (en) * | 2004-04-13 | 2005-11-03 | Sandisk Corporation | Programming inhibit for non-volatile memory based on trapped boosted channel potential |
WO2007078793A1 (en) * | 2005-12-19 | 2007-07-12 | Sandisk Corporation | Method for programming non-volatile memory with reduced program disturb using modified pass voltages |
WO2007089370A2 (en) * | 2005-12-28 | 2007-08-09 | Sandisk Corporation | Self-boosting method for flash memory cells |
Non-Patent Citations (1)
Title |
---|
ARITOME S ET AL: "RELIABILITY ISSUES OF FLASH MEMORY CELLS", PROCEEDINGS OF THE IEEE, IEEE. NEW YORK, US, vol. 81, no. 5, 1 May 1993 (1993-05-01), pages 776 - 788, XP000579999, ISSN: 0018-9219 * |
Also Published As
Publication number | Publication date |
---|---|
TWI378456B (en) | 2012-12-01 |
TW200822344A (en) | 2008-05-16 |
WO2008039667A2 (en) | 2008-04-03 |
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