TWI357603B - Reducing program disturb in non-volatile memory us - Google Patents

Description

1357603 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory. [Prior Art] Semiconductor 3 memory has become increasingly popular in various electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Erasable Programmable Read Only Memory (EEpR〇M) and Flash • Memory is among the most popular non-volatile semiconductor memories. In the case of flash memory (also a type of EEPROM), the contents of the entire memory array or the contents of a portion of the memory can be erased in a single step compared to a conventional full-featured EEPROM. Conventional EEPROMs and flash memories use floating gates that are above and insulated from the channel regions in the semiconductor substrate. The floating gate is located between the source and drain regions. The control gate is provided above and insulated from the floating gate. The threshold voltage (VTH) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between the source and the drain of the transistor is controlled by the charge level on the floating gate. Some EEPROM and flash memory devices have floating gates for storing two ranges of "charges, and thus the memory elements can be programmed between two states (eg, erased state and stylized state) / erase. Since each memory element can store one bit of data, such a flash memory device is sometimes referred to as a binary flash memory device. 126206.doc 1357603 A polymorphic (also known as multi-order) flash memory device is implemented by identifying a plurality of distinct allowable/effectively programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to an expected value of a set of data bits encoded in the memory device. For example, when each memory element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the e-element can store two bits of data.

Typically, the stylized voltage vPGM applied to the control gate during the stylization operation is applied as a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulse is increased by a predetermined step size with each successive pulse, for example, G2^.4v. I can be applied to the control bucks of the flash memory 7C device. In the period between the stylized pulses, the performing operation is also performed, that is, reading the stylized level of each of the group elements that are being parallelized in parallel between successively stylized pulses to determine that it is equal to It is also greater than the verification level to which the component is being programmed. For a multi-state flash memory device array, a verification step can be performed on each state of the component to determine if the component has reached its verification level associated with the data. For example, a polymorphic memory component that is capable of storing data in four states can perform a verification operation on two comparison points. In addition, when stylizing an EEPR〇M or a flash memory device (such as a "reverse" flash memory device), Vp(10) is typically applied to the control gate and the bit line is grounded. In turn, electrons from a channel of a cell or memory element (eg, a storage element) are injected into the floating interpole. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory component rises, causing the memory component to be considered to be in the stylized state of 126206.doc 1357603. Available under the heading "source Side Self B〇〇sting

This stylization can be found in US Patent Application Publication No. 2005/0024939, entitled "DetecUng 〇ver Programmed Mem〇ry", published in U.S. Patent No. 6,859,397, issued to, the entire entire entire entire entire content Further information; both patent documents are herein incorporated by reference in their entirety.

However, due to the proximity of the non-volatile storage elements to each other, various forms of program disturb have been experienced during stylization. In addition, it is expected that this problem will worsen with the further expansion of the "reverse" technology. Program disturb occurs when the threshold voltage of an unselected non-volatile storage element is shifted due to the stylization of other non-volatile storage elements. Various program interference mechanisms may limit (4) available operating windows for volatile storage devices (such as "reverse" flash memory). The boost technique attempts to boost the channel region of the "reverse" channel that is suppressed by stabilizing to a high potential and connect the channel region of the "reverse" string containing the storage element to be programmed to a low potential (such as G v) to solve this _ n given boost mode does not optimally solve multiple failure mechanisms. π [ SUMMARY OF THE INVENTION The present invention addresses these and other problems by providing a method for operating a non-volatile storage system that reduces program disturb. In one embodiment, a method for operating a non-volatile reservoir includes programming one of a set of non-volatile storage elements, wherein the set of non-volatile storage elements is in communication with a plurality of word lines, and the storing The component communicates with the - word line. The method further includes applying a set of the set of voltages to the unselected word lines and applying a first set of voltages to the unselected word lines to the unselected word lines based on the boost mode switching standard 126206.doc 1357603 A second set of voltages is applied to the unselected word lines. The first set of voltages is at least partially different from the second set of voltages. For example, the stylization can include applying a burst to a word line of 敎, wherein when a stylized pulse having a specified amplitude in the burst is applied to the selected word line, or when the pulse has been The boost mode switching criterion is triggered when a specified number of stylized pulses are applied to the selected word line.

In another embodiment, a method for operating a non-volatile reservoir includes performing a first boost mode during a stylized first stylization phase of a storage component in a set of non-volatile storage components, and continuing The second boost mode is implemented during the stylized second stylization phase of the health condition. The threshold voltage of the storage element increases from a first level to a second level during the first stylization phase and from a second level to a third level during the second stylization phase. In addition, the 'first stylization stage may include the number of times in the multi-pass stylization technique' and the second stylization stage may include the second pass of the multi-pass stylization technique. In one method, in a first stylization phase, a first subset of pulses in a burst is applied to the storage element 'and in a second stylized phase, a second pulse in the burst A subset is applied to the storage element. In another method, a first pulse train is applied to the storage element in a first stylization phase, and a second pulse train is applied to the storage element in a second stylization phase. In another embodiment, a method for operating a non-volatile reservoir includes staging a storage element in a set of non-volatile storage elements, wherein 126206.doc 1357603 is coupled with a non-volatile storage element and a pulse train. To... the storage line is wanted. The stylization includes the method of depositing the selected word line for 70 communications. The square is added to the first subset of the stylized pulses in the = string to apply the boost mode = = ;: the non-volatile storage (four) implements the second subset of the first-plus-formed pulse The selected non-volatile storage element is subjected to the first pressure switch to switch to the unselected non-volatile storage element to apply the second liter

The non-volatile storage stack can be provided in a plurality of "reverse" strings, including a selected "reverse" of the storage element and an unselected "reverse" string, wherein the first and second rise a modes will The channel of the "reverse" string that is not selected is boosted. In addition, in one method, 'implementing the first boost mode includes raising the channel so that the portion of the channel on the source side of the "reverse" string and the channel on the drain side of the "reverse" string Partial isolation, and implementing the second boost mode includes isolating portions of the channels on the source side of the "reverse" string from portions of the channels on the drain side of the "reverse" string. [Embodiment] The present invention provides a non-volatile storage system and method for reducing program interference. One example of a memory system suitable for use in practicing the present invention uses a "reverse flash memory structure that includes a plurality of transistors arranged in series between two select gates. The series transistors and the select gates It is called the "reverse" string. Figure 1 is a top view showing the "reverse" string. Figure 2 is its equivalent circuit. The "reverse" string depicted in Figures 1 and 2 includes four transistors 126206.doc • 11· 1357603 100, 102 connected in series and igniting between the first selection gate 120 and the second selection gate 122 , 104 and 106. The connection of the gate 120 gate control "reverse" string to the bit line 126 is selected. The connection of the gate 122 gate control "reverse" string to the source line 128 is selected. Controlled by applying an appropriate voltage to the control gate 12 〇 CG

. Select the gate 120. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 1〇〇, 1〇2, 104, and 106 has a control gate and a floating gate. The transistor 1 has a control gate 100CG and a floating gate i〇OFC^ transistor 1〇2 including a control gate 〇1〇2CG and a floating gate 102FG. The transistor 104 includes a control gate i〇4C(} and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate i〇〇cG is connected to (or is) a word line WL3, and is controlled. The gate 102CG is connected to the word line WL2, the control gate 1〇4 (:(} is connected to the word line WL1, and the control gate 1〇6CG is connected to the word line WL〇. In an embodiment, the transistors 100, 102 104 and 106 are each storage element, also referred to as a memory unit. In other embodiments, the storage element may comprise a plurality of transistors or may be different from the memory elements depicted in Figures i and 2. Gate 120 is connected to select line SGD. Select gate 122 is connected to select line SGS. Figure 3 is a circuit diagram of three "reverse" strings according to the edge. Typical architecture of flash memory system using "reverse" structure It will include a number of "reverse" strings. For example, in the memory array with more "reverse" _, two "reverse" strings 320, 340 and 360 are displayed. These are reversed in the string. Each of them includes two select gates and four storage elements. Although for the sake of simplicity: four storage elements Pieces, but modern "reverse", can have up to (for example) eleven or sixty-four storage elements. 126206.doc • 12- 1357603 For example and &, "reverse" string 320 includes selection gate 322 And 327 and storage elements 323 to 326 'reverse' string 340 includes selection gates 342 and 347 and storage elements 343 to 346. The "reverse" string 36 includes select gates 362 and 367 and storage elements to 366. Each "reverse" string is connected to the source line by its selection gate (for example, selection gate 327, 347 or 367). The selection line SGS is used to control the source side selection gate. The strings 32〇, 34〇 and 360 are connected to the respective bit lines 321, 341 and 361 by the selection transistors of the selection gates 322, 342, 362, etc. These selection transistors are controlled by the drain selection line SGD. In other embodiments, the select lines are not necessarily common in the "reverse" string. That is, different select lines may be provided for different "reverse" strings. Control of word lines WL3 connected to storage elements 323, 343, and 363 Gate. WL2 is connected to the control gate of the storage component ^ and π#. The word line WL1 is connected to the gate. The control gates of the components 325, Μ and 365. The word line WL is connected to the storage elements 326, 346 and the control gate of the 。. As can be seen, each bit line and the respective "reverse" string contain the memory. The array or set of lines of the word line (WL3, WL2, WL1, and WL0) contains the array or set of columns. Each word line connects the control gate of each storage element in the row. $, the control word can be word The line itself provides. For example, the word line WL2 provides control gates for the health elements 324, 344, and (10). In practice, there can be thousands of storage elements on a word line. Data can be stored for every 7L of storage. For example, when storing a bit of digital data dark, tech + eight, store a few pieces of possible threshold voltage (VTH) range of 7 two ranges 'assigning logical data to both ranges"1" and &quot ;0". In the case of the "Flash Memory" example, Vth is in the erase storage element 126206.doc • 13- 丄 is 7603 = negative, purely defined as logic, and Vth is positive after the stylization operation and is Defined as logical "〇". When Vth is negative and an attempt is made to read, the storage component will be turned on and the logic is "when Vth is positive and an attempt is made to perform a read operation. The firing element (4) is turned on. This refers to (4) storing logic"". The storage element can also store information of multiple levels, for example, digital data of multiple bits. In this case, the range of Vth values is divided into the data hierarchy of the number. For example, if you store four levels of information, there will be four VTH ranges, assigning data values to them, u ", "ι〇"', 〇1" and "(8)". In contrast to the "$memory-instance" example, Vth is negative after the erase operation and is defined as 'u'. The positive Vth value is used for the state "1" ", "〇1" and "(9)" . The special relationship between the data programmed into the storage element and the threshold voltage range of the component depends on the data encoding mechanism used for the storage component. For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Serial No. 2/4/255, filed to the entire disclosure of Data encoding mechanism.

Examples of anti-J-type flash memory and its operation are provided in U.S. Patent Nos. 5,386,422, 5,522,580, 5,570,315, 5'774,397, 帛6, 〇46,935, 帛6,456,528, and 6,522,580. Each of these is incorporated herein by reference. When the flash storage component is programmed, a programmed voltage is applied to the control gate of the storage device and the bit line associated with the storage component is grounded. The electrons from the channel are > mastered into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the Vth of the storage element rises. To apply a stylized voltage to the control gate 126206.doc 1357603 pole of the memory element being programmed, this stylized voltage is applied to the appropriate word line. As described above, one of the storage elements in each of the "reverse" strings shares the same word line. For example, when the storage element 324 of Figure 3 is programmed, the programmed voltage will also be applied to the control gates of storage elements 344 and 364. However, during the stylization of other "reverse" strings, program disturb may occur at the suppressed "reverse" string, and sometimes program disturb occurs at the stylized "reverse" string itself. For example, if the "reverse" string 320 is suppressed (eg, it is an unselected "reverse" _) that does not contain the currently stylized storage element and the "reverse" string 34 is being stylized ( For example, if it is a selected "reverse" string containing the currently stylized storage element, program disturb may occur at the "reverse" string 320. For example, if the turn-on voltage VPASS is low, the suppressed "reverse" channel will not be boosted well, and the selected word line of the unselected "reverse" string can be unintentionally programmed. In another possible case, the boosted voltage can be reduced by gate-induced drain leakage (GIDL) or other leakage mechanisms, which can cause the same problem. Other effects, such as shifting of charge stored in a stylized storage element due to capacitive coupling between storage elements, can also be problematic. Figure 4 depicts a conceptual diagram showing the boost mode decision process. As mentioned at the outset, program disturb remains a significant problem for non-volatile storage systems. Program disturb occurs when the threshold voltage of an unselected non-volatile storage element is shifted due to the stylization of other non-volatile storage elements. Program disturb can occur on previously stylized storage elements and on erased storage elements that have not been programmed. Various program disturb mechanisms can limit the available operating windows of non-volatile storage devices (such as 126206.doc -15·1JJ / ou^). For example, boosting techniques attempt to boost the channel region of the suppressed "reverse" string to a high potential and connect the channel region containing the "reverse" string of the storage element to be programmed to a low potential ( For example, QV) to solve this problem. Heart, given boost • _ type does not optimally solve multiple failure mechanisms. That is, the given wish mode σ effectively addresses the specific program interference failure mechanism but may be inefficient in solving other failure mechanisms. Typically, the boost mode is traded off or optimized to give the best operating window. Here, it is recommended to use different boost modes during stylization to better optimize boost. For example, in one method, a boost mode is used during initial stylization and a second boost mode is used at the end of a stylized single page or word line to improve the total margin relative to program disturb. . * Various standards can be used to determine which boost mode to use, & when switching from a boost mode to another boost mode. As an example, the three different boost modes indicated at blocks 4A, 4〇5, and 41〇 can be selected by the lift mode decision process (block 415). The boost mode includes, for example, self-boost (SB), local self-boost (LSB), erased area self-elevation (EASB), and modified erase area self-boost (REASB), discussed further below. Once a decision is made, the selected boost mode is applied (e.g., block 420) by applying a set of voltages corresponding to the selected boost mode to the unselected word line. For example, the boost mode switching decision process (block 415) may use one or more boost mode switching criteria (block 425). Such criteria may include the number of programmed pulses (block 430), the programmed pulse amplitude (block 435), the programmed pass number (block 440), the location of the selected word line (block 445), rough/ Fine stylization 126206.doc • 16-1357603 mode state (block 450), storage component 455), and pinning through the body, stylized condition (block 460). The number of shields (blocks = times =: (example W stylized ... first - over - people are still in progress for the first time. The criteria for the conditions can be (for example) by detecting a group of two :(=To Cheng:

The first storage element or part of the storage element in the block or array is tested: == implemented. When the verification condition is reached, the number of standards that can be issued can be implemented, for example, by tracking the number of stylized cycles and adjusting the switching point on a 2 basis. For example, if a switching point occurs during a burst, the switching point can occur relatively early in the burst after the memory device has experienced a relatively large number of cycles because the storage element is additionally stylized in the scripture. Loops tend to be faster programmed. The boost mode switching standard is described in more detail below. = Figure 5 depicts the process used to switch the boost mode during stylization. The conceptual diagram presented above can be further understood based on the flow chart. At step 5, stylization begins, and at step 51, the first boost mode is applied. At decision step 520, if the switching criteria are met, then switching to the second boost mode (step 530) and the programming continues (step 54A) until it is complete (step 550). If the switching criteria are not met at decision step 52, the first boost mode continues to be applied and the stylization continues (step 525). Typically, the boost mode is implemented by one or more control circuits of the configuration memory device to apply an appropriate voltage to the word line in communication with the set of storage elements. 126206.doc 1357603 The decision to switch the boost mode can be based on many factors. In general, it is necessary to implement a boost mode that is optimal for the current stylization mechanism and the current conditions of the storage component and the "reverse" string. For example, a non-EASB# voltage mode (such as SB or LSB) can be relatively efficient for initial stylized pulses (when VpGM is low), while EASB boost mode (including REASB) is for higher stylized pulses (in VPGM) High time) can be relatively effective. In this case, based on

The amplitude of Vpgm is switched from non-EASB mode to EASB mode. another

In addition to the programmed pulse amplitude, the fault mode responds to many stylized pulses. In this case, the knife change from the non-easb mode to the easb mode can be made based on the number of stylized pulses (which are usually associated with VpGM). In addition, some of the ups and downs modes can be advantageously based on the selected word line in him. The position in the subline. Typically, the operating window can be defined by a plurality of boosting modes that result in an acceptable lower failure rate, depending on the particular non-volatile storage device. Figure 6 depicts a self boosting mode implemented via a plurality of word lines. As mentioned, 'the various types of <boost mode have been developed to combat the program." The boost mode is implemented during the staging of the storage element on the selected word line by applying a set of voltages to the unselected m lines in communication with the currently unprogrammed storage. The storage element being coded is associated with the selected "reverse" string and the other storage elements are associated with the unselected "reverse" string. Programmatic interference usually involves storage elements in unselected "reverse" strings, but may also occur due to other storage elements in the same "reverse" string. In the method, the self-boost mode is depicted 600 by an example word line that communicates with the set of storage elements disposed in the "reverse" string. In this example, there are eight word lines labeled 126206.doc 1357603 as WLO to WL7 (eg, control lines), source side select gate control lines labeled SGS, and immersed side select poles labeled sgd Control line. A set of voltages applied to the control lines is also depicted. As the 'description, specify WL4 as the selected word line. From the source side of the "reverse" string, the voltage on the side of the money side is usually 'stamped every time the voltage is applied to the word line ^ includes: vSGS ' applied to the source side select gate control line sgs; turn-on voltage VPASS, It is applied to the mother of the unselected word lines WL〇 to WL3 and WL5 to φ, the programmed voltage vPGM applied to the selected word line WL4; and VSGD, which is selected via the drain side selection gate control line sqd Apply. Typically, VSGS is 0 V, causing the source side select gate to turn off. It is about 2.5 V, so that due to the fine addition of the corresponding low bit line voltage Vbl (such as 〇 to i V), the gate selection gate is turned on for the "reverse" string of the selected one. Due to the application of a correspondingly higher VBL (such as 1.5 to 3 V), the gate is closed for the "reverse" string of the unselected 没. In addition, VPASS can be about 7 to 10 v, and VpGM can vary between about 12 and 2 〇 v. In a stylized mechanism, a burst of stylized voltage is applied to the selected word line. See also Figure 23 and Figure 24. The amplitude of each successively programmed pulse in the burst increases in a stepwise manner, typically increasing by about 〇.3 to 0.5 V per pulse. Alternatively, a verify pulse can be applied between the stylized pulses to verify that the selected storage element has reached the target stylized condition. Note that each individual stylized pulse can also have a fixed amplitude ' or can have a varying amplitude. For example, §, some stylized mechanisms apply pulses whose amplitude changes in a ramp or step manner. Any type of stylized pulse can be used. In the case where WL4 is a stylized word line and is programmed to advance from the source 126206.doc 19 1357603 side of each "reverse" string to the drain side, it is stylized when the component is being programmed on WL4. A storage element associated with WLO to WL3, and the storage elements associated with WL5 through WL7 will be erased. The turn-on voltage on the unselected word line is coupled to the channel associated with the unselected "reverse" string such that there is a voltage in the channel that tends to reduce the voltage across the oxide of the storage element. Reduce program interference. Figure 7 depicts a local self-boosting (LSB) mode implemented via a plurality of word lines. In one method, the local auto-boost mode is depicted 700 by an example word line that communicates with a set of storage elements disposed in a "reverse" string. The local auto-boost differs from the self-boost mode of Figure 6 in that the word line adjacent to the selected word line receives an isolation voltage VIS0 of 0 V or another voltage close to 0 V instead of VPASS. The remaining unselected word lines are in VpASS. Local auto-boost attempts to reduce program disturb by isolating the channels of previously stylized storage elements from the channels of the storage elements being suppressed. Although the LSB mode is effective for lower value vPGMs, the disadvantage of the LSB mode is that the voltage of the boosted channel below the selected word line can be very high when VpGM is high' because the channel is the other one. Some are isolated from other channel areas below the unselected word line. Therefore, the boost voltage is mainly determined by the higher stylized voltage vpgm. Due to the higher boost' near the word line biased to 〇 V, band-to-band tunneling or gate-induced drain leakage (GIDL) can occur. The channel boost can be limited to a lower value by using the erase region self-boost (EASB) or modified EASB (REASB) modes discussed below. Figure 8 depicts an erase region self-boost mode implemented via a plurality of word lines. In one method, the EASB mode is depicted by an example word line that communicates with the set of 126206.doc -20- 1357603 storage elements disposed in the "reverse" string. Easb is similar to LSB' in that only the source side adjacent word line wL3 is in isolation [Vis〇-0 V ' such that the undesired "reverse" string is boosted on the source and drain sides. Channel isolation. The channel area below the selected word line is connected to the channel area at the drain side of the selected memory element such that the channel boost is primarily determined by VpAss applied to the unselected word lines instead of VpGM. See also Figure 13. The drain side adjacent word line WL5 is at VpAss. If να"

Low, the boost in the channel will not be enough to prevent program interference. However, if VPASS is too high, the unselected sub-lines in the selected "reverse" string can be programmed (where the bit line is at 〇 V), or program disturb due to GIDL can occur. Figure 9 depicts a first modified erase region self-boost mode implemented via a plurality of word lines. In one method, first! The eight-figure mode is depicted by an example word line that communicates with a set of storage elements disposed in the "reverse" string. The REASB is similar to the EASB but applies a smaller isolation voltage Vls 〇 (such as 25 v) to the adjacent isolated word line (eg, WL3). Figure 10 depicts a second modified erase region self-boost mode implemented via a plurality of word lines. In one method, the second REASB mode is depicted by an example word line in communication with the set of storage elements disposed in the "reverse" string. In this case, the plurality of VS0s applied by VIS0 to the source side of the selected word line WL4 may be progressively reduced, e.g., from word lines on wl3, such as WL2 and WL3. value. For example, 4 V of the same Viso or different V丨s〇 can be used to reduce to 2_5 V on WL2. Various other methods are also available. For example, 'vIS0 can be applied to three adjacent word lines (eg, to 126206.doc -21·1357603 WL3). 'In this case' the last word line (WL1) receives the lowest vls〇, and WL2 And WL3 receives the common VIS0. Figure 11a depicts a third modified erase region self-boost mode implemented via a plurality of word lines. In one method, the 'third REASB mode is depicted by an example word line that communicates with the set of storage elements disposed in the "reverse" string. In this case, when vPGM has a relatively low value (represented by Vpgm l〇w), a relatively low on-voltage (represented by vPASS_LOW) is applied to one of the end word lines (eg, WL0 and WL7). Or both, and the usual, higher vPASS is applied to other unselected word lines. For example, if it varies between 12 and 20V' then VPGM-L0W can represent a range of 12 to 16V. This boost mode resolves the program interference mechanism that affects the end word line. Specifically, 'the right VPASS with the same value is applied to all unselected word lines (including the end word lines), due to the slow rate of injecting electrons into the storage elements associated with the end word lines' Leakage or GIDL can occur on the gate. The boost mode depicted can solve this problem. In addition, '荽VpGM is in the range of the car's south (expressed by VpgM-HIGH), for example, in the range of 16 to 20 V, as depicted in Figure 1113, the turn-on voltage on the end word line can be raised back. To the level of other unselected word lines, for example, to VPASS. Alternatively, the turn-on voltage of the end word line can be raised to the intermediate level VPASS-INT, which is less than vPASS but greater than VpASS-LOW 0. Figure lib depicts the fourth modified erase region implemented via a plurality of word lines. Boost mode. In one method, the fourth REASB mode is depicted by an example word line that communicates with the set of storage elements disposed in the "reverse" string. 126206.doc •22· 1357603 Here, when the VPGM on the selected word line WL4 is in the higher range of values (represented by VPGM-High), the on-voltage of the end word lines (WLO and WL7) is raised back. To other unselected word lines, for example, to Vpass ° In addition, different boost modes can be implemented based on the position of the selected word line. For example, when a boost mode switch occurs during a burst, switching can occur at a location in the burst based on the relative position of the selected word line. In a method, the switching from SB or LSB to EASB or REASB occurs relatively late in the burst when the selected word line is relatively close to the unpolarized side of the unselected "reverse" string. Figure 11c depicts a fifth modified erase region self-boost mode implemented via a plurality of word lines. In one method, the fifth REASB mode is depicted by an example word line that communicates with the set of storage elements disposed in the "reverse" string. This boost mode is similar to the boost mode of Figure 11a, but uses lower vPASS (vPASS.L0W) for each of the unselected word lines when VpGM is in the lower range (represented by Vpgm_l〇w) . When vPGM reaches a higher range (represented by Vpgm high), this mode can be followed by the boost mode of Figure lib. Various other combinations are also possible. For example, the VpASS of unselected word lines other than the end word line can be higher than the VPASS of the end word line, regardless of vPGM. Additionally, there may be more than two VpGM ranges that trigger a change in boost mode. Figure 12 depicts a timeline showing how rough and fine stylization can be achieved by setting the bit line suppression voltage. As mentioned, the switching of the boost mode can occur based on the coarse/fine mode stylized state. Rough/Fine Stylization The threshold voltage (VTH) of the allowed storage element is first increased to a desired level faster during the coarse stylization than 126206.doc -23- 1357603 and then slowly during fine stylization. For this given a lower stylized state and a higher verify level vH, respectively, for a given stylized state. In particular, coarse stylization occurs when the voltage threshold is lower than V1, and fine-grained when the voltage threshold is between & and ¥11. Rough/fine stylization provides a tight voltage distribution to the stylized storage elements. See also Figure 21d. Curve 1200 indicates the change in Vth of the storage element over time, while curve 1250 indicates the bit line voltage (vBL) applied to the bit line associated with the storage element. The stylization of the storage element can be slowed down by providing a bit line suppression voltage vpartial ινηιβιτ, which counteracts the effects of the applied stylized voltage pulses. When vTH exceeds %, vFULL ΙΝΗΙΒ1Τ is applied to the bit line to place the storage element in the inhibit mode, in which the storage element is locked from further stylization and verification. Different 1 and VH values can be associated with different states of the polymorphic storage element (e. g., states A, 8 and C) to allow for coarse/fine stylization of different states. Suppressing the voltage slows down the stylization and thereby allows for more precise control of the stylized voltage threshold level. In one method, 'VPARTIAL INHIBIT (usually 0 5 to 1 () v) reduces the electric field across the oxide and passes it to the "reverse" string during stylization. This situation requires that the gate voltage be chosen high enough to pass this voltage, typically 25 V. In addition, the reduced step size in the VPGM burst can also be used to provide a fine stylized mode. This can be done with or without a suppression voltage on the bit line. Thus, in one method, when a single burst of stylized pulses is applied to a selected word line, it can be determined by determining that a certain number of storage elements (eg, one or more) have reached a lower verify level. Rough stylized mode 126206.doc -24- Γ=fine stylized mode to use coarse/fine stylization. In addition, the :,: stylization mechanism can use coarse/fine stylization, in which the staging is used in π-pass people to program the storage element to be close to the temporary (four) condition, and use in the second pass. Stylized to stylize storage elements from temporary stylization conditions to final gasification conditions. Different VPGM ranges can also be used for stylized programming. For example, δ ' VPGM range can be (for example) used in the first pass since the rough stylization The next time to 20 V is reduced to i 4 to 20 V in the second pass when fine-stylization is used. Figure 13 depicts a t^Easb (such as depicted in Figure 8) or reasb (such as the one depicted in Figure 9) In the case of a stylized area and an erased area, the unrestricted cross-section of the "reverse" string. This view is simplified and not drawn to scale. The "reverse" string 13 includes a source side selective closed pole 1306 formed on the substrate 139, a gateless select gate 1324, and eight storage elements 13A, 1310, 1312, 1314, 1316, 1318, 1320 and 1322. The components can be formed on the n well region on the p-well region of the substrate. In addition to the bit line 1326 (bit line) having the potential vdd, a source supply line 1304 having a potential Vs〇urce is provided. During stylization, VpGM is provided on the selected word line (in this case, WL4), which is associated with storage element 1316. In addition, it is reiterated that the control gate of the storage element can be provided as part of the word line. For example, 'WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 may extend through the control gates of storage elements 1308, 1310, 1312, 1314, 1316, 1318, 1320, and 1322, respectively. MVIS0 is applied to the source side word line (WL3, referred to as the isolated word line) of the selected word line. 126206.doc -25 - 1357603 vPASS is applied to the remaining word lines associated with the "reverse" string 1300. VsGs is applied to select gate 1306 and germanium (10) is applied to select idle 1324. It is assumed that the stylized storage element of the storage element along the "reverse" string is advanced from the storage element 1308 to the storage element 1322, and is stored when other "reverse" strings, t and WL4 associated storage elements are being programmed. The components will then be programmed, and the storage elements 1318 through 1322 will not be programmed. Note that when the "reverse" string 1300 is suppressed, the storage element 1316 is not programmed. Thus, depending on the stylized mode, all or some of the storage elements 13〇8 to 1314 will have electrons that are programmed into and stored in their respective floating gates, and can be erased or partially programmed to be stored. Elements 1318 to 1322. For example, storage elements 1318 through 1322 may have been previously programmed in the first step of the two-step stylization technique. Additionally, in the case of the EASB or REASB boost mode, a sufficiently low isolation voltage VIS0 is applied to the source side neighbors of the selected word line to isolate the private and erase channel regions in the substrate. That is, a portion of the channel (eg, region 1350) of the substrate on the source side or the stylized side of the unselected I "reverse" string and the drain side of the unselected "reverse" string or not One of the channels on the stylized side (eg, area 136〇) is isolated. The channel region 135 is boosted by applying VPASS to WL0 to WL2, and the channel region 13 60 is boosted by applying Vpgm to WL4 and applying vPASS to WL5 to WL7. Because VPGM is dominant, erase region 1360 will experience a relatively higher boost than stylized region 135. Figure 14 illustrates an example of an array of "reverse" storage elements, such as the arrays shown in Figures 1 and 2. Along each row, the bit line 丨4〇6 is coupled to the “reverse 126206.doc • 26 - 1357603 and the string 1450 of the drain select terminal of the drain terminal 1426. Along the respective columns of the "reverse" string, the source line 14〇4 can be connected to all source terminals 1428 of the source selection gate of the "reverse" string. Examples of "reverse" architecture arrays and their operation as part of a memory system are found in U.S. Patent Nos. 5,57,315, 5,774,397, and 6,6,935. The array of storage elements is divided into a plurality of storage element blocks. As is common to flash EEPROM systems, the block is the unit of erasure. That is, each block contains a minimum number of storage elements that are erased together. Each block is usually divided into a number of pages. The page is a stylized unit. In an embodiment, individual pages may be divided into segments and the segments may contain a minimum number of storage elements that are written once with the basic programming operation. The data of one or more pages is typically stored in a list of storage elements. The page can store one or more sectors. The sector includes user data and additional information. The additional data is an error correction code (ecC) calculated from the user data of the sector. One part of the controller (described below) calculates the ECC when the data is programmed into the array, and also checks £(:(:. or, if ECC and/or other additional data is stored in it) when reading the data from the array. The user data is in different pages or even different blocks. The user data of one sector is usually 512 bytes, which corresponds to the large additional data of the fan n in the disk drive. Up to 2 locations. A large number of pages form blocks from 8 pages (for example) up to 32, 64, or more pages. In some embodiments, a column of "reverse" strings contains a block. In the practical example, by raising the P well to the erase voltage (for example, 20 V) 126206.doc -27· 丄妁 7603 for a sufficient period of time and when the source line and the bit line are floating, the selection is made. The word line of the block is grounded to erase the memory storage element. Due to the capacitive coupling, the unselected sub-line, bit line, select line, and C· source are also raised to this, and most of the erase voltage Therefore, a strong electric field is applied to the tunneling oxide layer of the selected storage element, and The data of the selected storage element is usually erased by the Fowler-Nordheim tunneling mechanism when the electrons of the pre-grating gate are emitted to the substrate side. When the electron self-floating gate is transmitted to the ρ well area, the selected storage element is selected. The threshold voltage is reduced. The erase can be performed on the entire memory array, the independent block, or another unit of the storage element. Figure 15 is a non-volatile memory system using a single column/row decoder and a read/write circuit. The present invention illustrates a memory device 1596 having a read/write circuit for reading and programming a page of storage elements in parallel, in accordance with an embodiment of the present invention. The memory device 1596 can include a Or a plurality of memory crystal grains 1 598. The memory crystal grains 1 598 include a 2D dimensional array of storage elements, a control circuit 151A, and a read/write circuit 1565. In this case, the material array is The memory 1400 can be addressed by a bit line from the sub-line and via the row decoding device και. The read/write dry-circuit 1565 includes a plurality of sensing regions. Block 15 and. Allow reading in parallel Or stylized a storage element of a hundred products. Typically, the controller 1550 is included in the same memory device 1596 as the one or the other control *' 〇Μ 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日ρ» λ-., ). Between the host and the controller 1550, the command 15K and the resource are transmitted via the line 1520, and the controller and the 5 or more hidden crystals 15 9 8, λ 密 secret! c, left to send commands and data by line 1518. Control circuit 1510 and read / λ λ $ '', circuit 1 565 cooperate to memory array 126206.doc • 28 · 1357603 Column 1400 performs a memory operation. The control circuit 1 5 10 includes a state machine 1 52, a crystal address decoder 15 14 and a power control module 1516. The state machine 15 12 provides a wafer level control for the memory operation of the β crystal carrier address decoder 丨 5 14 at the address used by the host or § memory controller and the hardware address used by the decoders 1530 and 1560. Provide a bit interface between them. Power control module 1 5 16 controls the power and voltage supplied to the word lines and bit lines during the memory operation.

In some embodiments, some of the components of Figure 5 can be combined. One or more of the components (individually or in combination) other than the array of storage elements can be considered as management circuits in various designs. For example, one or more management circuits may include control circuit 1510, state machine 1512, decoder 1514/1560, power control 1516, sensing block 15A, read/write circuit 1565, controller 1550, etc. Any one or combination.

Figure 16 is a block diagram of a non-volatile memory system using a dual column/row decoder and a read/write circuit. Here, another configuration of the memory device 1596 shown in FIG. 5 is provided. Access to the memory array; U00 by various peripheral circuits is performed symmetrically on opposite sides of the array such that the density of access lines and circuitry on each side is reduced by half. Therefore, the column decoder is divided into column decoders 1530A and 1530B, and the row decoder is divided into row decoders 15A and B60B. Similarly, the read/write circuit is divided into a read/write circuit 1565 connected to the bit line from the bottom of the array 14A and a read/write connected to the bit line from the top of the array 14A. In this manner, the circuit 1565 Β β has substantially reduced the density of the read/write module—half. As described above with respect to the apparatus of Fig. 15, the apparatus of Fig. 16 may also include a controller. Figure 17 is a block diagram of an embodiment of a marginal sensing block. Will be individually sensed 126206.doc •29· 1357603

The block 1500 is divided into a core portion (referred to as a sensing module I) and a common portion 1590. In one embodiment, a separate sensing module 1580 will be present for each bit line, and a common portion 1590 will be provided for one of the plurality of sensing modules 1580. In one example, the sensing block will include a common portion 1 590 and eight sensing modules 1580 « - each of the sensing modules in the group will be associated via data bus 1572 The common part is wanted. For more details, please refer to the title of "N〇n_v〇Utile Mem〇ry & published in the text of June 29, 2002 and incorporated by reference in its entirety.

Method with Shared Processing for an Aggregate of Sense Amphflers " US Patent Application Publication No. 2/6/〇i4〇〇〇7. A sensing module 1580 includes a sensing circuit 判定 57 判定 that determines that the conduction current in the connected bit line is still below a predetermined threshold level. The sensing module 1 also includes a bit line latch 1582 for setting a voltage condition to the connected bit line. For example, the pre-locked bit in the bit line latch 1582

The shape L will cause the connected bit line to be pulled toward the specified stylized suppression state (e.g., Vdd). The common portion 1590 includes a processor 1592, a f-fed set 1594, and a !/〇 interface 1596 between the data latch set (10) and the data bus 15 . The processor 1592 performs computations in which the functions are stored in the sensed storage elements and the determined data is stored in the set of registers 1594 for storage in the set of latches. The data: _ is determined by the processor 1592 during the ° fetch operation: the data bit. It is also used to store the data from the data stream during the stylized operation; The input data bit indicates the intended process 126206.doc -30* 1357603 The data is written into the memory. The I/O interface 1596 provides an interface between the data latch 1594 and the data bus 152A. During reading or sensing, the operation of the system is controlled by state machine 1512, which controls the supply of different control gate voltages to the addressed storage elements. The sensing module 丨58〇 can jump at one of the voltages when it is stepped through various predetermined control gate voltages corresponding to various memory states supported by the memory. Off, and the output will be provided from the sensing module 1580 to the processor 1592 via the bus bar 572. At this time, the processor 1592 determines the obtained memory state I by considering the tripping event of the sensing module and the information about the applied control gate voltage from the state machine via the input line 丨593, and then about the 5 The binary code is calculated by recalling the body cancer and the resulting data bits are stored in the data latch 1 594. In another embodiment of the core portion, bit line latch 1582 is used for dual purposes, both as a latch for latching the output of sense module 580 and also as described above. Meta line latch. It is contemplated that some embodiments will include multiple processors 1592. In an embodiment, each processor 1592 will include an output line (not depicted in Figure 7) such that each of the output lines are commonly lined or connected. In some embodiments, the output line is inverted before the output line is connected to the line or line. This configuration allows for a quick determination of the time at which the stylization process is completed during the stylized verification process 'because the receive line or state machine can determine when all bits being programmed have reached the desired level," for example, each When a bit has reached its desired level, the logical zero of that bit will be sent to the line or line (or the data is inverted). When all bits output data (or reversed data one), 126206.doc •31 · 1357603 and the state machine knows to terminate the stylization process. Because each processor communicates with eight sensing modules' so the state machine needs to read lines or line people or logic is added to processor 1592 to accumulate the results of the associated bit lines, so that the state machine only needs to read Line or line - times. Similarly, by correctly selecting the logic level, the overall state machine can detect when the first bit changes its state and thus change the algorithm. During the stylization or verification, the program will be sent from the data bus 152

The data is stored in the data latch set. Under the control of the state machine, the stylized operation includes a series of stylized electrical secrets applied to the control idles of the addressed storage elements. Each stylized pulse is read back (verified.) to determine if the storage element has been programmed to the desired memory state. The processor 1592 monitors the memory state of the readback with respect to the desired memory state. When the two states coincide, processor 1592 sets the bit line latch to cause the bit line to be pulled toward the specified stylized suppression state. This situation suppresses storage elements that are lightly connected to the bit line from being step-by-step programmed, even if the program

The same applies to the presence of a pulse on its control gate. In other embodiments, the processor initially carries the bit line latch 1582 and the sensing circuit sets it to the suppression value during the verification process. The data latch stack 1594 contains a stack of data latches corresponding to the sense modules. In one embodiment, there are three data latches per sensing module 158. In some embodiments (but not necessarily), the data latch = implemented as a shift register 'so that parallel data stored therein is converted to serial data for data bus 1520' and vice versa . In a preferred embodiment, all of the 126206.doc • 32-1357603 material latches corresponding to the read/write blocks of the m storage elements can be linked together to form a block shift register. This allows the block of data to be input or output by serial transfer. In particular, the set of I read/write modules is adapted such that each of its set of data latches sequentially shifts data into or out of the data bus as if it were used for the entire read. The part of the shift register of the fetch/write block is the same. Additional information regarding the structure and/or operation of various embodiments of the non-volatile storage device can be found in the following: (1) U.S. Patent Application Publication No. 2/4/ filed on March 25, 2004. U.S. Patent No. 57,287, NN-Volatile Memory And Method; (3) U.S. Patent Application Serial No. 11/015,199, filed on Dec. 16, 2004, entitled "Improved Memory Sensing Circuit And Method For Low Voltage Operation"; (4) in 2005 4 U.S. Patent Application Serial No. i ^99^33, entitled "Compensating for Coupling During Read Operations of Non-Volatile Memory"; and (5) U.S. Patent Application filed on December 28, 2005 No. 11/321,953, entitled "Reference Sense Amplifier For Non-Volatile Memory". All of the five patent documents listed above are hereby incorporated by reference in their entirety. 18 illustrates an example of organizing a memory array into blocks for a full bit line memory architecture or for a parity memory architecture. An exemplary structure of the storage element array 1400 is described. As an example, the description is divided into ι, 〇 24 District 126206.doc -33· 1357603 Block "Reverse" flash EEPR0M. The data stored in each block can be erased at the same time. In an embodiment, the block is the smallest unit of storage elements that are simultaneously erased. In each block, in this example, there are 8,512 rows corresponding to the bit •1 line BL0, the sin...·BL85U. In an embodiment referred to as a full bit, line (ABL) architecture (architecture 181G), all bit lines of a block can be selected simultaneously during read and program operations. Storage elements along a common word line and connected to any bit line can be programmed simultaneously. φ "In the example provided, four storage elements_ are connected in series to form a "reverse" string. Although four storage elements are shown to be included in each "reverse" string, more or less than four (e.g., i6, U, 或 or another number) may be used. The "reverse" rate - the terminal is connected to the corresponding bit line via the immersive selection pole (connected to the selected gate drain line SGD), and the other terminal is connected to the selection gate via the source selection gate The source line SGS) is connected to the c-source. In another embodiment, referred to as an odd-even architecture (architecture 18), the bit art lines are divided into even bit lines (BLe) and odd bit lines (BL〇). In the odd/even bit line architecture, the storage elements along the common word line and connected to the odd bit lines are programmed at one time and stylized along the common word line and connected to the even bits at another time. The storage component of the meta line. The data can be stylized at the same time. The product is read from different blocks. In this example, there are 8,512 rows in each block, which are divided into even rows and odd rows. In this example, four storage elements are connected in series to form a "reverse" string. Although not four storage elements are included in each "reverse", more or less than four storage elements can be used. 126206.doc •34· 1357603 During the configuration of one of the fetching and stylizing operations, the component is also selected. The selected storage component has a bucket - a b-bit with the same line and the same type of 7L line (for example, even or odd letters read or programmatically form a logical page of 532 bytes) And the memory-area machine can store at least eight logical pages (four word lines, each with odd and even pages). For polymorphic storage elements, when each storage element stores two bits Information (in which one of the bits

Stored in different sides)—The block stores sixteen logical pages. Blocks and pages of other sizes can also be used. For an ABL architecture or an odd-even architecture, 70 pieces of memory can be erased by raising the p-well by a voltage (e.g., 20 V) and causing the word of the selected block to be erased. The source line and the bit line are floating. Erasing can be performed on the entire memory array, on a separate block, or on another unit of the storage element of the memory device. The floating gate of the electronic self-storage component is transferred to the P well region such that the VTH of the storage component becomes negative. In read and verify operations, select gates (SGD and SGS) connected to voltages in the range of 2. 5 V to 4·5 v and unselected word lines (eg, when WL2 is the selected word line) The time is up, and the machine 3) is raised to the read: voltage Vread (typically a voltage in the range of 4.5 乂 to 6 V) to operate the transistor as a turn-on gate. The selected word line milk 2 is connected to a voltage, which is referred to for each read and verify operation to determine whether the VTH of the associated storage element is above or below this level. For example, in a read operation of a two-stage storage device, the selected word line WL2 can be 'whether or not the VTH is higher than 〇 V. For example, in the verify operation of the double-order storage element 126206.doc -35 - 1357603, the selected word line WL2 is connected to 〇 8 v so that it is verified whether the VTH has reached at least 〇.8 V. The source and p wells are 选定 The selected I line (assumed to be an even bit line (BLe)) is precharged to, for example, 〇 7乂2. If VtH is above the read or verify level on the word line, the potential level of the bit line (BLe) associated with the associated memory element is maintained at the level due to the non-conductive memory element. The other side;, very v. For the aspect right Vth is lower than the read or verify level, the potential level of the associated bit line (BLe) is reduced to a low level (for example, less than 〇.5 V) because the conductive material The component discharges the bit line. The state of the storage element can thereby be sensed by a voltage comparator connected to the bit line. The above-described erasing, reading, and inspection are performed in accordance with techniques known in the art: intervening, many of the details explained may be used in the art, as well as other erasing, readings known in the art. Take the verification technology. Figure 19 depicts the continuation of the threshold voltage. An example of a storage element array is provided for each storage element in the condition of eight bits of data: cloth. Provide a first-to-be-limited distribution E for the storage elements other than _. ρ . Three threshold voltage distributions A, B and L ° of the storage element In one embodiment, the threshold voltage in the ^ . b blade is negative and the threshold voltage in the distribution is Λ, B and (: Positive value: ^ The limit voltage range corresponds to the threshold voltage level of the data and storage elements used in the predetermined data set of the data bits. The relationship between the parameters and the storage elements depends on the data used for the storage elements. For example, the encoders are incorporated by reference in their entirety in U.S. Patent No. 126,206, filed on Jun. No. 6,222,762, filed on Jan. No. describes various data encoding mechanisms for multi-state flash storage elements. In one embodiment, gray code assignments are used to assign data values to a threshold voltage range such that the threshold of the floating gate is When the voltage is erroneously shifted to its neighboring entity state, it will only affect one bit. One case assigns "11" to the threshold voltage range E (state E), and assigns "1 〇" to the threshold Voltage range A (state A), assigning "〇〇" to the threshold voltage Lu B (state B) and assign "01" to the threshold voltage range C (state c). However, in other embodiments, the Gray code is not used. Although four states are shown, the invention may also be used For other polymorphic structures, including polymorphic structures that include more or less than four states. Three read reference voltages Vra, Vrb, and Vrc are also provided for reading data from the storage element. Whether the threshold voltage of the storage element is higher or lower than Vra, Vrb and Vrc, the system can determine the state in which the storage element is located, such as a stylized condition. • In addition, three verification reference voltages Vva, Vvb and VVC are provided. When storing 70 pieces of code into state A, the system will test whether these storage elements have a threshold dust greater than or equal to Vva. When the storage element is programmed to • state B, the system will test whether the storage element has Greater than or equal to μ • = & power limit M ° When the storage component is programmed to state C, the system will determine whether the storage component has its threshold voltage greater than or equal to Vvc. Implementing a shot (4) The self-erasing state of the memory component can be directly simplified to the stylized state. For example, γ first erases the population of the storage component to be programmed, I26206.doc -37- 1357603 makes the group All of the storage elements are in an erased state E. The storage elements are then directly programmed to state A, B or C using a series of stylized pulses such as those depicted by the control gate voltage sequence of Figure 23, although some of the storage elements are From state E to state a, but other storage elements are from, state E is programmed to state B and/or from state e to state c. When staging from state E to state on WLn, the amount of parasitic coupling to the adjacent floating gate below wLnj is the largest because it is stylized from state E to state A or from state E to The change in voltage at state B is greater than the change in the amount of charge on the floating gate below WLn. When staging from state E to state B, the amount of coupling to adjacent floating gates is reduced but still Significantly, the amount of coupling is further reduced when staging from state E to state A. Therefore, the amount of positives required to subsequently read each state of WLn-丨 will depend on the adjacent WLn. The state of the storage element changes. Figure 20 illustrates an example of a two-pass technique that stylizes a polymorphic storage element that stores negative materials for two different pages (lower page and upper page), depicting four states: state Ε (11), status Α (1〇), status Β (〇〇), and status c (01). For status Ε, both pages store “丨". For status Α, the next page stores "0&quot And the upper page stores "1". For state B, two τ faces are stored "0". For state c, the lower page stores "i" and the upper page stores 0 »Zhuang Yi' although a specific bit pattern has been assigned to each of these states' but also Assigning different bit styles. In the first stylized pass, the threshold voltage level of the storage element is set according to the bit to be programmed into the lower logical page. If the bit is logic 126206.doc • 38, 1357603 ·· 1" 'There is no change to the thunder, the m method, electricity [because this bit is in the proper state because it has been taken earlier. However, if a does not divide and the right #stylized position is logical, , 〇", then the storage component's threshold is a bit of apricot, and the drought increases and is in state A, as indicated by arrow 11〇〇. The first stylization is over.

In the first stylized pass, the threshold voltage level of the storage element is set according to the bit being programmed into the upper logical page. If the upper logical page bit will store the logic T, no stylization will occur, because depending on the stylization of the lower page bit, the storage element is in one of the states E or A, both of which carry the upper page bit. ''". If the upper page bit is logic T', the threshold voltage is shifted. If the first time the dummy element is maintained in the erased state E, then the storage element is programmed in the second stage, so that The limit voltage is increased in state 0, as depicted by the arrow 2〇2〇. If the storage element has been programmed to state A due to the first stylization pass, the storage element is further stylized in the second pass, The threshold voltage is increased to be in state B, as depicted by arrow 2010. The result of the second pass is to program the storage element to be designated to store the logic for the upper page without changing the lower page. The state of the data. In Figures 19 and 20, the amount of coupling to the floating gates on adjacent word lines depends on the final state. In a consistent example, the system can be set to perform full sequence writes (if enough writes) Fill in the information Page). If enough data is not written for the full page, the stylization process can be programmed to program the lower page with the received data. When the subsequent data is received, the system will then program the upper page. In an embodiment, the system can program the lower page mode to start writing, and if it subsequently receives enough data to fill the entire (or most) word line of the 126206.doc -39-1357603 storage element, it can be converted to full Sequence stylized mode. More details of this embodiment are disclosed in the article published on June 15, 2002. The article titled "pipelined Pr〇gramming Non-Volatile Memories Using EaHy U.S. Patent Application Publication No. 2006/0126390 to Data".

Figures 21a through 21c illustrate another process for staging non-volatile memory that reduces the effects of floating gate-to-floating gate coupling by: for any-specific storage elements, for the previous page After the data is written to the adjacent storage element, (4) is written to the specific storage element with respect to the specific page. In the example embodiment, the non-volatile storage element stores four bits of data for each storage element using four data states. For example, assume that state E is an erased state and state A ' MC is a stylized state. State E storage (4). Status renewal data 状态 status B storage data Π). State C stores the system. This is an example of non-Gray coding because the two bits change between adjacent states eight and five. Other codes that enable the data to be in the state of the entity data can also be used. Each storage element stores two pages of information. For the purposes of this reference, such data pages are referred to as upper and lower pages; however, they may be given other indicia. Regarding state A, the upper page stores bit 0 and the lower page stores bit 1. Regarding the __, the upper page stores the bit 1 and the lower page is stored by the ancient _j. Regarding state c, both pages store bit data 〇. This stylization process is a two-step process page. If the lower page will remain in the status E. If the data will be stylized to 〇. In the first step, the stylized lower material 1 'the storage element state is maintained at 'the storage element voltage threshold 126206.doc •40·1357603 high' causes the storage element to be programmed to state B, figure... Shows that the storage condition is stylized from state E to state B. State B is the temporary state B. Therefore, the verification point is depicted as Vvb, which is lower than Vvb. In one embodiment, 'in the storage element self-state' is stylized to state Β. The adjacent storage element (WLn+1) in the "reverse" string will then be programmed with respect to the "lower page. For example, return Referring to Figure 2, after the page below the stylized storage element 1〇6, the lower part of the page will be stylized. After the stylized storage element 1〇4, if the element 〇4 is stored and the self-state E rises To state B, the threshold voltage, the coupling effect of the floating-to-floating gate will increase the apparent threshold voltage of the storage element 1〇6. This will have the threshold voltage distribution for state B, The width is the effect of the distribution depicted by the threshold voltage distribution 215〇 of Figure 10. The apparent widening of the threshold I distribution will be corrected when the upper page is programmed. Figure...The process of riding the upper page. When the storage element is in the erased state E and the upper page will remain at i, the storage element will remain in state E. If the storage element is in state E and its upper page data will be programmed, then the threshold voltage of the storage element will rise. 'Make the storage component in State A. If the storage element is in the middle threshold voltage distribution 2丨5〇 and the upper page data remains at i, the storage element will be programmed to the final state b. The second storage element is in the middle threshold voltage distribution 215〇 and upper The page data will become data 〇 'The threshold voltage of the storage component will rise, causing the stagnation component to be in state C. The process depicted by Figures (1) through (1) reduces the effect of the floating gate to floating gate coupling because only Program stylization on top of adjacent storage elements will have an effect on the apparent threshold voltage of a given storage element. Alternative 126206.doc •41 · 1357603 An example of state coding is self-distribution when the upper page data is] State C' and move to state B when the upper page data is 。. Although Figures 21a through 21c provide examples of four data states and two profile pages, the concepts taught can be applied to have more or less Four states and other embodiments different from the two pages. Figure 21d depicts a rough/fine stylization process. As previously mentioned in conjunction with Figure ^, it can be initially stylized in a coarse mode. The component is stored to move it quickly to the target stylized condition and then programmed in a fine mode to move it to the target stylized condition more slowly with greater accuracy. The fine stylized mode may involve, for example, The reduced step size is used in the VPGM burst and/or the suppression voltage is applied to the selected "reverse" bit line. In addition, coarse_fine stylization can occur in one or more passes of stylization. In one pass coarse/fine stylization, as indicated in Figure 23, there is a switch from coarse stylization to fine stylization during the VpGM burst. In contrast, in multi-pass rough/fine stylization, for example, coarse stylization can be used during the first pass and fine stylization used during the second pass. Switching from coarse stylization to fine stylization as indicated in Figure 24 can occur, for example, between full VPGM bursts. Additionally or alternatively, the % heart burst may use a lower range of values in the second pass or other extra pass stylization. Multiple pass coarse/fine stylization can be considered as a multi-pass stylization of a particular type, which typically involves, for example, using more than one burst to program the storage element to the target stylized condition in more than one pass. . For example, the storage element can be self-erased (the state is simplistically programmed to the target stylized state A, B or C. In one method, the rough stylized 126206.doc -42 - stylizes the storage element to the temporary State A, B, or c, these states respectively have an associated verification level VvaL, VvbL or VvcL. Subscript, L" indicates that the 3rd rank is associated with a lower state than the target state Subsequently, the fine-grained stylization is used to program the storage elements from the temporary state to state A, b or C'. These states respectively have associated verification levels Vvail, VvbH or Vvch. The subscript "Η" indicates the verification level. Associated with a higher cancer that is the final target state. The threshold voltage of the programmed storage element is thus increased from the first level (eg, state Α) to the second level during the first stylization phase (eg , VvaL, VvbL or VvcL) and increase from the first level to the third level (eg, vvaH, VvbH or VvcH) during the second stylization phase. Figure 22 is a diagram for describing a method for staging non-volatile memory Flowchart of one embodiment. In an embodiment 'Erase the storage element (in blocks or other units) prior to stylization. In step 2200, the controller issues a data load " command and receives input by control circuitry 1510. In step 2205, the The address information of the page address is input from the controller or host to the decoder 1514. In step 2210, the stylized data for a page of the addressed page is input to the data buffer for stylization. Latched into the appropriate set of latches. In step 2215, the controller will issue the stylized " command to state machine 1512. Triggered by the "stylized" command, the use is applied to the appropriate selection The stepped stylized pulses 2305, 2310, 2315, 2320, 2325, 2330, 2335, 2340, 2345, 2350 of the pulse train 2300 of FIG. 23 of the zigzag line...

The data latched in step 2210 is programmed into the selected storage element controlled by state machine 1512. In step 2220, the programmed voltage VPGM 126206.doc • 43· 1357603 is initialized to a start pulse (e.g., 12 v or another value) and the program counter (pc) maintained by state machine 1512 is initialized to zero. In the steps Μ. The initial boost mode is applied, and in the step, the first pulse is applied to the selected word line to begin programming the storage elements associated with the selected word line. If the logic "0" is stored in a specific data latch indicating that the corresponding storage element should be programmed, the corresponding bit line is grounded. On the other hand, if the logic 1 _ is stored in the special latch indicating that the corresponding storage element should remain in its current data I state, then the corresponding bit line is connected to Vdd to suppress stylization. In field 2 step 2235, the status of the selected storage element is verified. If it is detected that the target threshold voltage of the selected storage component has reached the appropriate t level, the data stored in the corresponding data latch becomes logic", and if the threshold voltage is detected, the appropriate level has not been reached. , the material stored in the corresponding data latch does not change. In this way, it is not necessary to programmatically store the bit line of logic T in the corresponding data latch. When all data latches store logic M" The 'state machine (via the line or type mechanism described above) knows that all selected storage elements have been programmed. In step 224, a check is made as to whether all data latches store logic "Γ". If all data latches store logic 1, the stylization process is completed and successful because all selected storage elements are programmed and verified. The "pass" status is reported in step 2245. Right in step 224G, it is determined that not all of the data latches store logic "1", then the stylization process continues. In step 2250, the program counter PC is checked against the programmed limit PCmax. An example of one of the stylized limits is twenty; however, other numbers may be used. If the program counter PC is not less than PCmax', the process fails and the 126206.doc 1357603 ''fault" state is reported in step 2255. If the program counter PC is less than pCmax, then in step 226, VPGM is incremented by the step size and the program counter Pc is incremented. At step 2265, a determination is made as to whether the boost mode switching criteria (e.g., see Figure 4) is met. If this criterion is met, the boost mode is switched at step 2270 and the process returns to step 2230 to apply the next VPGM pulse. If the boost mode switching criterion is not met at step 2265, the process returns to step 223 to not apply a different VpGM pulse without changing the boost mode. Figure 23 depicts an example pulse train 2300 applied to the control gate of the non-volatile storage element during stylization, and boost mode switching that occurs during the burst. Burst 2300 includes a series of stylized pulses 2305, 2310, 2315, 2320, 2325, 2330, 2335, 2340, 2345, 2350, ... applied to the word line selected for stylization. In one embodiment, the stylized pulse has a voltage VPGM that begins at 12 v and increments (e.g., 〇 5 v) for each successive stylized pulse until a maximum of 2 〇 v is reached. There is a verify pulse between the stylized pulses. For example, the set of verification pulses 23 06 includes two verify pulses. In some embodiments, there may be an authentication pulse for each state to which the material is being programmed (e.g., states A, 8 and c). In other embodiments, there may be more or fewer verification pulses. For example, the verification pulse in each set may have an amplitude Vva,

Vvb and Vvc (Fig. 20), Vvb' (Fig. 21a)' or VvaL, VvbL and VvcL or VvaH, VvbH and VvcH (Fig. 21d) 描绘 The switching of the boost mode is depicted as occurring before the application of the stylized pulse 2335 The first boost mode is applied, and after the switch, the first boost mode is applied. As mentioned, when stylization occurs (for example, when 126206.doc •45-1357603

When a stylized pulse is applied, the voltage applied to the word line to apply the boost mode is applied. Practically, the boost voltage of the boost mode can be initiated slightly before each stylized pulse and removed after each stylized pulse. Therefore, during the verification process (example #, which occurs between the stylized pulses), no boost voltage is applied. Instead, a read voltage, typically less than the boost voltage, is applied to the unselected word line. The read voltage has an amplitude sufficient to maintain the previously stylized storage element in the "reverse" rate on when the threshold voltage of the currently staging storage element is being compared to the verify level. In a stylized phase, a subset of the bursts (e.g., pulse 2305, and therefore, in a method, 2310, 2315, 2320, 2325, and 2330 of the stylized pulses in 2300) are applied to one or more A storage element, and in a second stylization phase, a second subset of pulses in the burst (eg, pulses 2335, 2340, 2345, 235〇) is applied to the OR: etc. 7L pieces are stored. Each stylized pass can thus include multiple stylized segments. • Figure 24 depicts an example pulse train applied to the control gate of the non-volatile storage element during stylization and the switching of the boost mode that occurs between the bursts. In particular, switching the boost mode to green occurs between bursts 24_ •. Prior to the switching, during the first burst 2_, the second boost mode should be applied during the second burst 245 during the second burst 245. For example, the burst 24 可 may be applied during the first pass of the multi-pass stylization process, while the burst 245 施加 is applied during the second pass of the stylization process. Thus, in a method, 'in the first stylization phase, the first burst (eg, burst 126206.doc -46·1357603 2400) is applied to the selected word line - or a plurality of library elements, And in the second stylized order, a second burst (eg, burst 2450) is applied to the or the (four) memory component. Each stylized pass can therefore be consistent with the program.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments described are chosen to best explain the principles of the invention and the application of the embodiments of the invention in the various embodiments of the invention. The present invention is optimally used in the case. The scope of the invention is intended to be defined by the scope of the appended claims. [Simple description of the diagram] t Figure 1 is a top view of the "reverse" string. Figure 2 is an equivalent circuit diagram of the "reverse" string of Figure 1. Figure 3 is a block diagram of an "reverse" flash memory device array. Figure 4 depicts a conceptual diagram showing the boost mode decision process. Figure 5 depicts a process for switching the boost mode during stylization. Figure 6 depicts a self boosting mode implemented via a plurality of word lines. Figure 7 depicts a local self-boost mode implemented via a plurality of word lines. Figure 8 depicts an erase region self-boost mode implemented via a plurality of word lines. Figure 9 depicts a first modified erase region boost mode implemented via a plurality of word lines. Figure 1 〇 depicts a second modified erase region implemented via a plurality of word lines 126206.doc • 47-1357603 Boost mode. Figure la depicts a third modified erase region self-boost mode implemented via a plurality of word lines. Figure lib depicts a fourth modified erase region self-boost mode implemented via a plurality of word lines. Figure 11c depicts a fifth modified erase region self-boost mode implemented via a plurality of word lines. Figure 12 depicts a timeline showing how rough and fine stylization can be achieved by setting the bit line suppression voltage. Figure 13 depicts a cross-sectional view of an unselected "reverse" string showing stylized and erased regions. Figure 14 is a block diagram of an "reverse" flash memory device array. Figure 15 is a block diagram of a non-volatile memory system using a single column/row decoder and a read/write circuit. Figure 16 is a block diagram of a non-volatile memory system using a dual column/row decoder and a read/write circuit. 17 is a block diagram depicting one embodiment of a sensing block. Figure 18 illustrates an example of organizing memory arrays into blocks for a full bit line memory frame or for an even and odd memory frame. Figure 19 shows an example collection of the threshold voltage distribution. Figure 20 depicts an example set of threshold voltage distributions. Figures 21a through 21c show various threshold voltage divisions and describe the process for staging non-volatile memory. Figure 21d depicts a rough/fine stylization process. 126206.doc _48, 1357603 FIG. 22 is a flow chart depicting one embodiment of a process for programming non-volatile memory. Figure 23 depicts an example pulse train applied to the control gate of the non-volatile storage element during stylization, and boost mode switching that occurs during the burst.

Figure 24 depicts an example pulse train applied to the control gate of the non-volatile storage element during stylization, and boost mode switching occurring between the bursts. [Main component symbol description] 100 transistor 100CG control gate 100FG floating gate 102 transistor 102CG control gate 102FG floating gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 106CG control gate 106FG floating gate 120 first selection gate 120CG control gate 122 second selection gate 122CG control gate 126 bit line 126206.doc -49- 1357603

128 source line 320 "reverse" 321 bit line 322 select gate 323 storage element 324 storage element 325 storage element 326 storage element 327 select gate 340 "reverse" 341 bit line 342 select gate 343 storage element 344 Storage Element 345 Storage Element 346 Storage Element 347 Select Gate 360 "Reverse" 361 Bit Line 362 Select Gate 363 Storage Element 364 Storage Element 365 Storage Element 366 Storage Element 126206.doc -50- 1357603

367 Select Gate 400 Block 405 Block 410 Block 415 Block 420 Block 425 Block 430 Block 435 Block 440 Block 445 Block 460 Block 1200 Curve 1250 Curve 1300 "Reverse" String 1304 Source Supply line 1306 select gate 1308 storage element 1310 storage element 1312 storage element 1314 storage element 13 16 storage element 1320 storage element 1322 storage element 126206.doc • 51 · 1357603 1324 bungee side selection gate; 1326 bit line 1350 area 1360 area 1390 Substrate 1400 "Reverse" Storage: 1404 Source Line 1406 Bit Line 1426 汲 Terminal 1428 Source Terminal 1450 "Reverse" String 1500 Sensing Block 1510 Control Circuit 1512 State Machine 1514 Crystal Address Address Decoding 5 1516 Power Control Module 1518 Line 1520 Data Bus 1530A Column Decoder 1530B Column Decoder 1560 Line Decoder 1560A Line Decoder 1560B Line Decoder 1565 Word Buy/Write Circuit 126206.doc -52- 1357603

1565A Read/Write Circuit 1565B Read/Write Circuit 1570 Sensing Circuit 1572 Busbar 1580 Sensing Module 1582 Bit Line Latch 1592 Processor 1593 Input Line 1594 Data Latch 1596 Memory Device 1598 Memory Body Grain 1800 Parity Structure 1810 Full Bit Line Architecture 2010 Arrow 2020 Arrow 2150 Threshold Voltage Distribution 2300 Example Burst 2305 Stylized Pulse 2310 Stylized Pulse 2315 Stylized Pulse 2320 Stylized Pulse 2325 Stylized Pulse 2340 Stylized Pulse 2345 Stylized pulse 126206.doc -53- 1357603 2350 2400 2450 AA' BB, BLe

CC' E SGD SGS Vbl Vdd VH V iso VL VPARTIAL inhibit V PASS v PASS-LOW V PGM VpoM-HIGH 126206.doc Stylized pulse burst burst stylized state temporary state stylized state temporary state even bit line odd bit Meta-threaded state Temporary state Erase state Bole side Select gate control line Source side Select gate control line Bit line Voltage potential higher Verify level isolation voltage Lower verify level bit line suppress voltage turn-on voltage Relatively low turn-on voltage stylized voltage higher range -54 - 1357603

VpGM-LOW Lower range VsGD Voltage VsGS Voltage VsOURCE Potential V th Threshold voltage Vra, Vrb, Vrc Read reference voltage Vva, Vvb, Vvc, Vvb' Amplitude WL1 to WL7 Word line

126206.doc -55-

Claims (1)

Patent Application No. 096,141,503, the disclosure of which is incorporated herein by reference in its entirety in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire At least one storage element of the non-volatile storage element set, the non-volatile storage element set is provided in a plurality of "reverse" strings and is configured by a plurality of sub-line communication, and the at least one storage element and one of the plurality of word lines are selected Word line communication, the stylization comprising applying a first series of stylized pulses to the selected word line, and then applying a second series of stylized pulses to the selected word line; first series of stylized During each of the stylized pulses of the pulse, the root 2 - first boost mode applies a first set of voltages to the unselected word lines of the plurality of word lines; after the first consecutive programmed pulse, Switching from the first boost mode to a second boost mode based on a boost mode switching criterion; and during each of the stylized pulses of the second series of programmed pulses, The second voltage boosting silk formula < applied to a second set of such non-selected line to the first voltage set at least partially different from the second set voltage. 2. The method of claim 1, wherein: the stylizing comprises applying a burst to the selected word line, the burst comprising the first and second series of stylized pulses, the switching being applied One of the pulse trains occurs after the first pulse and before one of the last pulses in the pulse train is applied. 3. The method of claim 1, wherein: the stylizing comprises applying a burst to the selected word line, the pulse 126206-1000812.doc comprising the first and the second series of stylized pulses, The dusting mode switching criterion is based on the time at which a programmed pulse having one of the specified amplitudes is applied to the selected word line. 4. The method of claim 1, wherein: the stylizing comprises applying a burst to the selected word line, the pulse string comprising a first and a second series of stylized pulses, the boosting The mode switching criteria is based on the time at which the specified number of stylized pulses have been applied to the selected word line. 5. The method of claim 1, wherein: the boost mode switching criterion is based on a position of the selected word line at one of the plurality of word lines. 6. The method of claim 1, wherein: the threshold voltage of the at least one storage element increases from a first level to a second level before the switching and increases from the second level after the switching To the third level. 7. The method of claim 1, wherein: the stylization involves coarse stylization prior to the switching and fine stylization after the switching. The method of claim 1, wherein: the boost mode switching criterion is based on at least one of the non-volatile storage element sets - the time at which the other storage elements reach a specified stylization condition. 9. The method of claim 1, wherein: The boost mode switching criterion is based on a number of stylized cycles experienced by the set of non-volatile storage elements. The method of claim 1, wherein: the at least one storage component is provided in a selected "reverse" string of the plurality of "reverse" strings, In a boost mode, prior to the switching, a particular unselected word line receives a voltage that does not cause a channel region on one of the particular unselected word lines to be unselected at that particular The other of the word lines is isolated from one of the channel regions; and in the first _ 虔 mode, after the switching, the particular unselected word line receives a voltage that causes the particular unselected word The channel region on one side of the line is isolated from the channel region on the other side of the particular unselected word line. 11. The method of claim 1, wherein: the at least one storage component is provided in the plurality of "reverse" strings - the selected "reverse" string; the first set of voltage boost channel regions and the A plurality of "reverse" strings are associated with an unselected "reverse" string; when the field is boosted by the first set of voltages, each stylized pulse of the first series of stylized pulses is applied; The second set of voltage boost channel regions is associated with an unselected "reverse" string of the plurality of "reverse" strings; and when the field is boosted by the second set of voltages, Each of the stylized pulses of the second series of stylized pulses. 12_ - a non-volatile storage system comprising: a set of non-volatile storage elements provided in a plurality of "reverse" strings 126206-1000812.doc a plurality of word lines 'communicating with a collection of non-volatile storage elements' Communicating with a selected one of the plurality of word lines; and communicating with the non-volatile storage element set of one or more control circuits, the one or more control circuits stylizing the at least one storage element, the stylized The method includes applying a first series of stylized pulses to the selected word line, and then applying a second series of stylized pulses to the selected word line during each stylized pulse of the first series of programmed pulses And the one or more control circuits apply a set of voltages to the unselected word lines of the plurality of word lines according to a first boost mode, and after the first series of stylized pulses, the one or more control circuits - or a plurality of control circuits switching from the first boost mode to a second boost mode based on the -boost mode switching criterion, and during each of the stylized pulses of the second series of programmed pulses, The second set of pressure applied to one of these unselected word lines, the set pressure of the first electrically least partially different from the second set voltage. 13. For the non-volatile storage system of claim 12, its ten: a control circuit for programming the at least one storage element by applying a burst to the selected word line, the pulse train including the first and the second series of stylized pulses, the switching is applying One of the first pulses of the pulse train occurs and before one of the last pulses of the pulse season is applied. 14. The non-volatile storage system of claim 12, wherein: one or more control circuits program the at least one storage element by applying a pulse train to the selected word line, the pulse train including the first 126206-1000812.doc -4 - 1357603 and the first series of stylized pulses, the boost mode switching criterion is based on applying a stylized pulse having a specified amplitude to the selected word line Moment. 15. The non-volatile storage system of claim 12, wherein: ??? or a control circuit to program the at least one storage element by applying a burst to the selected word line, the pulse train comprising the first and. Haidi - a series of stylized pulses based on the boost mode switching criteria A time has been applied to the selected word line by a specified number of stylized pulses in the burst. 16_ The non-volatile storage system of claim 12, wherein: the boost mode is based on one of the plurality of word lines of the word count. 17. The non-volatile storage system of claim 12, wherein: the threshold voltage of the at least one storage component increases from a first level to a second level prior to the switching and from the second after the switching The level is increased to a third level. 18 'A non-volatile storage system as claimed in claim 12, wherein: the simplification involves a rough stylization prior to the switch and a fine stylization after the switch. 19. The non-volatile storage system of claim 12, wherein the boost mode switching criterion is based on at least the other of the non-volatile storage element sets - the time at which the stylized condition is specified. 20. The non-volatile storage system of claim 12, wherein the delta dust mode switching criterion is based on a number of stylized cycles experienced by the non-volatile storage element set 126206 · 0008 0008 丨 2.d〇c. 21. The non-volatile storage system of claim 12, wherein: the at least-storage component is provided in the plurality of "reverse" and selected "reverse" strings; in the Haishengsheng mode, before the switching, - a particular unselected word line receiving H that does not isolate one of the channel regions on one side of the particular unselected word line from one of the channel regions on the other side of the particular undefined word line; And 2 in the second boost mode, after the switching, the (4) unselected pre-wire receives a voltage, the voltage causing the channel region on the side of the unselected word line The channel region on the other L side of the particular unexamined word line is isolated. 22. The non-volatile storage system of claim 12, wherein: the at least one storage component is provided in the "reverse" string of the plurality of "reverse" strings, and the selection and determination of the "reverse" string; The first set is associated with an unselected "reverse" string of the plurality of "reverse" strings; when the channel region is boosted due to the first set of voltages, the first series of stylized pulses are applied Each of the stylized pulses; the second set of voltage boost channel regions being associated with an unselected "reverse" string of the plurality of "reverse" strings; and when the channel is due to the second set of voltages When the zone is boosted, each stylized pulse of the second consecutive _stylized pulse is applied. 126206-1000812.doc • 6 ·