TW200836203A - Reducing program disturb in non-volatile memory using multiple boosting modes and non-volatile storage system thereof - Google Patents

Abstract

A method for operating a non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

Description

200836203 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory. [Prior Art] Semiconductor memory has become increasingly popular in various electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Electrically erasable and programmable read-only memory (EEPr〇m) and flash memory are among the most popular non-volatile semiconductor memories. Compared with the traditional full-featured EEPROM, in the case of flash memory (also a type of EEPROM), the content of the entire memory array or the contents of one part of the body can be erased in a single step. Conventional EEPROMs and flash memories use floating gates that are above and insulated from the via regions in the semiconductor substrate. The floating gate is located between the source and drain regions. The control gate is provided above and insulated from the floating gate. The threshold voltage (Vth) of the thus formed transistor is controlled by the amount of electricity remaining on the floating gate. Also, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to conduct the conduction between the source and the drain of the quasi-pen θ body is controlled by the charge content on the floating gate. A second EEPROM and flash memory device has a floating (four)' for storing two ranges of charge's and thus the memory element can be programmed between two states (eg, t-deletion and stylized state). Erase. Because the mother 3 recalls 7L pieces can store one bit of data, such a flash U body is sometimes referred to as a binary flash memory device. 126206.doc 200836203 A multi-sorrow (also known as multi-order) flash memory device is implemented by identifying a plurality of distinct allowable/effectively programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to an expected value of a set of data bits encoded in the memory device. For example, when each memory component can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the component can store two bits of data.

Typically, the stylized voltage VPGM applied to the control gate during the stylization operation is applied as a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulse is increased by a predetermined step size with each successive pulse, for example, 〇·2 to 〇·4 V. The VPGM can be applied to the control gate of the flash element. The verification operation is performed during the period between the stylized pulses. That is, the programmed level of each of the group elements that are being parallelized in parallel is read between successive stylized pulses to determine whether it is equal to or greater than the verify level to which the component is being programmed. For multi-state flashing. In the case of a hidden 7L array, a verification step can be performed on each state of the component to determine if the component has reached its verification level associated with the data. For example, a polymorphic memory component capable of storing data in four states may need to perform a verify operation on three comparison points. In addition, 'when stylized EEPR0M5il flash memory device (such as "oppositely" reverse flash memory device), 'vpgm is usually applied to the 'gate' and the bit line is grounded, thus making the memory element ( For example, the eclipse left-slave, ^ ((4)% of the storage of the channel of the electronic injection to the floating closed-pole two, although the electrons accumulate in the floating gate, the floating (four) pole becomes negatively charged and the Lu-body component of the thunder Section i > , power-limited housing upgrades make the memory component considered to be in a stylized state at 126206.doc 200836203. Available under the heading "s〇urce Side Self B(10)α叩Technique For Non-Volatile Mem〇ry" Further information on this stylization can be found in U.S. Patent No. 6,859,397 and issued on Feb. 3, 2005, entitled Detecting 〇ver Programmed Memory, U.S. Patent Application Publication No. 2005/0024939; The literature is hereby incorporated by reference in its entirety. However, due to the proximity of non-volatile storage elements to each other, various forms of programmatic interference have been experienced during stylization. Moreover, this problem is expected to Further expansion of the technology deteriorates. Programmatic interference occurs when the threshold voltage of an unselected non-volatile storage element is shifted due to the stylization of other non-volatile storage elements. Various program interferences may limit the non-volatile storage device ( An operational window such as "reverse" flash memory. Boost technology - boosts the channel region of the "reverse" string that is suppressed by stylization to a high potential and contains the storage elements to be programmed The channel area of the "reverse" string is connected to a low potential (such as Gv) to solve this problem. However, the 疋 boost mode does not optimally solve multiple failure mechanisms. [Invention] The present invention provides The above and other problems are solved by operating a non-volatile storage system that reduces program interference. In the example of the invention, a method for operating a non-volatile storage device includes storing one of a set of non-volatile storage elements. An element, wherein the set of non-volatile storage elements is in communication with a plurality of word lines, and the storage element communicates with a selected word line. The method further includes during stylization The first set of electricity is applied to the unselected word line and based on the riser switch bar 126206.doc 200836203 from applying the first set of voltages to the untwisted word line switching to applying the second set of voltages to a selected word line. The first set of voltages is at least partially different from the second set of electricity. For example, the stylization can include: applying a pulse train to the selected word line 'where the pulse train has The boost mode switching criterion is triggered when a programmed pulse of a specified amplitude is applied to the selected word line' or when a specified number of stylized pulses in the burst have been applied to the selected word line. x In another embodiment, a method for operating a non-volatile memory includes performing a first boost mode during a stylized first stylization phase of a storage component in a set of non-volatile storage components, and The second boost mode is implemented during the second stylized phase of continuing the stylization of the storage element. The threshold voltage of the storage element increases from a first level to a second level during the first stylization phase and from a second level to a third level during the second stylization phase. In addition, the 'first stylization stage may include the first pass in the multi-pass stylization technique' and the second stylization stage may include the second pass of the multi-pass stylization technique. / In the 7 method, in the first stylization phase, the subset of the pulses in a burst is added to the storage element, and in the second stylization phase, the pulse in the burst is Two subsets are applied to the storage element. In another method, in a first stylization phase, a first pulse train is applied to the storage element and a second pulse train is applied to the storage element in a second stylization phase. In another embodiment, a method for operating a non-volatile reservoir includes staging a storage element in a collection of non-volatile storage elements, wherein 126206.doc 200836203 the non-volatile storage element set and the Xu-burst application Up to the communication with the store. The stylization includes the step-by-step method of including the pulse train in two steps: the selected word line. When the square is applied to the selected word line, the (four) mode is applied to the first subset of the unconformed pulses, and when the = storage element in the burst is implemented - added to the selected word line, ^ The second subset of pulses is applied to the unselected: the volatile storage element implements the first pressure mode. Non-volatile storage element implements second liter

: a collection of non-volatile storage elements can be provided in a number of "reverse" strings, the selected "reverse" string of the storage element, and the "reverse string" in which the first and second boost modes are unselected. In addition, in one method, the implementation of the first-boost mode & boosts the channel without reversing the channel on the source side of the "anti-eight" application. Part of the channel on the drain side of the _ is isolated, and the implementation/first boost mode includes the knives of the channel on the source side of the "reverse" string, on the opposite side of the string Part of the channel is isolated. [Embodiment] The present invention provides a non-volatile storage system and method for reducing program interference. One example of a memory system suitable for use in practicing the present invention uses a "reverse flash memory structure that includes a plurality of transistors arranged in series between two select gates. The series transistors and the select gates It is called the "reverse" string. Figure 丨 is a top view showing the r and the string. Figure $ is its equivalent circuit. The "reverse" string depicted in Figures 1 and 2 includes four transistors 126206.doc -11 - 200836203 100, 102 connected in series and sandwiched between a first selection gate 120 and a second selection gate 122. , 104 and 106. Select the connection of the gate 12 〇 gate "reverse" string to the 兀 line 126. The connection of the gate 122 gate control "reverse" string to the source line 128 is selected. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 12 CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122cg. Each of the transistors 1〇〇, 102, 1〇4, and 1〇6 has a control gate and a floating gate. The transistor 1 has a control gate 100CG and a floating gate 100FG. The transistor 1〇2 includes a control gate 102C and a floating gate 丨02FG. The transistor 丨〇4 includes a control gate 丨〇4Cg and a floating gate 104FG. The transistor 〇6 includes a control gate 1〇6CG and a floating gate 106FG. The control gate 100CG is connected to (or is) a word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 1〇4CG is connected to the word line WL1, and the control gate 1〇6CG is connected to the word line WL〇. In one embodiment, 'transistors 100, 102, 1〇4, and 1〇6 are each storage element, also referred to as a memory unit. In other embodiments, the storage element can comprise a plurality of transistors or can be different from the memory elements depicted in Figure 2 and Figure 2. The selection gate 120 is connected to the selection line SGD. Select gate 122 is connected to select line SGS 〇 Figure 3 is a circuit diagram depicting three r and "strings". A typical architecture using a "reverse" ~ structured flash memory system will include a number of "reverse" strings. The cows "show" three "reverse" strings 320, 34 and 360 in an array of memory with more "reverse" strings. Each of the "reverse" strings selects a gate and four storage elements. Although four storage elements are illustrated for simplicity, modern "reverse" _ can have up to, for example, twenty-two or sixty-four storage elements. 126206.doc •12- 200836203 For example, the "reverse" string 320 includes selection gates 322 and 327 and storage elements 3 23 to 326. The "reverse" string 340 includes selection gates 342 and 347 and storage elements 3 43 To 3 46, the "reverse" string 360 includes select gates 362 and 367 and storage elements 363 through 366. Each "reverse" string is connected to the source line by its selection gate (e.g., selection gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. The respective "reverse" strings 320, 340 and 360 are connected to the respective bit lines 321, 341 and 361 by selecting a selection transistor among the gates 322, 342, 362 and the like. These selective transistors are controlled by the drain select line SGD. In other embodiments, the selection lines are not necessarily common in the "reverse" string. That is, different selection lines can be provided for different "reverse" strings. Word line WL3 is coupled to the control gates of storage elements 323, 343, and 363. Word line WL2 is coupled to the storage element to the bucket and the control gate of %*. Word line WL1 is connected to the storage element milk, % and the control gate of the milk. The pre-wire WLG is connected to the storage gates of storage elements 326, (10) and 鸠. As can be seen, 'every bit line and each "reverse" string contains

C Array of components or 隼人夕 ^ ^ ^ 果 口 仃. The word lines (WL3, WL2, WL1, and chassis) contain the array or set of columns. Each word line connects the control gate of each of the rows. Or the 'control' (four) pole can be provided by the word line itself. Line WL2 provides control over storage elements 324, 344 and corrections, and there may be thousands of storage elements on a word line. For example, when the storage element can store data, the storage of one bit is divided into two ranges, and the range of the voltage of the second limit voltage (VTH) is assigned to the logical data "1" and "〇". ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

Then $ negative, and is defined as logical "丨". Vth is positive after the stylization operation and is defined as logic "G''. When vTH is negative and an attempt is made to read, the store will be turned "on" to indicate that the logic is being stored,". When % is positive and an attempt is made to make a drink, the storage element will not be turned on. This indication stores the logic, 0,,. Storage: Components can also store information from multiple levels, for example, the number of multiple bits: bedding. In this case, the range of the Vth value is divided into the number of data P outside the white layer. For example, if you store four levels of information, there will be four VtH ranges assigned to the data values "11", "10", "01", and "〇〇". In one example of the inverse memory type, Vth is negative after the erase operation and is defined as "11''. The positive Vth value is used for the state "10", ,, 〇1,, and "〇〇" The relationship between the data stored in the storage element and the threshold voltage range of the component depends on the data encoding mechanism used for the storage component. For example, the full text is incorporated herein by reference. U.S. Patent No. 6,222, the issue of the U.S. Patent and the U.S. Patent No. 55-No. describes the various data encoding mechanisms for multi-state flash memory components. ~, and the related types of flash memory and its operation Examples are provided in U.S. Patent Nos. 5,386,422, 5,522, 5, 57, 315, 5,774, 397, 帛 6, 〇 46, 935, Μ%, and No. 6,522, 580, each of which This is incorporated herein by reference. When the flash storage component is programmed, a programmed voltage is applied to the control Φ] gate of the storage element and will be coupled to the storage element (4). Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the oceanic gate becomes negatively charged and the Vth of the storage element rises. To apply a stylized voltage to the control gate 126206.doc •14- 200836203 pole of the memory element being programmed, this stylized voltage is applied to the appropriate word line. As described above, one of the storage elements in each of the "reverse" strings shares the same word line. For example, when the storage element 324 of Figure 3 is programmed, the programmed voltage will also be applied to the control gates of storage elements 344 and 364.

However, during the stylization of other "reverse" strings, program disturb may occur at the suppressed "reverse" string, and sometimes program disturb occurs at the stylized "reverse" string itself. For example, if the "reverse" string 320 is suppressed (eg, it is an unselected "reverse" string that does not contain the currently-synchronized storage element) and the "reverse" string 34 is being stylized ( For example, if it is a selected "reverse" string containing the currently stylized storage element, program disturb may occur at the "reverse" string 320. For example, if the turn-on voltage Vpass is low, the suppressed r is not boosted by the "string" channel, and the selected word line of the unselected "reverse" string can be unintentionally programmed. In another possible case, the boosted voltage can be reduced by gate-induced drain leakage (GIDL) or other leakage mechanisms, which in turn causes the same problem. Other effects, such as shifting of charge stored in stylized storage elements due to electrical valley coupling between storage elements, can also be problematic. Figure 4 depicts a conceptual diagram showing the boost mode decision process. As mentioned at the outset, the program disturb is still a significant problem for non-volatile storage systems. Program disturb occurs when the threshold voltage of an unselected non-volatile storage element is shifted due to the stylization of other non-volatile storage elements. Program disturb can occur on previously stylized storage objects and erased storage elements that have not yet been programmed. Various program disturb mechanisms can limit the available operational windows of non-volatile storage devices (such as 126206.doc -15-200836203 ... and syllabary). For example, t, the dust-cleaning technique, the pattern is boosted to a high potential by the channel region of the suppressed "reverse" string and the channel region containing the "reverse" string of the storage element to be programmed is connected to the low Potential (such as 〇v) to solve this problem. However, given the dust-up type, it is not possible to solve many failure mechanisms most. That is, given the boost mode ΰ is also effective to solve the special & type of interference failure mechanism but may be inefficient in solving other failure mechanisms. Typically, the boost mode is traded off or optimized to give the best operating window. Here, it is recommended to use different boost modes during stylization to better optimize boost. For example, in one method, a boost mode is used during initial stylization and the second boost mode is used to improve the total margin relative to program disturb when the spear renders a single page or the word line is nearing the end ( Margin). Various criteria can be used to determine which boost mode to use and when to switch from one boost mode to another. As an example, the three different boost modes indicated at blocks 4A, 405, and 410 can be selected by the boost mode decision process (block 41 5). The boost mode includes, for example, self-boost (SB), local self-boost (LSB), erased area self-boost (EASB), and modified erase area self-boost (REASB), discussed further below. Once a decision is made, the selected boost mode (block 420) is applied, for example, by applying a set of voltages corresponding to the selected boost mode to the unselected word lines. For example, the boost mode switching decision process (block 41 5) may use one or more boost mode switching criteria (block 425). Such criteria may include the number of programmed pulses (block 430), the programmed pulse amplitude (block 43 5), the programmed pass number (block 440), the location of the selected word line (block 445), rough /Fine stylized 126206.doc -16- 200836203 杈 state (block 450), storage element 45" 'and stylized programmatic conditions experienced by memory device (block 460). Block, style pass number can be & (for example) multi-pass type

V

The second or the second time is in progress. The criteria for the storage element 2 may be (for example, 疋m) reach the first storage element or the storage element in the beta-group storage element (such as an F-block or array)= : Factory money type switching. Regarding the program experienced by the memory device: the number of criteria can be implemented, for example, by tracking the basis of the stylization to adjust the switching point. To cite the example of the beta, if the switching point is in the burst period, then the switching point can appear relatively early in the burst after the memory device has experienced a relatively large number of cycles, because the storage Meta... The extra stylized loop tends to be faster programmed. The mode of the sorcer mode switching is described in more detail below. Sub Figure 5 illustrates the process of switching the boost mode during stylization. The conceptual diagram presented above can be further understood based on the flow chart. At step (4), the stylization begins, and at step 51, the first boost mode is applied: at decision 520, 'If the switching criteria are met, then switch to the second; the house mode (step 530) and the stylization continues ( Step 54 〇) until it is completed (step 550). If the switching criteria are not met at decision step 52, the first boost mode continues to be applied and the stylization continues (step 525). Typically, the boost mode is implemented by one or more control circuits of the memory device to apply an appropriate voltage to the word line in communication with the set of storage elements. 126206.doc -17- 200836203 The decision to switch the boost mode can be based on many factors. In general, it is necessary to implement a boost mode that is optimal for the current stylization mechanism and the current conditions of the storage component and the "reverse" string. For example, the non-EASB# voltage mode (such as SB*LSB) can be relatively effective for initial stylized pulses (when VPGM is low) 'WASB boost mode (including REASB) for higher stylized pulses (in When VPGM is high, it can be relatively effective. In this case, switching from the non-EASB mode to the EASB mode can be made based on the amplitude of the VPGM. In addition to f, in addition to the programmed pulse amplitude, the fault mode responds to many stylized pulses. In this case, switching from the non-EASB mode sEAsb mode can be made based on the number of stylized pulses, which are typically associated with vPGM. Furthermore, an I boost mode may be more than (4) based on the position of the selected word line in other word lines. Generally, depending on the characteristics of a given non-volatile storage device, a plurality of boost modes that produce an acceptable lower failure rate can be used to define the operating window. Figure 6 depicts a self boosting mode implemented via a plurality of word lines. As mentioned in 1 &, various types of boost modes have been developed to combat program disturb. During the stylization of the storage element on the selected word line, the boost nucleus is implemented by applying (4) a set of unselected word lines that communicate with the currently unprogrammed storage element. JL is associated with the selected "reverse" string, and other storage elements are associated with the unselected "reverse" string. Programmable interference typically involves storage elements in unselected "reverse" strings, which may occur due to other storage elements in the same "reverse" string. In one method, the self-elevation mode is depicted by an example word line that communicates with the set of storage elements in the "reverse" string of configuration 9. In this example, there are eight word lines labeled WL0 through WL7 (eg, control lines), the source side select gate control lines labeled SGS, and the drain side select gates labeled SGD. Control line. The set of voltages applied to the control lines are also depicted. As an illustration, specify WL4 as the selected word line. From the source side to the drain side of the "reverse" string, stylization usually advances one word line at a time. The applied voltage includes ··vSGS applied to the source side selection gate control line SGS; the on voltage VPASS applied to each of the unselected word lines WL〇 to WL3 and wl5 to My, stylized Voltage VpGM, which is applied to the selected word line WL4; and VSGD, which is applied via the drain side select gate control line s(}d. Typically, vSGSg 〇v causes the source side select gate to be turned off. V, such that it is attributed to the corresponding low bit line voltage, such as 〇 to 1 V), for the r's r and the string, the drain side selects the gate to be turned on. Due to the application of a correspondingly higher Vbl (such as 15 to 3 v), for the "reverse" string of unselected turns, the drain side select gate is turned off. Additionally, VPASS can be about 7 to 1 〇 v, and VpGM can vary between about 12 and 2 〇 v. In a stylized mechanism, a burst of stylized voltage is applied to the selected word line. See also Figure 23 and Figure 24. The amplitude of each successive stylized pulse in the burst is increased in a stepwise manner, typically increasing from about 0. 3 to 0. 5 V per pulse. Additionally, a verify pulse is applied between the stylized pulses to verify that the selected storage element is The target stylization condition has been reached. Note that each individual stylized pulse can also have a fixed amplitude or can have a varying amplitude. For example, some stylized mechanisms apply pulses whose amplitude changes in a ramp or step manner. Any type of stylized pulse can be used. In the case where WL4 is a stylized word line and is programmed to advance from the source 126206.doc -19- 200836203 side of each "reverse" string to the drain side, when the component is being programmed on the WL4, The storage elements associated with WL0 through WL3 are programmed and the storage elements associated with WL5 through WL7 will be erased. The conduction of the unselected word line is coupled to the channel associated with the unselected "reverse" string such that there is a voltage in the channel that tends to reduce the wear of the storage element by the emulsion Voltage to reduce program interference. 7 depicts a partial auto boost (ls... mode implemented via a plurality of word lines. In one method, the local auto boost mode is depicted by an example word line in communication with a set of storage elements disposed in a "reverse" string. 7. The local self-boost differs from the self-boost mode of Figure 6 in that the word line adjacent to the selected word line receives the isolated voltage VlS0 of 〇v or another voltage close to 〇v. Non-VPASS. The remaining unselected word lines are at VpAss. Local auto-boost attempts to reduce program disturb by isolating the channels of the previously stored storage elements from the channels of the storage elements being suppressed. Although the LSB mode is The lower value of Vpgm is effective, but the disadvantage of LSB mode is that when VpGM is at the same time, the voltage of the channel under the selected word line can be very high, because the part of the channel is not The other channel areas below the selected word line are isolated. Therefore, the boost voltage is mainly judged by the higher stylized voltage % (four). Due to the higher boost, near the word line biased to 〇V, f can occur. Leakage caused by tunneling or gate Electrical (GIDL). The channel boost can be limited to a lower value by using the erase region self-boost (EASB) or modified easb (REASB) modes described below. Figure 8 depicts implementation via a plurality of word lines The erase region self-boost mode. In one method, the EASB mode is depicted by an example word line that communicates with the set of 126206.doc -20-200836203 storage elements disposed in the "reverse" string. The eASB is similar to the LSB. 'The difference is that only the source side adjacent word line WL3 is at the isolation voltage 'VISO=〇V' to isolate the boosted channel on the source and drain sides of the unselected "reverse" string. The channel region below the word line is connected to the channel region at the drain side of the selected storage element such that the channel boost is primarily determined by the VpASs applied to the unselected word lines instead of (10). See also Figure 13. Bungee The side adjacent word line WL5 is at VpASs. If VpASS is too low, then boosting in the channel will not be sufficient to prevent program interference. However, if VPASS is too high, the unselected words in the selected "reverse" string can be programmed. Line (where the bit line is at 〇V), or The program is attributed to KGIDL. Figure 9 depicts a first modified erase region self-boost mode implemented via a plurality of word lines. In one method, the first REASB mode is configured and placed in the "reverse" string. The example word line of the storage element set communication depicts 9 〇〇 REASB is similar to EASB but applies a smaller isolation voltage VlS0 (such as 25 v) to an adjacent isolated word line (eg, WL3). Figure 10 depicts a plurality of words The second modified erase region self-boost mode implemented in the line. In one method, the second REASB mode is depicted by an example word line in communication with the set of storage elements disposed in the "reverse" string. In this case, vIS0 is applied to a plurality of word lines, such as WL2 and WL3, on the source side of the selected word line WL4. You can use the same Vls〇 or different Vis〇 values. For example, vIS0 can be reduced in a progressive manner, for example, from 4 V on wl3 to 2.5 V on WL2. Various other methods are also available. For example, vIS0 can be applied to three adjacent word lines (eg, wli to 126206.doc -21 - 200836203 WL3), in which case the last word line (WL1) receives the lowest Vis 〇, and WL2 and WL3 receive the common VIS〇. Figure la depicts a third modified erase region self-boost mode implemented via a plurality of word lines. In one method, the third REASB mode is depicted by an example word line that is in communication with the set of storage elements disposed in the "reverse" string. In this case, when vPGM has a relatively low value (represented by Vpgm l〇w), a relatively low on-voltage (represented by VPASS_L0W) is applied to one of the end word lines (eg, WL0 and WL7). Or both, applying the usual, higher VPASS to other unselected word lines. For example, if %(10) varies between 12 and 20V, then VPGM_L〇w can represent a range from 12 to 16. This boost mode resolves the program interference mechanism that affects the end word line. In particular, if VPASS having the same value is applied to all unselected word lines (including the end word lines), the slow rate is due to the injection of electrons into the storage elements associated with the end word lines. Leakage or GIDL can occur on the gate. The boost mode depicted can solve this problem. In addition, when vPGM is in a higher range (represented by Vpgmhigh), for example, in the range of 16 to 20 V, as shown in Figure nb, the turn-on voltage on the end word line can be raised back to other unselected The level of the word line, for example, to VpASS. Or, the on-voltage of the end word line can be raised to the intermediate level vPASS_INT, which is less than VpAss but greater than

VpASS-LOW 0 Figure 11b depicts a fourth modified erase region self-boosting mode implemented via a plurality of word lines. In one method, the fourth REASB mode is depicted by an instance word line 1150 in communication with the set of storage elements disposed in the "reverse" port. 126206.doc -22- 200836203 Here, when the VPGM on the selected word line WL4 is in the higher range of values (represented by VPGM-HIGh), the turn-on voltage on the end word lines (WL0 and WL7) is raised back. To other unselected word lines, for example, to VpASS 〇

Additionally, different boost modes can be implemented based on the location of the selected word line. For example, when a boost mode switch occurs during a burst, switching can occur at a location in the burst based on the relative position of the selected word line. In one method, switching from SB or LSB to EASB or REASB occurs relatively late in the burst when the position of the selected word line is relatively close to the drain side of the unselected "reverse" string. Figure 11c depicts a fifth modified erase region self-boost mode implemented via a plurality of word lines. In one method, the fifth rEASB mode is depicted by an example word line that communicates with the set of storage elements disposed in the "reverse" string. This boost mode is similar to the boost mode of Figure 1U, but when ... (10) is in the lower range (represented by VPGM_L0W), a lower vPASS (vPASS.L0W) is used for each of the unselected word lines. When vPGM reaches a higher range (represented by Vp(10) offset), this mode can be followed by the boost mode of Figure 11b. Various other combinations are also possible. For example I and f, the VPASS of the selected word line other than the end word line may be higher than the VpAss of the end word line, regardless of ^(10). Additionally, there may be more than two (10) ranges that trigger a change in boost mode. Figure 12 depicts a timeline showing how rough and fine stylization can be achieved by setting the bit line suppression voltage. As mentioned, the boost panel 丌 & 切换 switching can occur based on the coarse/fine mode stylized state. Rough/fine stylization allows the threshold voltage of the storage component (VTT, singularity +, electric & (VTH) to be more severe during the stylized period than 126206.doc -23- 200836203 and then during fine stylization Slowly increase to the desired level. For the ten pairs, , and ° private state, you can use the lower verification level vL and the higher verification bit to complete V. A^ early νΗ. Special 5, when the voltage A coarse stylization occurs when the threshold is below VL, and a fine stylization occurs when the voltage threshold is between VL and VH. Rough/fine stylization provides a tight voltage distribution to the programmed storage element. See Figure 21d."

Curve 1200 indicates a change in the Vth of the storage element over time, and curve 1250 indicates that the bit line voltage (VBL) applied to the bit line associated with the storage element can be made by providing a bit line suppression voltage VpARTIAL inhibit The stylization of the memory component is slowed down. When the resistive voltage pulse effect applied by the rejection is more than Vh, 'VFULL INHIBIT is applied to the bit line to place the storage element in the suppression mode. In the suppression mode, the storage is performed. Components are locked to prevent further stylization and verification. Different values and values can be associated with different states of the polymorphic storage element (e.g., states A,; 3, and c) to allow for coarse/fine stylization of different states. Suppressing the voltage slows down the stylization and thereby allows for more precise control of the stylized voltage threshold level. In one method, vPARTIALINHIBIT (usually 0 5 to 1 () v) reduces the electric field across the oxide and passes it to the r-"string during stylization. This situation requires that the gate voltage be chosen high enough to pass this voltage, typically 2.5 v. In addition, the reduced step size in the VPGM burst can also be used to provide a fine stylized mode. This can be done with or without a suppression voltage on the bit line. Thus, in a method, when a single pulse train of a programmed pulse is applied to a selected word line, it can be determined by determining that a certain number of storage elements (eg, 'one or more') have reached a lower verify level. Rough stylized mode 126206.doc -24- 200836203 Switch to fine stylized mode A ^ ^ u A uses coarse/fine stylization. In addition, in the multi-pass stylization mechanism, the stems and soaps are roughly/finely programmed, in which the storage elements are programmed to be close to the final stylization conditions. And in the second pass, the programmatically digitizes the storage element from the time to the finalization: U 〃 遍 程式 程式 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可 亦可Example

VPG secrets can be reduced, for example, from 12 to 20 V in the first pass to the first 20 V when using fine stylization. Figure 13 depicts a cross-sectional view of the unselected "" of the stylized and erased regions in the case of an EASB (such as that depicted in the figure) or REASB (depicted in Figure 9). The view is simplified and not to scale, and the series 1300 includes a source side select gate 1306, a drain side select gate 1324, and eight storage elements (1) (10), 1310, 1312 formed on the substrate 1390. , 1314, 1316, 1318, 1320, and 1322. The components can be formed on the n-well region on the P-well region of the substrate. In addition to the bit line 1326 (bit line) having the potential Vdd, the source supply line 13 04 with the potential Vs〇urce is provided to provide VPGM to the selected word line during the stylization (in this case 'WL4) The word line is associated with storage element 1316. In addition, it is reiterated that the control gate of the storage element can be provided as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 may extend through the control gates of storage elements 1308, 131A, m4, 1316, 1318, 1320, and 1322, respectively. Vls is applied to the source side word line (WL3, referred to as the isolated word line) of the selected word line. 126206.doc -25-200836203:_ is applied to the remaining word lines associated with the "reverse" string 1300. Put VsG, add to the selection gate (four) write ' and apply ¥ coffee to the selection gate (10). Assume that the stylized self-storage element 1308 along the storage element of the "reverse" string 1300 is advanced to the storage element 1322. When the other "reverse" strings are stored in the associated storage element, the storage elements 1308 through 13 are stored. 14 will have been programmed and storage elements 1318 through 1322 will not be programmed. Note that when the "reverse" string is suppressed, the unprogrammed storage element 131 is therefore, depending on the stylized mode, all or some of the storage elements 13〇8 to 1314 will be stylized and stored in their respective categories. The electrons in the floating gate, and the storage elements 1318 through 1322 can be erased or partially programmed. For example, in the first step of the two-step stylization technique, the storage elements 1318 to 1322 may be programmed in (4). Additionally, in the case of the EASB or REASB boost mode, a sufficiently low isolation voltage VIS0 is applied to the source side neighbors of the selected word line to isolate the stylized and erased channel regions in the substrate. That is, a portion of the channel (eg, region 1350) of the substrate on the source side or the stylized side of the unselected "reverse" string is opposite to the unselected r and the bottom side of the string or unprogrammed A portion of the channel on the side (eg, region 1360) is isolated by boosting channel region 135 by applying VPASS to WL0 through WL2, by applying VPGM to WL4 and applying VPASS to WL5. The channel region 1360 is boosted on WL7. Because VPGM is dominant, the erase region 136〇 will experience a relatively higher boost than the stylized region 1350. Figure 14 illustrates an example of an array of "reverse" storage elements, such as the arrays shown in Figures 1 and 2. Along each row, the bit line 14〇6 is coupled to the “reverse 126206.doc -26-200836203 and” string 1450 of the drain select terminal of the drain terminal 1426. Along the respective columns of the "reverse" string, the source line 14〇4 can be connected to all source terminals 1428 of the source selection gate of the "reverse" string. U.S. Patent Nos. 5, 57, 315; 5,774,397; & 6, G46, 935 will find examples of "reverse" architecture arrays and their operation as part of a memory system. The array of storage elements is divided into a plurality of storage element blocks. As is common to flash EEPROM systems, the block is the unit of erasure. That is, each block contains a minimum number of storage elements that are erased together. Each block is usually divided into a number of pages. The page is a stylized unit. In an embodiment, individual pages may be divided into segments and the segments may contain a minimum number of storage elements that are written once with the basic programming operation. The data of one or more pages is typically stored in a list of storage elements. The page can store one or more sectors. The sector includes user data and additional information. The additional information includes an error correction code (Ecc) calculated from the user data of the sector. One portion of the controller (described below) counts the ECC' when programming the data into the array and also checks for ecc when reading data from the array. Alternatively, store the ECC and/or other additional materials on a different page than the user profile to which it belongs or in a different block. The user data of the sector is usually 512 bytes, which corresponds to the size of the sector in the disk drive. Additional information is usually an additional 16 to 2 bytes. The big page forms a block that includes pages from 8 pages (for example) up to 32, 64, 12 8 or more. In some embodiments, a column of "reverse" strings contains a block. In one embodiment, by raising the p-well to an erase voltage (eg, 2〇ν) 126206.doc -27-200836203 for a sufficient period of time and when the source line and the bit line are floating The word line of the block is grounded to erase the memory storage element. Due to the capacitive coupling, the unselected word lines, bit lines, select lines, and turns are also raised to the majority of the erase voltage. Therefore, a strong electric field is applied to the tunneling oxide layer ' of the storage X' and the material of the memory element is erased when the electrons of the floating gate are normally emitted to the substrate side by F〇wler_N〇rdheim tunneling. When the electronic self-floating gate transmits the "well area, the threshold energy of the selected storage element is low. It can be performed on the entire memory array and the independent component.

Figure 15 is a block diagram of a non-volatile memory system using a single column/row decoder and a read/write circuit. The figure illustrates a memory device 1596 having a read/write circuit for storing and staging a storage element of a page in parallel, in accordance with an embodiment of the present invention. Memory device 1596 can include one or more memory dies 1598. The memory die 1598 includes a 2' dimension (4) of the storage element, a control circuit 151A, and a read/write circuit 1565. In some embodiments, the array of storage elements can be 3 dimensional. The memory array can be just addressed by the column line 1530 from the word line and by the row decoder (10) by the bit line. The read/write circuit (10) includes a plurality of sensing blocks that are read or programmed in parallel - the storage elements of the page. Typically, controller 1550 is included in the same memory port as the or so memory die 598, e.g., a removable memory card. Commands and data are transmitted between the host and the controller (10) via line 1520, and commands and data are transmitted between the controller and the or such memory die 1598 via line (5) 8.

The control circuit 1 5 1 敌 读 宜 λ ” ” 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写1514 and power control module 1516. The state provides wafer level control for the operation. The crystal address decoder is used by the host or the device and the address used by the decoder and the device. An address interface is provided between the body addresses. The power control module 1516 controls the power and voltage supplied to the word lines and bit lines during the memory operation. In some embodiments, some of the components of FIG. 15 may be combined. In various aspects, one or more of the components other than the storage element array 400 (alone or in combination) may be considered as a management circuit. For example, one or more management circuits may include the control circuit 1510. Any one or combination of state machine 1512, decoder 1514/1560, power control 1516, sensing block 15A, read/write circuit 1565, controller 155, etc. Figure 16 is a use of dual columns /row decoder and read/write circuit non-swing A block diagram of a memory system. Here, another configuration of the memory device 1 596 shown in Figure 15 is provided. The memory array 14 is stored by various peripheral circuits on opposite sides of the array in a symmetrical manner. Take so that the access line and circuit robbing on each side is reduced by half. Therefore, the column decoder is divided into column decoder (5) slave and moB, and the row decoder is divided into row decoder and 1560B. Similarly, read / The write circuit is divided into a read/write circuit 15658 connected to the bit line from the bottom of the array 14A and a read/write circuit 1565B connected to the bit line from the top of the array 14A. The density of the read/write module is substantially reduced by one. As described above with respect to Figure 15, the device of Figure 16 may also include a controller. Figure 17 is a touch sensing block. A block diagram of one embodiment. The individual sensing 126206.doc -29-200836203 block 1500 is divided into a core portion (referred to as sensing module 158A) and a common portion 1590. In an embodiment, There will be an independent sensing module 1580 for each bit line, and the needle One of the plurality of sensing modules 158 will have a common portion 1 590. In one example, the sensing block will include a common portion 1590 and eight sensing modules 1580. Sensing in a group Each of the modules will communicate with the associated common portion via data bus 1572. For more details, please refer to the title published on June 29, 2006 and incorporated herein by reference in its entirety. Non_v〇latUe MemQ1T &

US Patent Application Publication No. 2〇〇6/〇14〇〇〇7, which is incorporated by reference. The sensing module 1580 includes determining that the conduction current in the connected bit line is a bureau. The sensing circuit is further below a predetermined threshold level. The sensing module 158 also includes a bit line latch 1582 for setting a voltage condition to the connected bit line. The predetermined state latched in the bit line latch 1582 will cause the connected bit line to be pulled to a specified stabilizing state (eg, Vdd). The common portion 1590 includes a processor 1592, a data lock The memory set 1 594 and an I/O interface 1596 coupled between the data latch set 1 594 and the data bus 1 wo. The processor 1592 performs calculations. For example, one of its functions is Determining the data stored in the sensed storage element and storing the determined data in the data latch set. The data latch set 15 94 is for storage by the processor 1 $92 during the read operation. Data bit. It is also used to store The data bit input from the data bus 1 520 during the operation. The input data bit indicates the data to be written in the intended program 126206.doc -30- 200836203. The I/O interface 1596 is in An interface is provided between the data latch 1594 and the data bus 1520. During reading or sensing, the operation of the system is controlled by a state machine 丨5丨2, which controls the storage of different control gate voltage pairs. Supply of components. The sensing module 15 8 can be one of the voltages when it is stepped through various predetermined control gate voltages corresponding to various memory states supported by the memory. At the moment, the output is provided from the sensing module 1580 to the processor 1592 via the bus 1572. At this time, the processor 1592 takes the tripping event of the sensing module and the state machine from the input line 1593. The information about the applied control gate voltage is used to determine the resulting memory shape. The binary code is calculated for the memory state and the resulting data bit is stored in the data latch 1594. One real In the example, the bit line latch 1582 is used for dual purposes, both as a latch for the output of the second memory sensing module 1580 and also as a bit line latch as described above. ^ Expected - Some embodiments will include a plurality of processors 1592. In one implementation, each processor (10) will include an output line (not depicted in Figure 7 = each of the output lines are commonly lined or connected. In some embodiments, ^ inverts the transmission line before connecting the transmission line to the line or line. This group can quickly determine the completion time during the stylized verification process because the receive line or state machine can determine the positive time The moment to reach the desired level. For example, when each bit is aligned, the logical zero of the bit will be sent to the line ^ to be inverted. When all bits output data. (or the reversed asset: 126206.doc .31 - 200836203 is the same as the strain; knows to terminate the stylization process. Because each processor communicates with eight sensing modules' so the state machine needs to read the line or The line is eight times, or the logic is added to the processor 1592 to accumulate the result of the associated bit line, such that the line ~, the branch only draws the line or line once. Similarly, by correctly selecting the 33 position Quasi, the overall state machine is integrable (4) The first unit changes its & state and thus changes the algorithm. During stylization or verification, the data to be programmed from the data bus 1520 is stored in the data latch. The set is 159. Under the control of the state machine, the stylization operation includes a series of stylized voltage pulses applied to the control idle of the addressed memory element. Each stylized pulse is then read back (verified) to determine Whether the storage element has been programmed to the desired memory state. The processor 1 592 monitors the memory of the readback with respect to the desired memory state. When the two states are identical, the processor 1592 sets the bit line latch. 1582 to make the line Specifies the state of stylization suppression. This situation suppresses storage elements coupled to bit lines from further stylization, even if stylized pulses appear on their control gates. In other embodiments, the processor is initially loaded. Bit line latch 1582, and the sense circuit sets it to a suppressed value during verify 2. ^ Data latch stack 1594 contains a stack of data latches corresponding to the sense module. In the example, each sensing module 158 is in three data latches. In some embodiments (but not necessarily), the data latch is applied to the shift register H, so that it is expected to be in its towel. The parallel dump is converted to the serial data of the data bus 152G, and vice versa. In each of the preferred examples, the read/write block corresponding to the m storage elements can be replaced by two = 126206 .doc -32- 200836203 The material latches are linked together to form a block shift register so that the block of data can be input or output by serial transfer. In detail, the set of r reads is adapted. /write module so that each of its data latch sets will be The data bus is sequentially moved in or out as if it were part of a shift register for the entire read/write block. Various embodiments for non-volatile storage devices can be found in the following Additional information on the structure and/or operation: (1) US Patent Application Publication No. 2004/0057287, published on March 25, 2004, ''Non-Volatile Memory And Method With Reduced Source Line Bias Errors'; U.S. Patent Application Publication No. 2004/0109357, issued June 10, 2004, 'Non-Volatile Memory And Method with Improved Sensing'; (3) US Patent Application filed on December 16, 2004 Clause 11/15, 199, entitled "Improved Memory Sensing Circuit And Method For Low Voltage Operation"; (4) U.S. Patent Application No. 11/099,133, filed on April 5, 2005, entitled &quot ;Compensating for Coupling During Read

Operations of Non-Volatile Memory"; and (5) U.S. Patent Application Serial No. 11/321,953, filed on Dec. 2, 2005, entitled "Reference Sense Amplifier For Non-Volatile Memory" All of the five patent documents listed above are hereby incorporated by reference in their entirety. FIG. 18 illustrates an example of organizing memory arrays into blocks for a full bit line memory architecture or for a parity memory architecture. An exemplary structure for the storage element array 1400 is described. As an example, a "reverse" flash EEPROM that is divided into ι, 24 regions 126206.doc - 33 - 200836203, and the BL0, BL1 blocks are described. The data stored in each block can be erased at the same time. In one embodiment, the block is the smallest unit of storage elements that are simultaneously erased. In each block, in this example 'there is a pair of Z bits in 8,512 rows called the all-bit BL8511. In one embodiment of the line (ABL) architecture (architecture 1810), all of the bit lines of a block can be selected simultaneously during read and program operations. Storage elements along a common word line and connected to any bit line can be programmed simultaneously. f

In the example provided, four storage elements are connected in series to form a "reverse" string. Although four storage elements are shown to be included in each "reverse" string, more or less than four (e.g., 16, U, 或 or another number) may be used. The "reverse" string-terminal is connected to the corresponding bit line via the poleless selection pole (connected to the selected gate electrode line SGD), and the other terminal is connected to the selection gate via the source selection gate The source line sgs) is connected to the c-source. In another embodiment, referred to as an odd-even architecture (architecture 18), the bit lines are divided into even bit lines (BLe) and odd bit lines (BL〇). In the odd/even bit line architecture, the -it stylized along the common word line to the odd bit line store it, and the other time stylized along the common word line and connected to the even bit Line storage component. Data can be programmed into different blocks at the same time and data can be read from different blocks. In this example, there are 8, 5 12 rows in each block, which are divided into even rows and odd rows. In this example, four storage elements are connected in series to form a "reverse" string. Although four storage elements are shown to be included in each "reverse" string, more or less than four storage elements can be used. 126206.doc -34- 200836203 In the item acquisition and weighting operation, store; open Du belt, joint, heart / month, select 4,256 at the same time 1 save 7L pieces. The selected storage has the same word line and the same type of position line (for example, even number or Fen disk., Γ ^ ^ ^ one. The mouth can be read or stylized at the same time ^ ^ , And the bells, and one block of the memory can be even..., wide word lines, each with an odd page heart storage element, when each storage element stores two bits of information, Japan, Ganzibei Time (where the two bits

Stored on different pages), one @抡蚀六丄 The mother's system) The Q block stores sixteen logical pages. Blocks and pages of other sizes can also be used. For a fox architecture or a parity architecture, the storage elements can be erased by raising the p-well to a voltage of (e.g., 2GV) and grounding the word lines of the selected block. Source line and bit line system (4). Erasing can be performed on the entire memory array, on a separate block, or on another unit of the storage element of the memory device. The floating gate of the electron self-storing S piece is transferred to the P well area, so that the VTH of the storage element becomes negative. In the read and verify operations, the select gate (SGD and SGS) is connected to the voltage in the range of 2·5 V to 4.5 V, and the unselected word line (for example, when WL2 is the selected word line) (d), wl1 & wl3) is raised to the read turn-on voltage vREAD (typically a voltage in the range of 4·5 ¥ to 6 v) to operate the transistor as a turn-on gate. The selected word line WL2 is coupled to a voltage that is specified for each read and verify operation to determine if the VTH of the associated storage element is above or below this level. For example, in the read operation wipe of the double-order storage element, the selected word line WL2 can be grounded so that the detection of VTH is higher than 〇V. For example, in the verify operation of the two-level storage element 126206.doc -35 - 200836203, the selected word line WL2 is coupled to 〇·8 v such that it verifies that the VTH has reached at least 0.8 volts. The source and p wells are 〇 v. The selected bit line (assumed to be an even bit line (BLe)) is precharged to, for example, 2 〇. If VTH is above the read or verify level on the word line, the potential level of the bit line (BLe) associated with the associated memory element remains high due to the non-conductive storage element. On the other hand, if the % is lower than the read or verify level, the potential level of the associated bit line (BLe) is reduced to a low level (eg, less than 〇·5 V) because the conductive storage element makes the bit line Discharge. The state of the storage element can thereby be determined by the voltage comparator sense amplifier connected to the bit line, according to techniques known in the art, to perform the above erase, read and verify operations. Therefore, many of the explained details can be changed by those skilled in the art. This technology can also be used. Other erasures, acquisitions, and inspections = a set of examples of distributions. Examples of storage element arrays for each of the conditions of the data: two bits of data.

Vth distribution. For the erased storage, the two pieces of the device are given a threshold voltage distribution E. It also shakes the stylized storage components of a cow's threshold voltage distribution A, B and C. In one embodiment, the remainder of the E distribution τ and the 'limit voltage are negative and the threshold voltage in A, the division is positive. Each distinct threshold voltage range 斟_μm broadcast, W corresponds to a predetermined value for the set of data bits. Stylized to the storage component it ^ pe ^ ^ The specific relationship between Beike and the storage device's threshold voltage is determined by the data encoding mechanism used for ΦΙ ο βι, J , and side storage components. For example, U.S. Patent Application Serial No. 126,206, filed on Jun. Various data encoding mechanisms for polymorphic flash storage elements. In an embodiment, a Gray (call) code assignment is used to assign a data value to a threshold voltage range such that when the threshold voltage of the floating gate is erroneously shifted to its neighboring entity state, only one bit element is affected .

An example assigns "11" to the threshold voltage range E (state E), assigns 1〇" to the threshold voltage range A (state A), and assigns "〇〇" to the threshold voltage range B ( State B) and assign "〇1" to the threshold voltage range c (state c). However, in other embodiments, the Gray code is not used. Although four states are shown, the invention can also be applied to other polymorphic structures, including polymorphic structures that would include more or less than four states. Three read reference voltages Vra, Vrb, and Vrc are also provided for reading data from the storage element. By testing whether the threshold voltage of a given storage element is above or below Vra, Vrb, and Vrc, the system can determine the Z state of the storage element, such as a stylized condition. In addition, three verification reference voltages Vva, Vvb, and Vvc are provided. When the storage element is programmed to state A, the system will test if the storage elements have a threshold voltage greater than or equal to Vva. When the storage element is programmed to state B, the system will test whether the storage element has a greater than or equal to w = threshold voltage. When the storage element is programmed to state c, the system will determine if the storage element has its threshold voltage greater than or equal to Vvc. In the so-called full sequence stylization-implementation, the storage element can be directly programmed from the erased state E to the stylized state A, B or c. For example, s can be erased first. A population of storage elements, 126206.doc -37- 200836203 causes all storage elements in the population to be in an erased state E. The storage element is then directly programmed to state A, B or C using a series of programmed pulses, such as the control gate voltage sequence diagram of Figure 23. While some of the storage elements are programmed from state E to state A, other storage elements are programmed from state E to state B and/or from state E to state c. When staging from state E to state c on WLn, the amount of parasitic coupling to the adjacent floating-flip gate below WLn-Ι is maximized because it is stylized from state E to state A or self-state E. The change in the amount of charge on the floating gate below WLn is greatest compared to the change in voltage when stylized to state b. When staging from state E to state b, the amount of coupling to adjacent floating gates is reduced but still significant. When staging from state E to state A, the amount of coupling is further reduced. Thus, the amount of correction required to subsequently read each state of WLndi will vary depending on the state of the adjacent storage elements on WLn. Figure 20 illustrates that the stylization is stored for two different pages (lower page and upper page). An example of a two-pass technique for polymorphic storage elements of data. Describe four states: the shape of the heart (the sorrow A (10), the state B (00) and the state C (〇l). For the state E' both pages are stored". For the state a, the lower: face Save "〇" and the upper page stores "1. For state B, both pages store "0". For state C, store, ,, and 疋 bit styles are assigned to the parent in those states. , but you can also assign different bit styles. In the first stylized pass, set the storage component to the lower logical page according to the bit. If the bit is logic 126206.doc - 38- 200836203 τ, does not change the threshold voltage, because this bit is in the field because of the earlier erasure. However, if the bit to be programmed is logic, then 70 pieces of the product limit are stored. The increase is in state A, as indicated by arrow i 1 (9). The first stylized pass ends. In the second stylized pass _, the storage element is set according to the bit that is being programmed into the upper logical page. Limit the voltage level. If the upper logic page bit will store logic, r, no program will occur. Because the storage element is in one of the states E or A depending on the stylization of the lower page bit, both states carry the upper page bit "Γ. If the upper page bit is logical ''〇,', The county threshold voltage shift. If the storage element is maintained in the erased state E' for the first time, the storage element is programmed in the second stage, so that the threshold dust is increased to be in the state c as indicated by the arrow 2 2. If the storage element has been programmed to state A due to the first stylization, then the storage element is further programmed in the second pass to increase the threshold voltage in state B, as The result of the second pass is to program the storage element to a state that is designated to store logic "〇" on the upper page without changing the data of the lower page. In Figures 19 and 2, The amount of coupling of the floating gates on adjacent word lines depends on the final state.

In one embodiment, the system can be set up to perform a full sequence of writes (filling the entire page if enough data is written). If sufficient information is not written for the full page, the stylization process can be programmed to program the lower page with the received data. When subsequent data is received, the system will then follow the stylized facade. In a further embodiment, the system can program the lower page mode to begin writing, and if it subsequently receives enough data to fill the entire (or most) word H 126206.doc -39- 200836203 storage element, then convertible To full sequence stylized mode. Further details of this embodiment are disclosed in the June 2006 issue of I5曰.

U.S. Patent Application Publication No. 2006/0126390 to Volatile Memories Using Early Data.

Figures 21a through 21c illustrate another process for staging non-volatile memory that reduces the effects of floating gate-to-floating gate coupling by, for any particular storage element, data for the previous page. Data is written to this particular storage element with respect to a particular page after being written to an adjacent storage element. In the example embodiment, the non-volatile storage element stores four bits of data for each storage element using four data states. For example, =, assume that state E is the erased state and state A is the stylized state. State E stores the immortality. State A stores data 〇1. State b stores funds (4). State C stores data. This is an example of non-Gray coding because the two bits change between adjacent states. Other codes that enable the data to be in the state of the entity data can also be used. Every—storage (4) is stored (4). For the purpose of reference, these data pages are referred to as the upper page and the lower page, however, the basin can be recognized; 〇, and other marks are given. Regarding state A, on: face storage: bit. And the lower page stores the bit. Regarding state B, the last hundred:: child: where 1 and the lower page stores the bit 〇. Regarding state C, both pages store bit data 〇. This stylization process is a two-step process. On the + page. If the lower page will be saved, the lower state E will be programmed. If the data is programmed to 〇, the state of the storage element is maintained at the voltage threshold of 126206.doc -40-200836203 high so that the storage element is programmed to state B. Figure 21a thus shows the staging of the storage element from state E to state B. State B is the temporary state B. Therefore, the verification point is depicted as Vvb, which is lower than Vvb.

In one embodiment, the storage element is programmed from state E to state B, and its adjacent storage element (WLn+1) in the "reverse" string will then be programmed with respect to its lower page. For example, referring back to Figure 2, after the page below the stylized storage element 106, the page below the component (10) will be stylized. After staging the storage element 104, if the storage element 1〇4 has a threshold voltage from state E to state B, the coupling effect of the floating gate to the floating gate will make the storage element 1〇6 look The threshold voltage rises. This will have the effect of widening the threshold voltage distribution for state B to the distribution depicted by the threshold voltage distribution 215 如图 of Figure 2ib. This apparent widening of the threshold voltage distribution will be corrected when the upper page is programmed. Figure 2U depicts the process of stylizing the upper page. If the storage element is in the erased state E and the upper page will remain at i, the storage element will remain in state E. If the storage element is in state E and its upper page data is programmed to =, then the threshold voltage of the storage + storage component will rise, causing the storage component to be in a state of complaint. If the storage element is in the intermediate threshold voltage distribution 2150 and the upper page is kept lean! , the storage component will be programmed to the final state b. If the storage: the component is in the middle threshold voltage distribution 215〇 and the upper page data will change, the lean voltage will increase the threshold voltage of the storage component, so that the storage component:; i, c. The process depicted by Figures 21a through 21c reduces the effect of the coupling of the floating gate to the floating gate because only the page top of the adjacent storage element "has an effect on the apparent threshold voltage of a given storage element. 126206.doc -41 · 200836203 An example of state code is to move from state 21 50 to state C when the top page _ ow 4 page material is 1, and move to state B when the upper page data is 。. Although Figure 21β 2le provides examples of four f-states and two profile pages' but the concepts taught can be applied to other embodiments having more or less than four states and different pages.

The figure depicts the rough/fine stylization process. As previously mentioned in conjunction with '' initially, the storage element can be programmed in a coarse mode to move it quickly to the target's private condition and then programmed in a fine mode to slow it down with greater accuracy. Move to the target stylization condition. The fine stylized mode can, for example, use a reduced step size in the VpGM burst and/or apply a suppression voltage to the bit line of the string. In addition, coarse_fine stylization can occur in one-time or multiple-pass stylization. In one pass coarse/fine stylization, as indicated in Figure 23, there is a switch from coarse stylization to fine stylization during the VPGM burst. In contrast, in multi-pass rough/fine stylization, for example, coarse privateization can be used during the first pass and fine stylization used during the second pass. As shown in the figure, switching from coarse stylization to fine stylization can occur, for example, between integer VpGM bursts. Additionally or alternatively, the Vp(10) burst may use a lower range of values in the second pass or other additional pass stylization. Multiple pass coarse/fine stylization can be considered as a multi-pass stylization of a particular type, which typically involves, for example, using more than one burst to program the storage element to the target stylized condition in more than one pass. . For example, the storage element can be programmed from the erased state (state E) to the privately stylized state A, B or C. In one method, the stylized 126206.doc -42-200836203 is used to program the stored 7L pieces into a temporary state A, B, or c, which have associated verification levels ^^%, Vvbi, respectively. ^VvcL. The subscript, l" indicates that the inspection level is also associated with a lower state than the target state. Subsequently, using the fine stylization to stylize the storage element from the temporary state to the state A, B or C, etc. The associated verification level VvaH, VvbH or η red Η indicates that the verification level is associated with a higher centroid for the final target state. The threshold voltage of the programmed storage element is therefore during the first stylization phase. The first quasi (eg, state Α) is increased to the second level (eg, VvaL, VvbL4VvCL) and increased from the second level to the third level during the second stylized phase (eg, VvaH, VvbH, or Vvch) Figure 22 is a flow diagram depicting one embodiment of a method for staging non-volatile memory. In one embodiment, the storage element (in blocks or other units) is erased prior to stylization. In the middle, issued by the controller, the data is loaded into the π command and received by the control circuit 151. In step 22〇5, the address data of the specified page address is input from the controller or the host to the decoder 1514. In step 2210, it will be used The stylized negative of a page of the addressed page is input to the data buffer for stylization. This data is latched into the appropriate set of latches. In step 2215, the controller will, stylize ' The 'command is sent to the state machine 1512. The stepped stylized pulses 23 〇 5, 23 1 〇, 2315 of the pulse train 2300 of Figure 23 applied to the appropriate selected word line will be triggered by the stylized '' command. , 2320, 2325, 2330, 2335, 2340, 2345, 2350...

The data latched in step 2210 is programmed into the selected storage element controlled by state machine 1512. In step 2220, the programmed voltages VPGM 126206.doc • 43-200836203 are initialized to a start pulse (e.g., 12V or another value) and the programmer (4) (4) maintained by state machine 1512 is initialized to zero. In (4), the initial boost mode is applied, and the name +, fly, and in step 2230, the first VPGM pulse is applied to the word line of the selected one to start borrowing and selecting. The storage element associated with the zigzag line. If the logic "〇," is stored in a specific data latch indicating that the corresponding storage element should be programmed, the corresponding bit line is grounded. On the other hand,

"1" stored in a specific latch refers to the dry phase 廍 H A 曰 曰 曰 相应 相应 相应 相应 相应 相应 相应 相应 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In step 2235, the status of the storage element is verified. If it is detected that the target threshold voltage of the selected storage element has reached the appropriate level, the data stored in the corresponding data latch becomes logical "i ". If it is detected that the threshold voltage has not reached the appropriate level, the data stored in the corresponding data latch does not change. In this way, the v and the multi-type do not have to be programmed to store the logic T, the bit line in the corresponding data latch. When all data latches store logic τ, the state machine (via the line or type mechanism described above) knows that all selected storage elements have been programmed. In step 224, a check is made as to whether all data latches store logic '4". If all data latches store logic T ', the stylization process is completed successfully' because all selected storage elements are programmed and verified. In step 2245, the report "passes the pass". If it is determined in the step test that the (4) register stores the logic "1", the stylization process continues. In step 225, the program counter PC is checked against the programmed limit PCmax. An example of one of the stylized limits is twenty; however, other numbers may be used. If the program counter PC is not less than PCmax', the stylization process fails and is reported in the step coffee 126206.doc -44- 200836203. If the right program counter PC is less than pcmax, then in step 2260 Vpgm is incremented by the step size and the program counter Pc is incremented. At step 2265, a determination is made as to whether the boost mode switching criteria (e.g., see Figure 4) is met. If this criterion is met, the boost mode is switched at step 227, and the process returns to step 2230 to apply the next vPGM pulse. If the boost mode switching criteria are not met at step 2265, the process returns to step 2230 to apply the next VpGM pulse without changing the boost mode. Figure 23 depicts an example pulse train 2300 applied to the control gate of the non-volatile storage element during the privateization, and a boost mode switch that occurs during the burst. Burst 2300 includes a series of stylized pulses 2305, 2310, 2315, 2320, 2325, 2330, 2335, 234G, 2345, 2350, ... applied to the word line selected for stylization. In an embodiment, the stylized pulse has a voltage vPGM that begins at 12 v and increments (e.g., 〇·5 V) for each successive stylized pulse until a maximum of 2 〇 V is reached. There is a verify pulse between the stylized pulses. For example, the set of verification pulses 2306 includes three verify pulses. In some embodiments, an authentication pulse may exist for each state to which the material is being programmed (e.g., states A, B, and C). In other embodiments, there may be more or fewer verification pulses. For example, the verification pulses in each set can have amplitudes Vva, VVb, and VVC (Fig. 20), Vvb, (Fig. 21a), or VvaL, Vvbi^VvcL or

VvaH, VvbH and VVCh (Fig. 2id). The switching of the boost mode is depicted as occurring before the application of the stylized pulse Μ, the first boost mode is applied, and after the switching, the second boost mode is applied. As mentioned, when stylized When it occurs (for example, when ^ 126206.doc •45-200836203 〆 applies a stylized pulse), the application of the applied voltage to the word line to implement the boost mode can be slightly increased before each stylized pulse. The boost voltage of the start boost mode is removed after each stylized pulse. Therefore, during the verify process (eg, it occurs during a programmed pulse, no boost voltage is applied. Instead 'will usually be less than The boost voltage (4) is applied to the unfinished word line. The read voltage has an amplitude sufficient to be inverted when the threshold voltage of the currently stylized storage element is being compared with the verify level. The previously stylized storage element remains open. Thus, in a first stylization phase, the first subset of the stylized pulses in the burst 2300 (eg, pulses 2305, 2310, 23b) , 232G, 2325 and 233()) Applied to - or a plurality of storage elements' and in a second stylization phase, applying a second subset of pulses (eg, pulses 2335, 234A, 2345, 235A) in the burst to the Storage elements. Each stylized pass can therefore include multiple stylization stages. t ® 24 rides between the program (4) (4) the instance pulse of the control gate of the volatile element, and the boost between the bursts Switching mode switching mode 5, the switching mode of the boost mode is generated between the burst 2 gamma and 245: Before the switching, during the first burst 2, the first boost mode should be used. 'And after the switch, during the second burst 245, the second boost mode is applied. For example, the burst 24 可 can be applied during the first pass in the multi-pass stylization process, while The burst 2450 is applied during the second pass of such stylized privacy. Thus, in one method, the first burst is in the first stylized phase (eg, burst 126206.doc -46-200836203 2400) applied to one or more storage elements on the selected word line, and In the second stylization phase, a second burst (eg, burst 245 〇) is applied to the or the storage element. Each stylized pass can thus be consistent with the stylization phase. For purposes of illustration and description The foregoing detailed description of the present invention is intended to be illustrative and not restrictive The principles of the invention and its practical application, in order to enable those skilled in the art to <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The scope of the patent application is intended to define the scope of the invention. X [Simple description of the figure] β Figure 1 is a top view of the "reverse" string. Figure 2 is an equivalent circuit diagram of the "reverse" string of Figure 1. Figure 3 is a block diagram of an "reverse" flash memory device array. Figure 4 depicts a conceptual diagram showing the boost mode decision process. Figure 5 depicts a process for switching the boost mode during stylization. Figure 6 depicts a self boosting mode implemented via a plurality of word lines. Figure 7 depicts a local self-boost mode implemented via a plurality of word lines. Figure 8 depicts an erase region self-boost mode implemented via a plurality of word lines. And depicting the first-to-reverse boost mode implemented via a plurality of word lines. Figure 1 depicts a second modified erase region implemented by a plurality of word lines from 126206.doc • 47· 200836203 Boost mode.

And boost mode. Figure 12 ^ Tian Jian Exhibition does not have a timeline that is finely programmed by setting bits. Figure 11a depicts a boost mode via a plurality of word lines. Figure 1 lb depicts boost mode via a plurality of word lines. FIG. 11c depicts a fifth modified erase region meta-line suppression voltage implemented by a fourth modified erase region implemented by a third modified erase region implemented by a plurality of word lines to achieve a rough representation of FIG. A cross-sectional view of an unselected "reverse" string of the erased region. Figure 14 is a block diagram of an "reverse" flash memory device array. Figure 15 is a block diagram of a non-volatile memory system using a single column/row decoder and a read/write circuit.

Figure 16 is a block diagram of a non-volatile memory system using a dual column/row decoder and a read/write circuit. Figure 17 is a block diagram depicting one embodiment of a sensing block. S 1 8 σ 儿月 An example of organizing memory arrays into blocks for the kingdom line or the parity memory architecture. Figure 19 depicts an example set of threshold voltage distributions. Figure 20 depicts an example set of threshold voltage distributions. Figures 21a through 21c show various threshold voltage distributions and describe the process for staging non-volatile memory. Figure 21d depicts a rough/fine stylization process. 126206.doc -48- 200836203 Figure 22 is a flow chart depicting one embodiment of a process for staging non-volatile memory. Figure 23 depicts an example pulse train applied to the control gate of the non-volatile storage element during stylization, and boost mode switching that occurs during the burst.

Figure 24 depicts an example pulse train applied to the control gate of the non-volatile storage element during stylization, and a boost mode switch that occurs between the bursts. [Main component symbol description] 100 transistor 100CG control gate 100FG floating gate 102 transistor 102CG control gate 102FG floating gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 106CG control gate 106FG floating gate 120 first selection gate 120CG control gate 122 second selection gate 122CG control gate 126 bit line 126206.doc 200836203 128 source line 320 "reverse" 321 bit line 322 select gate 323 storage element 324 storage Component 325 Storage Element 326 Storage Element 327 Select Gate 340 "Reverse" 341 Bit Line 342 Select Gate 343 Storage Element 344 Storage Element 345 Storage Element 346 Storage Element 347 Select Gate 360 "Reverse" 361 Bit Line 362 Select Gate 363 Storage Element 364 Storage Element 365 Storage Element 366 Storage Element 126206.doc -50- 200836203 367 Select Gate 400 Block 405 Block 410 Block 415 Block 420 Block 425 Block 430 Block 435 Block 440 Block 445 Block 460 Block 1200 Curve 1250 Curve 130 0 "reverse" string 1304 source supply line 1306 select gate 1308 storage element 1310 storage element 1312 storage element 1314 storage element 1316 storage element 1320 storage element 1322 storage element 126206.doc -51 - 200836203 1324 bungee side selection gate; 1326 bit line 1350 area 1360 area 1390 substrate 1400 "reverse" storage, 1404 source line 1406 bit line 1426 汲 terminal 1428 source terminal 1450 "reverse" string 1500 sensing block 1510 control circuit 1512 state machine 1514 Crystal Load Address Decoding; 1516 Power Control Module 1518 Line 1520 Lean Bus 1530A Column Decoder 1530B Column Decoder 1560 Line Decoder 1560A Line Decoder 1560B Line Decoder 1565 Read/Write Circuit 126206.doc, 52- 200836203 1565A Read/Write Circuit 1565B Read/Write Circuit 1570 Sensing Circuit 1572 Busbar 1580 Sensing Module 1582 Bit Line Latch 1592 Processor 1593 Input Line 1594 Data Latch 1596 Memory Device 1598 Memory Grain 1800 Parity Structure 1810 Full Bit Line Architecture 2010 Arrow 2020 Head 2150 Threshold Voltage Distribution 2300 Example Burst 2305 Stylized Pulse 2310 Stylized Pulse 2315 Stylized Pulse 2320 Stylized Pulse 2325 Stylized Pulse 2340 Stylized Pulse 2345 Stylized Pulse 126206.doc -53- 200836203 2350 Stylized Pulse 2400 Burst 2450 Burst A Stylized state A1 Temporary state B Stylized state Bf Temporary state BLe Even bit line BLO Odd bit line C Stylized state C, Temporary state E Erase state SGD Bungee side select gate control line SGS source side select gate control line Vbl bit line voltage vdd potential Vh higher verify level V iso isolation voltage Vl lower verify level VPARTIAL INHIBIT bit line inhibit voltage V PASS turn-on voltage V PASS-LOW relatively low Turn-on voltage V PGM Stylized voltage VpgM-HIGH Higher range 126206.doc -54- 200836203

VpgM-LOW Lower range V SGD Voltage V SGS Voltage V SOURCE Potential V th Threshold voltage Vra, Vrb, Vrc Read reference voltage Vva, Vvb, Vvc, Vvb' Amplitude WL1 to WL7 Word line f 126206.doc -55-

Claims (1)

200836203, the scope of the patent application: 1. A method for operating a non-volatile storage device, comprising: at least one storage component in a broadened-nonvolatile storage component set, a set of 5 non-volatile storage components and a plurality of word line communications And storing at least one of the 7G pieces and the plurality of word lines to select the selected word line; and during the stylization, applying the voltage-first set to the unselected word lines of the plurality of sub-lines, and Based on a boost mode switching criterion, a set of voltages and rg 隹 “ 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加The unselected word line, the # of the voltage is at least partially different from the second set of voltages. 2. The method of claim 1, wherein the legacy program comprises applying a burst to the selected The word line is cut = the force in the pulse train - after the first pulse and before the last pulse of one of the pulse trains is applied. 3 · The method of claim 1, wherein the stylized inclusion A pulse train is applied to the selected one Line, the rising (four) switching criterion is based on the time at which a programmed pulse having one of the specified amplitudes is applied to the selected word line. 4. The method of claim 1, wherein «· A pulse-to-four (4) is applied to the selected word line based on the time at which a specified number of stylized pulses in the burst have been applied to the selected word line. The method of item 1, wherein "·, pull ^ switching; ^ is based on the position of the selected word line in the plurality of 126206.doc 200836203 strands. 6. The method of claim 1, wherein: thawing at least _ &gt;- one of the ridge elements has a threshold voltage from a θ ^ to a second level before the switching and after the switching Two-digit increase • Add to a third level. 7. The method of claim 1, wherein: ^ sizing involves a rough stylization before the switching and a fine stylization after the switching (% 8_, as in the method of claim 1, wherein: Λ boost 杈The switching standard is based on the moment when the other storage elements in the non-volatile storage element set reach a specified stylization condition. 9. The method of claim 1, wherein the swell type switching standard is based on the non- A number of stylized cycles experienced by the collection of volatile storage elements. 10 · The method of claim 1, wherein: ί The non-volatile storage element set is provided in a plurality of "reverse" strings / a plurality of "reverse" The string includes - providing the at least - error of the component, and a string, and a) prior to the switching, a particular unselected •, the word line receives H 'the power will cause the particular unselected 'One channel region on one side of the word line is isolated from one of the channel regions on the other side of the particular unselected word line, and b) after the switching, the particular unselected word line receives a voltage, This voltage will make this particular Isolating the channel region on the other side of the channel region on one side of the set of word lines of the particular unselected word line of. A non-volatile storage system comprising: Word line communication; and one or more control circuits of the non-volatile storage element set communication, or a control circuit such as &quot;Hai and other programs to program the at least one storage element, and during the stylization, one of the voltages Applying a set to the unexposed sum of the plurality of word lines and applying the first set of voltages to the unselected word lines to switch to the first of the voltages based on a boost mode switching criterion A set is applied to the unselected word lines, the first set of voltages being at least partially different from the second set of voltages. 12. The non-volatile storage system of claim 11, wherein the control circuit or the like controls the at least one storage element by applying a burst to the selected word line, the switching applying the pulse string The middle-first pulse occurs and occurs before one of the last pulses in the pulse train is applied. 13. The non-volatile storage system of claim 11, wherein the or the control circuitry programs the at least-storage element by applying a burst to the selected word line, the a-mode switching standard A time is applied to the selected word line based on a programmed pulse having one of the finger 疋 虿 将该 amplitudes in the burst. 14. The non-volatile storage system of claim 11, wherein the pulse train is applied to the selected word, the boost mode switching criterion is that the special control circuit programs the at least one storage element by _ line 126206.doc 200836203 is based on the time at which a specified number of stylized pulses have been applied to the selected word line. 15. The non-volatile storage system of claim 11, wherein: the boost weight switching criterion is based on a position of the selected word line at one of the plurality of word lines. 16. The non-volatile storage system of claim 11, wherein: the threshold voltage of the at least one storage component is from a first level before the switching: t曰 to a second level and after the switching The second level is increased to a third level. 17. The non-volatile storage system of claim 11, wherein: the privateization involves a coarse stylization prior to the switching and a fine stylization after the switching. 18. The non-volatile storage system of claim 11, wherein: the boost mode switching criterion is based on at least one of the set of non-volatile storage elements - the time at which the staging condition is specified. 1 9. The non-volatile storage system of claim 11, wherein: the boost mode switching criterion is based on a number of stylized cycles experienced by the set of non-volatile storage elements.口2ϋ·If the request item ^千,钱,仔乐~ _ } · The non-volatile storage component set is provided in a plurality of "reverse" strings «a number of "reverse" strings including - providing the charm less - material (four) selection The "reverse" string, called before the switch, the unselected word line receives the voltage, which will cause the channel region on the particular unselected side and the word line not selected in the material. _ side 126206.doc 200836203 one of the upper channel regions is isolated, and b) after the switching, the particular unselected word line receives a voltage that will be on the side of the particular unselected word line The channel region is isolated from the channel region on the other side of the particular unselected word line. 126206.doc