JP4950299B2 - Reducing program disturb in non-volatile memory using multiple boost modes - Google Patents

Description

  The present invention relates to a nonvolatile memory.

  Semiconductor memories are becoming more commonly used in various electronic devices. For example, non-volatile semiconductor memory is used in cell phones, digital cameras, personal digital assistants, mobile computers, non-mobile computers and other devices. Electrically erasable programmable read only memory (EEPROM) and flash memory are one of the most popular non-volatile semiconductor memories. Using flash memory, a type of EEPROM, the contents of the entire memory array, or a portion of the contents of the memory, can be erased in one step as opposed to a conventional full-function EEPROM.

Both conventional EEPROM and flash memory utilize a floating gate that is disposed over a channel region in a semiconductor substrate and insulated from the channel region. The floating gate is disposed between the source region and the drain region. The control gate is disposed on the floating gate and is insulated from the floating gate. The threshold voltage (V _TH ) of the transistor formed in this way is controlled by the amount of charge held on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before turning on the transistor to allow conduction between its source and drain is controlled by the charge level on the floating gate.

  Since some EEPROM and flash memory devices have floating gates that are used to store two ranges of charge, the storage device can be programmed / erased between two states, for example, an erase state and a program state. Such a flash memory device is sometimes called a binary flash memory device because each storage device can store 1 bit of data.

  A multi-state (also called multi-level) flash memory device is implemented by identifying a plurality of distinct allowed / valid program threshold voltage ranges. Each threshold voltage range corresponds to a predetermined value of a set of data bits encoded in the memory element. For example, each storage element can store 2 bits of data when the element can be stored in one of four isolated charge bands corresponding to four threshold voltage ranges.

Normally, the program voltage _VPGM applied to the control gate during a program operation is applied as a series of pulses that increase over time. In one possible approach, the pulse magnitude is increased with each successive pulse by a predetermined step size, such as 0.2 to 0.4V. _VPGM can be applied to the control gate of the flash memory device. In a period between program pulses, a verification operation is performed. That is, the programming level of each element in the group of elements that are programmed in parallel is read between successive programming pulses to determine whether the element is greater than or equal to the verification level at which it is programmed. In the case of an array of multi-state flash memory elements, a verification step may be performed for each state of the element to determine whether the element has reached a verification level for its data. For example, a multi-state storage element that can store data in four states needs to perform verification operations on three comparison points.

Further, when programming a flash memory device, such as an EEPROM or NAND string NAND flash memory device, typically _VPGM is applied to the control gate, the bit line is grounded, and the cell or memory device (eg, storage device, etc.) Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the storage element rises so that the storage element is considered to be in the programmed state. Details of such programming are described in US Pat. No. 6,859,397 “Source Side Self Boosting Technique For Non-Volatile Memory” and US Patent Publication No. 2005/0024939 published on Feb. 3, 2005. Detecting Over Programmed Memory, both applications are hereby incorporated by reference in their entirety.

  However, because of the proximity of the non-volatile storage elements, various forms of program disturb occur during programming. Furthermore, this problem is expected to worsen as NAND technology is further scaled. Program disturb occurs when the threshold voltage of an unselected non-volatile storage element shifts due to programming of other non-volatile storage elements. Various program disturb mechanisms limit the operating window that can be used for non-volatile storage devices such as NAND flash memory. The boost approach connects this channel region of a NAND string that includes storage elements that are programmed to a low potential, such as 0V, while boosting the channel region of the NAND string that is prevented from being programmed to a high potential. Try to deal with the problem. However, existing boost modes cannot adequately handle multiple failure mechanisms.

  The present invention addresses these and other problems by providing a method of operating a non-volatile storage device that reduces program disturb.

  In one embodiment, a method of operating a non-volatile storage device includes programming a storage element in a set of non-volatile storage elements, wherein the set of non-volatile storage elements includes a plurality of word lines. And the storage element communicates with the selected word line. The method applies a first set of voltages to unselected word lines during the programming step and applies a first set of voltages to unselected word lines based on boost mode switching criteria. And further switching from applying to a second set of voltages. The first set of voltages is at least partially different from the second set of voltages. For example, the programming step may include applying a pulse train to a selected word line, in which case the boost mode switching criterion is when a program pulse of a specific amplitude in the pulse train is applied to the selected word line. Alternatively, it is triggered when a certain number of program pulses in the pulse train are applied to the selected word line.

  In another embodiment, a method of operating a non-volatile storage device implements a first boost mode during a first programming phase in which programming of a storage element in a set of non-volatile storage elements occurs, Performing a second boost mode during a second programming phase in which programming continues. The threshold voltage of the storage element is increased from the first level to the second level during the first programming phase and from the second level to the third level during the second programming phase. Further, the first programming stage may include a first pass of a multi-pass programming technique, and the second programming stage may include a second pass of a multi-pass programming technique.

  In one approach, in a first programming phase, a first subset of pulses in the pulse train is applied to the storage elements, and in a second programming phase, a second subset of pulses in the pulse train is applied to the storage elements. The

  In another approach, a first pulse train is applied to the storage element in a first programming phase, and a second pulse train is applied to the storage element in a second programming phase.

  In another embodiment, a method of operating a non-volatile storage device includes programming a storage element in a set of non-volatile storage elements, where the set of non-volatile storage elements includes a plurality of word lines. Communicate with. The programming step includes applying a pulse train to a selected word line in communication with the storage element. The method implements a first boost mode for unselected non-volatile storage elements when a first subset of program pulses in the pulse train is applied to a selected word line, and the program pulses in the pulse train Switching to the selected boosted word line includes performing a switch from the first boost mode to the second boost mode for the non-selected non-volatile storage elements.

  A set of non-volatile storage elements may be present in a number of NAND strings, and the number of NAND strings may have a selected NAND string in which the storage elements are present. In this case, the first boost mode and the second boost mode boost the channel of the unselected NAND string. Further, in one approach, the first boost mode boosts the channel without separating the portion of the NAND string source side channel from the portion of the NAND string drain side channel, and the second boost mode A part of the channel on the source side of the NAND string may be separated from a part of the channel on the drain side of the NAND string.

The top view of a NAND string. FIG. 2 is an equivalent circuit diagram of the NAND string of FIG. 1. 1 is a block diagram of an array of NAND flash storage elements. FIG. The conceptual diagram which shows the boost mode determination process. Fig. 4 illustrates the process of switching boost mode during programming. Fig. 4 shows a self-boost mode realized via a plurality of word lines. Fig. 4 shows a local self-boost mode realized via a plurality of word lines. Fig. 5 shows an erase region self-boost mode realized via a plurality of word lines. The first modified erase region self-boost mode realized via a plurality of word lines is shown. FIG. 10 shows a second modified erase region self-boost mode realized via a plurality of word lines. FIG. FIG. 10 shows a third modified erase region self-boost mode realized via a plurality of word lines. FIG. FIG. 10 shows a fourth modified erase region self-boost mode realized via a plurality of word lines. FIG. FIG. 10 shows a fifth modified erase region self-boost mode realized via a plurality of word lines. FIG. FIG. 6 shows a timeline illustrating how to achieve coarse / fine programming by setting the bit line inhibit voltage. FIG. 6 is a cross-sectional view of an unselected NAND string showing a programming area and an erasing area. 1 is a block diagram of an array of NAND flash storage elements. FIG. 1 is a block diagram of a non-volatile memory system that uses a single row / column decoder and read / write circuitry. FIG. 1 is a block diagram of a non-volatile memory system that uses dual row / column decoders and read / write circuits. FIG. The block diagram which shows one Embodiment of a detection block. An example of the organization of a memory array into blocks for all bit line memory architectures or odd-even memory architectures is shown. An example of a set of threshold voltage distributions is shown. An example of a set of threshold voltage distributions is shown. Various threshold voltage distributions are shown and a process for programming non-volatile memory is described. Various threshold voltage distributions are shown and a process for programming non-volatile memory is described. Various threshold voltage distributions are shown and a process for programming non-volatile memory is described. Figure 2 illustrates a coarse / fine programming process. 6 is a flowchart describing one embodiment of a process for programming non-volatile memory. An example of a pulse train applied to a control gate of a nonvolatile memory element during programming and boost mode switching that occurs during the pulse train are shown. 2 shows an example of a pulse train applied to a control gate of a nonvolatile memory element during programming, and boost mode switching that occurs between the pulse trains.

  The present invention provides a non-volatile storage system and method that reduces program disturb.

  One example of a memory system suitable for implementing the present invention uses a NAND flash memory structure. The NAND flash memory structure includes a plurality of transistors connected directly between two select gates. The transistors and select gates connected in series are called NAND strings. FIG. 1 is a plan view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string shown in FIGS. 1 and 2 includes four transistors 100, 102, 104, and 106 that are sandwiched between a first selection gate 120 and a second selection gate 122 and connected in series. Select gate 120 gates the NAND string connection of bit line 126. Select gate 122 gates the connection of the NAND string to source line 128. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 has a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3 (or the word line WL3), the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. In one embodiment, transistors 100, 102, 104, and 106 are each storage elements and are also referred to as memory cells. In other embodiments, the storage element may comprise a plurality of transistors or may be different from that shown in FIG. 1 or FIG. The selection gate 120 is connected to the selection line SGD. The selection gate 122 is connected to the selection line SGS.

  FIG. 3 is a circuit diagram depicting three NAND strings. A typical architecture of a flash memory system that uses a NAND structure includes several NAND strings. For example, three NAND strings, 320, 340, and 360 are shown in a memory array having more NAND strings. Each NAND string has two select gates and four storage elements. Although four storage elements are depicted for simplicity, modern NAND strings may have up to 32 or 64 storage elements, for example.

  For example, the NAND string 320 includes selection gates 322 and 327 and storage elements 323 to 326, the NAND string 340 includes selection gates 342 and 347 and storage elements 343 to 346, and the NAND string 360 includes selection gates 362 and 367. The memory elements 363 to 366 are included. Each NAND string is connected to the source line by its select gate (eg, select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. The various NAND strings 320, 340 and 360 are connected to each bit line 321, 341 and 361 by a select transistor such as select gates 322, 342 and 362. These selection transistors are controlled by a drain selection line SGD. In other embodiments, the select line need not be common between NAND strings. That is, different select lines can be connected to different NAND strings. Word line WL3 is connected to a control gate for storage elements 323, 343 and 363. Word line WL2 is connected to a control gate for storage elements 324, 344 and 364. Word line WL1 is connected to a control gate for storage elements 325, 345, and 365. Word line WL0 is connected to a control gate for storage elements 326, 346, and 366. That is, each bit line and each NAND string includes a column of an array or set of storage elements. The word lines (WL3, WL2, WL1 and WL0) include an array or set of rows. Each word line connects the control gates of each storage element in a row. Alternatively, the control gate may be provided by the word line itself. For example, word line WL2 provides a control gate for storage elements 324, 344, and 364. In practice, there may be thousands of storage elements per word line.

Each storage element can store data. For example, when storing 1-bit digital data, the possible threshold voltage (V _TH ) range of the storage element is divided into two ranges assigned to local data “1” and “0”. In one example of a NAND type flash memory, V _TH becomes negative after the storage element is erased and is defined as a logic “1”. V _TH after the program operation is positive and is defined as logic “0”. If V _TH is negative and a read is attempted, the storage element is turned on indicating that a logic “1” is stored. If V _TH is positive and a read operation is attempted, the storage element does not turn on, indicating that a logic “0” is stored. The storage element can also store information at a plurality of levels such as digital data of a plurality of bits. In this case, the range of _VTH values is divided into the number of data levels. For example, if four levels of information are stored, there are four V _TH ranges assigned to data values “11”, “10”, “01”, and “00”. In an example of a NAND type memory, V _TH after the erase operation is negative and is defined as “11”. Positive _VTH values are used for the "10", "01" and "00" states. The specific relationship between the data programmed into the storage element and the threshold voltage range of the element depends on the data encoding scheme employed for the storage element. For example, US Pat. No. 6,222,762 and US Patent Application Publication No. 2004/0255090, which are incorporated herein by reference in their entirety, describe various data codes for multi-state flash storage elements. Explains the conversion method.

  Relevant examples of NAND type flash memory and its operation are described in US Pat. Nos. 5,386,422, 5,522,580, 5, respectively, each incorporated herein by reference. 570,315, 5,774,397, 6,046,935, 6,456,528, and 6,522,580.

When programming a flash storage element, a program voltage is applied to the control gate of the storage element and the bit line associated with the storage element is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged, V _TH of the storage element is raised. In order to apply a program voltage to the control gate of the storage element being programmed, the program voltage is applied on the appropriate word line. As described above, one storage element in each NAND string shares the same word line. For example, when programming the storage element 324 of FIG. 3, the program voltage is also applied to the control gates of the storage elements 344 and 364.

However, while other NAND strings are being programmed, program disturb may occur in the prohibited NAND strings, and in some cases may occur in the NAND string itself being programmed. For example, NAND string 320 is prohibited (eg, the NAND string is an unselected NAND string that does not include the currently programmed storage element) and NAND string 340 is being programmed (eg, the NAND string is currently In the case of a select NAND string that includes a storage element being programmed, program disturb may occur in the NAND string 320. For example, if the pass voltage V _PASS is low, the channel of the forbidden NAND string may not be sufficiently boosted and the selected word line of the unselected NAND string may be programmed unintentionally. In another possible case, the boosted voltage may be pulled down by gate induced drain leakage (GIDL) or other leakage mechanisms, causing the same problem. Other effects include problems such as a shift in charge stored in programmed storage elements for capacitive coupling between the storage elements.

  FIG. 4 is a conceptual diagram illustrating a boost mode determination process. As first mentioned, program disturb remains an important problem in non-volatile storage systems. Program disturb occurs when the threshold voltage of an unselected non-volatile storage element is shifted to program other non-volatile storage elements. Program disturb can occur with previously programmed storage elements as well as erased storage elements that have not yet been programmed. Various program disturb mechanisms limit the usable operating window for non-volatile storage devices such as NAND flash memory. For example, the boost technique addresses this problem by connecting the channel region of a NAND string that includes storage elements that are programmed to a low potential, such as 0V, while boosting the channel region of the prohibited NAND string to a high potential. try to. However, existing boost modes cannot optimally deal with multiple failure mechanisms. That is, existing boost modes can effectively deal with certain program disturb failure mechanisms, but may not be effective against other failure mechanisms. Typically, boost mode compromises or optimizations are made to give the best operating window. Here we propose to use various boost modes during programming in order to optimize the boost more appropriately. For example, in one approach, one boost mode is used during initial programming and a second boost mode is used at the end of single page or wordline programming to improve overall margin for program disturb. To do.

  Various criteria can be used to determine which boost mode to use and when to switch from one boost mode to another. As an example, three different boost modes, indicated by blocks 400, 405, and 410, can be selected in the boost mode determination process (block 415). The boost mode includes, for example, self-boost (SB), local self-boost (LSB), erase area self-boost (EASB), and corrected erase area self-boost (REASB), as will be described later. Once the determination is made, the second boost mode is applied (block 420), for example, by applying a set of voltages to unselected word lines corresponding to the selected boost mode. The boost mode switching decision process (block 415) may use, for example, one or more boost mode switching criteria (block 425). These criteria are: program pulse number (block 430), program pulse amplitude (block 435), program pass number (block 440), selected word line position (block 445), coarse / fine programming mode status (block 450), It may include whether the storage element reaches a programmed state (block 455) and the number of program cycles experienced by the memory element (block 460).

  The program pass number may indicate, for example, whether a first pass of a multi-pass programming process is in progress or a second pass is in progress. The criteria for whether or not a storage element reaches a programmed state, for example, detects when a first storage element or part of a storage element in a storage element group such as a block or an array reaches a verification state Is realized. Switching to another boost mode may occur when the verification state is reached. The criteria for the number of program cycles experienced by the memory element can be realized, for example, by tracking the number of program cycles and adjusting the switch point based on that. Because storage elements tend to program faster as they experience additional programming cycles, for example, if a switching point occurs during a pulse train, the switching point is after the memory element has experienced a relatively large number of cycles. It may occur relatively early in the pulse train. The boost mode switching criteria will be described in detail later.

  FIG. 5 shows the process of switching boost mode during programming. The conceptual diagram described above can be further understood from the viewpoint of a flowchart. Programming begins at step 500 and a first boost mode is applied at step 510. In decision step 520, when the switching criteria are met, switching to the second boost mode is performed (step 530) and continues until programming is complete (step 550) (step 540). If the switching criteria are not met at decision step 520, the first boost mode continues to be applied and programming continues (step 525). In general, boost mode is achieved by configuring one or more control circuits of a memory element to apply an appropriate voltage to a word line that is in communication with a set of storage elements.

The decision to switch boost mode may be based on many factors. In general, it is desirable to implement a boost mode that is optimal for the current programming scheme and the current state of the storage elements and NAND strings. For example, a non-EASB boost mode, such as SB or LSB, is relatively effective with respect to the initial program pulse when V _PGM is low, and an EASB boost mode including REASB has a higher program pulse when V _PGM is high. It may be relatively effective. In this case, switching from the non-EASB mode to the EASB mode _can be performed based on the amplitude of _{V PGM.} Further, the failure mode may react to many program pulses in addition to the program pulse amplitude. In this case, switching from the non-EASB mode to the EASB mode can be performed (often correlates with V _PGM instead) based on the number of program pulses. Furthermore, certain boost modes may be further advantageous based on the position of the selected word line among other word lines. In general, depending on the characteristics of a given non-volatile storage device, the operating window can be defined using multiple boost modes with a sufficiently low failure rate.

  FIG. 6 shows a self-boost mode realized via a plurality of word lines. As mentioned, various types of boost modes have been developed to combat program disturb. During programming of the storage elements on the selected word line, the boost mode is achieved by applying a set of voltages to unselected word lines that are in communication with storage elements that are not currently programmed. The storage element being programmed is associated with the selected NAND string, while the other storage elements are associated with the unselected NAND string. In general, program disturb is related to storage elements of unselected NAND strings, but may occur for other storage elements in the same NAND string.

In one approach, the self-boost mode is indicated by an exemplary word line 600 that communicates with a set of storage elements arranged in a NAND string. In this example, eight word lines (eg, control lines labeled WL0 to WL7), one source side select gate control line labeled SGS, and one drain side labeled SGD. There is a select gate control line. A set of voltages applied to the control line is also shown. WL4 is shown as a word line selected as an example. Typically, programming proceeds one word line at a time from the source side to the drain side of the NAND string. The applied voltage includes V _SGS applied to the source side select gate control line SGS, pass voltage V _PASS applied to each of the unselected word lines WL0 to WL3 and WL5 to WL7, and applied to the selected word line WL4. And a program voltage V _PGM to be applied, and V _SGD applied via the drain side select gate control line SGD. Normally, V _SGS is 0V so that the source side select gate is turned off. Since corresponding low bit line voltage _{V BL} such 0~1V is applied, as the drain-side select gate for the selected NAND string are turned _{on, V SGD} is about 2.5V. Since the high _{V GL} is applied from a corresponding such 1.5～3V, the drain side select gate for the unselected NAND strings are turned off.

_{Further, V PASS} is about _{7~10V, V PGM} may change from about 12～20V. In one programming scheme, a pulse train of program voltages is applied to the selected word line. See also FIG. 23 and FIG. The amplitude of each continuous program pulse in the pulse train usually increases stepwise by about 0.3 to 0.5 V per pulse. Further, verification pulses are applied between program pulses to verify whether the selected storage element has reached the target programming state. Note also that each program pulse may have a fixed amplitude or may have a varying amplitude. For example, some programming schemes apply pulses with amplitudes that vary in a slope or step. Any type of program pulse can be used.

  If the programmed word line is WL4 and programming proceeds from the source side to the drain side of each NAND string, the storage elements WL0 to WL3 are already programmed and the storage elements WL5 to WL7 are , WL4 is erased when it is programmed. The pass voltage on the unselected word lines couples to the channel associated with the unselected NAND string and generates a voltage in the channel that tends to reduce program disturb by lowering the voltage across the tunnel oxide of the storage element Let

FIG. 7 shows a local self-boost (LSB) mode implemented via multiple word lines. In one approach, the local self-boost mode is illustrated by the example word line 700 communicating with a set of storage elements arranged in a NAND string. Local self-boost is different from the self-boost mode of FIG. 6 in that the word line adjacent to the selected word line receives the isolation voltage V _ISO , which is another voltage close to 0V or close to 0V rather than V _PASS . Different. The remaining unselected word lines are at _VPASS . Local self-boost attempts to reduce program disturb by separating the already programmed storage element channel from the prohibited storage element channel. The LSB mode is effective when V _PGM is low, but the disadvantage of the LSB mode is that because V _PGM is isolated from other channel regions below the unselected word lines, part of the channel is isolated. When high, the boosted channel voltage below the selected word line can be very high. Therefore, the boost voltage is mainly determined by the high programming voltage _VPGM . Due to the high boost, inter-band tunneling or gate induced drain leakage (GIDL) near the word line biased to 0V may occur. The amount of channel boost can be limited to a lower value by using erase region self-boost (EASB) mode or modified EASB (REASB) mode, as described below.

FIG. 8 shows an erase region self-boost mode realized via a plurality of word lines. In one approach, the EASB mode is illustrated by an exemplary word line 800 that communicates with a set of storage elements arranged in a NAND string. In EASB, there is an exception that only the source side adjacent word line WL3 is set as the isolation voltage, that is, V _ISO = 0V and the boosted channel on the source side and drain side of the unselected NAND string is isolated. , Similar to LSB. The channel region on the drain side of the memory element is selected and the channel region below the selected word line is connected, the channel boosting is determined mainly by the applied V _PASS to unselected word lines instead of V _PGM (See also FIG. 13). The drain side adjacent word line WL5 is at _VPASS . If _VPASS is too low, boosting in the channel is not sufficient to prevent program disturb. However, if V _PASS is too high, the unselected word line of the selected NAND string (of 0V on the bit line) may be programmed or program disturb due to GIDL may occur.

FIG. 9 shows a first modified erase region self-boost mode implemented via a plurality of word lines. In one approach, the first REASB mode is illustrated by an exemplary word line 900 that communicates with a set of storage elements arranged in a NAND string. REASB is similar to EASB, but a small isolation voltage V _ISO such as 2.5V is applied to an adjacent isolation word line such as WL3.

FIG. 10 shows a second modified erase region self-boost mode implemented via a plurality of word lines. In one approach, the second REASB mode is illustrated by the example word line 1000 communicating with a set of storage elements arranged in a NAND string. In this case, V _ISO is applied to a plurality of word lines such as WL2 and WL3 on the source side of the selected word line WL4. The same V _ISO value or different V _ISO values can be used. For example, V _ISO may gradually decrease, such as 4V at WL3 and 2.5V at WL2. A variety of other techniques can also be used. For example, if V _ISO is applied to three adjacent word lines (eg, WL1-WL3), the last word line (WL1) receives the lowest V _ISO and WL2 and WL3 are common V _ISO. You may receive.

FIG. 11a shows a third modified erase region self-boost mode implemented via a plurality of word lines. In one scheme, a third REASB mode is indicated by an example word line 1100 that communicates with a set of storage elements arranged in a NAND string. In this case, when _VPGM has a relatively low value, a relatively low passing voltage represented by VPGM _-LOW is applied to one or both word lines (for example, WL0 and WL7), while the other A general high V _pass is applied to the unselected word lines. For example, when V _PGM changes from 12 to 20V, V _PGM-LOW represents a range of 12 to 16V. This boost mode can deal with program disturb mechanisms that affect the end word lines. Specifically, when the same value of V _PASS is applied to all of the unselected word lines including the end word line, the electron injection into the storage element associated with the end word line is slow, Leakage, i.e. GIDL, may occur on the selection gate. The boost mode shown can address this problem.

Further, when V _PGM is in a higher range represented by V _PGM-HIGH , such as in the range of 16-20V, for example, as shown in FIG. _{It is} raised again to the level of another unselected word line such as _PASS . Alternatively, pass voltage of the end word _lines, but less than _{V PASS} pulled _{V PASS-LOW} higher intermediate level _{V PASS-INT.}

FIG. 11b shows a fourth modified erase region self-boost mode implemented via a plurality of word lines. In one approach, the fourth REASB mode is indicated by an example word line 1150 communicating with a set of storage elements arranged in a NAND string. Here, another when in a range of high _{value V PGM} on the word line WL4 selected is represented by _{V PGM-HIGH,} the pass voltage on the end word lines WL0, WL7, for example _{V PASS} etc. It is raised again to the level of the unselected word line.

  Furthermore, another boost mode may be implemented based on the position of the selected word line. For example, when boost mode switching occurs during a pulse train, the switching may occur at a position in the pulse train that is based on a relative position on a selected word line. In one approach, when the position of the selected word line is relatively close to the drain side of the unselected NAND string, switching from SB or LSB to EASB or REASB occurs relatively late in the pulse train.

FIG. 11c shows a fifth modified erase region self-boost mode implemented via multiple word lines. In one approach, the fifth REASB mode is indicated by an exemplary word line 1170 communicating with a set of storage elements arranged in a NAND string. This boost mode is similar to the boost mode of FIG. 11a, but when V _PGM is within the low range represented by V _PGM-LOW , the low V _PASS represented by V _PASS-LOW is not selected. Used for each of the word lines. When V _PGM reaches high range represented by _{V PGM-HIGH,} there is a case where the boost mode of Figure 11b after this mode continues. A variety of other combinations may be used. For example, regardless of _VPGM , V _PASS for unselected word lines other than the end word lines may be higher than V _PASS for the end word lines. In addition, there may be more than one range of _VPGM that triggers a boost mode change.

FIG. 12 shows a timeline showing how coarse / fine programming is achieved by setting the bitline inhibit voltage. As mentioned, boost mode switching may be performed based on the coarse / fine programming state. Coarse / fine programming allows the threshold voltage (V _TH ) of the storage element to rise to a desired level quickly during the first coarse programming and slower during the next fine programming. . For this purpose, a low verification level V _L and a high verification level V _H are respectively used for a given programming state. In particular, coarse programming occurs when the voltage threshold is below V _L, fine programming occurs when the voltage threshold is between V _L and V _H. Coarse / fine programming provides a tight voltage distribution to the programmed memory element. See also FIG. 21d.

Curve 1200 shows the change in V _TH of the storage element over time, and curve 1250 shows the bit line voltage (V _BL ) applied to the bit line associated with the storage element. Programming of the storage element is capable to slow by providing a bit line inhibit voltage _{V PARTIAL INHIBIT, V PARTIAL INHIBIT} cancels the effect of the applied programming voltage pulses. When V _TH exceeds V _H , V _{FULL INHIBIT} is applied to the bit line to transition the storage element to an inhibit mode that is locked out of additional programming and verification. Different _VL and _VH values can be associated with different states of the multi-state storage element, such as states A, B, and C, to allow different states of coarse / fine programming. The forbidden voltage slows down programming, which allows precise control of the programmed voltage threshold level. In one approach, V _{PARTIAL INHIBIT} , typically 0.5-1.0 V, reduces the electric field in the oxide and is passed to the NAND string during programming. This requires that the select gate voltage be high enough to pass this voltage (usually 2.5V). In addition, step sizes that are reduced with a _VPGM pulse train can also be used to provide a fine programming mode. This can be done with or without the forbidden voltage on the bit line.

Thus, one approach is to program coarse / fine programming by switching from coarse programming mode to fine programming mode when it is determined that several storage elements (eg, one or more) have reached a lower verification level. It can be used when a single pulse train of pulses is applied to a selected word line. Furthermore, coarse / fine programming can be used in a multi-pass programming scheme. In the multi-pass programming scheme, the storage element is programmed to an intermediate program state close to the final program state in the first pass using coarse programming, and the storage element is moved from the intermediate program state in the second pass using fine programming. Programmed to final program state. Multi-pass programming can utilize various ranges of _VPGM . For _example, the range of _{V PGM,} in the first pass coarse programming is used narrowed in example 12～20V, in the second pass fine programming is used can be 14～20V.

FIG. 13 shows a cross-sectional view of an unselected NAND string, and shows a program area and an erase area by EASB as shown in FIG. 8 or REASB as shown in FIG. The diagram is simplified and not to scale. The NAND string 1300 includes a source-side selection gate 1306, a drain-side selection gate 1324, and eight storage elements 1308, 1310, 1312, 1314, 1316, 1318, 1320, and 1322 formed on the substrate 1390. is doing. The component can be formed on the n-well region on the p-well region of the substrate. In addition to a bit line 1326 having a potential of Vdd (bit line), a source supply line 1304 having a potential of V _SOURCE is provided. During programming, V _PGM is applied to the selected word line, in this case applied to WL4 associated with storage element 1316. Furthermore, the control gate of the storage element may be provided as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6 and WL7 may extend through the control gates of storage elements 1308, 1310, 1312, 1314, 1316, 1318, 1320 and 1322, respectively. V _ISO is applied to the source-side word line of the selected word line (WL3 called an isolation word line). V _PASS is applied to the remaining word lines associated with NAND string 1300. V _SGS is applied to select gate 1306 and V _SGD is applied to select gate 1324.

  Assuming that programming of storage elements along NAND string 1300 proceeds from storage element 1308 to storage element 1322, storage elements 1308 to 1314 are stored when the storage element associated with WL4 is being programmed in other NAND strings. Has already been programmed and storage elements 1318 to 1322 have not yet been programmed. Note that storage element 1316 is not programmed when NAND string 1300 is disabled. Accordingly, all or some of the storage elements 1308-1314 have electrons that are programmed and held in the floating gates of the storage elements, and the storage elements 1318-1322 are erased or partially depending on the programming mode. Can be programmed automatically. For example, storage elements 1318-1322 may have been previously programmed with the first step of a two-step programming technique.

Furthermore, when using the EASB boost mode or the REASB boost mode, a sufficiently low isolation voltage V _ISO is applied to the adjacent word line on the source side of the selected word line and erased with the programmed channel region in the substrate. Separate channel regions. That is, a portion of the source-side or programming-side substrate channel (eg, region 1350) of the unselected NAND string is a portion of the unselected NAND string drain side or non-programmed channel (eg, region). 1360). Channel region 1350 is boosted by applying V _PASS to WL0-WL2, while channel region 1360 is boosted by applying V _PGM to WL4 and V _PASS to WL5-WL7. Because V _PGM is dominant, erase region 1360 experiences a relatively higher boost than programmed region 1350.

  FIG. 14 shows an example of an array 1400 of NAND storage elements as shown in FIGS. Along each column, the bit line 1406 is connected to the drain terminal 1426 of the drain select gate of the NAND string 1450. Along each row of NAND strings, source line 1404 can be connected to all source terminals 1428 of the NAND string source select gates. An example of a NAND architecture array and its operation as part of a memory system is described in US Pat. Nos. 5,570,315, 5,774,397, and 6,046,935.

  The array of storage elements is divided into a number of blocks of storage elements. As is common in flash EEPROM systems, a block is an erase unit. That is, each block has a minimum number of storage elements that are erased together. Each block is generally divided into a plurality of pages. A page is a unit of programming. In one embodiment, individual pages are divided into segments, which can have a minimum number of storage elements that are written at one time as a basic programming operation. Generally, data of one page or more is stored in one row of the storage element. A page can store one or more sectors. One sector has user data and overhead data. Overhead data typically has an error correction code (ECC) calculated from the user data for that sector. Some of the controls (discussed below) calculate an ECC when data is programmed into the array and check it as data is read from the array. Also, ECC and / or other overhead data is stored on different pages or even different blocks other than the user data with which they are associated.

  The sector of user data is generally 512 bytes and corresponds to the size of the sector in the magnetic disk drive. Overhead data is typically an additional 16-20 bytes. Multiple pages make up a block, which can be any of 8 pages up to, for example, 32, 64, 128 or more. In some embodiments, a string of NAND strings includes blocks.

  In one embodiment, the memory storage element has a word line of a selected block while the p-well is raised to an erase voltage (eg, 20V) for a sufficient period of time and the source and bit lines are floating. Is erased by grounding. Due to capacitive coupling, the unselected word lines, bit lines, selected lines, and c-source are also raised to a significant portion of the erase voltage. Accordingly, a strong electric field is applied to the tunnel oxide layer of the selected storage element, and the data of the selected storage element is erased as electrons of the floating gate are emitted to the substrate side by the Fowler-Nordheim tunneling mechanism. As electrons are transferred from the floating gate to the p-well region, the threshold voltage of the selected storage element is lowered. Erasing can be performed on the entire memory array, individual blocks, or other units of storage elements.

  FIG. 15 is a block diagram of a non-volatile memory system using a single row / column decoder and read / write circuit. The figure shows a memory element 1596 having read / write circuitry for simultaneously reading and programming a page of storage elements in accordance with one embodiment of the present invention. Memory device 1596 includes one or more memory dies 1598. The memory die 1598 includes a two-dimensional array of storage elements 1400, a control circuit 1510, and a read / write circuit 1565. In some embodiments, the array of storage elements can be three dimensional. The memory array 1400 can be addressed by word lines via row decoder 1530 and by bit lines via column decoder 1560. The read / write circuit 1565 includes a plurality of detection blocks 1500 and can read or program one page of storage elements in parallel. In general, the controller 1550 is included in the same memory device 1596 (eg, a removable storage card) as one or more memory dies 1598. Commands and data are sent between the host and controller 1550 via line 1520 and between the controller and one or more memory dies 1598 via line 1518.

  The control circuit 1510 executes a memory operation on the memory array 1400 in cooperation with the read / write circuit 1565. The control circuit 1510 includes a state machine 1512, an on-chip address decoding unit 1514, and a power control module 1516. The state machine 1512 provides chip level control of memory operations. The on-chip address decoder 1514 is used by the host or memory controller and provides an address interface between the hardware addresses used by the decoders 1530 and 1560. The power control module 1516 controls the power and voltage supplied to the word lines and bit lines during memory operation.

  In some implementations, some of the components of FIG. 15 can be combined. In various designs, one or more of the components other than the storage element array 1400 may be considered (single or combined) as a single management circuit. For example, the one or more management circuits include one or a combination of a control circuit 1510, a state machine 1512, a decoding unit 1514/1560, a power control 1516, a detection block 1500, a read / write circuit 1565, a control unit 1550, and the like. May be included.

  FIG. 16 is a block diagram of a non-volatile memory system using a double row / column decoder and a read / write circuit. Here, another arrangement of the memory elements 1596 illustrated in FIG. 15 is shown. Access to the memory array 1400 by various peripheral circuits is implemented in a symmetric fashion on both sides of the array, so that the density of access lines and circuitry on each side is reduced by half. Therefore, the row decoding unit is divided into row decoding units 1530A and 1530B, and the column decoding unit is divided into column decoding units 1560A and 1560B. Similarly, the read / write circuit is divided into a read / write circuit 1565A connected to the bit line from the bottom of the array 1400 and a read / write circuit 1565B connected to the bit line from the top of the array 1400. By this method, the density of the read / write module is essentially reduced by a factor of two. The apparatus of FIG. 16 can also have a control unit as described above for the apparatus of FIG.

  FIG. 17 is a block diagram illustrating an embodiment of a detection block. Each detection block 1500 is divided into a core part called a detection module 1580 and a common part 1590. In one embodiment, there may be a separate detection module 1580 for each bit line and one common portion 1590 of the set of multiple detection modules 1580. In one example, the detection block may have one common part 1590 and eight detection modules 1580. Each detection module in the group can communicate with an associated common part via a data bus 1572. For further details, see US Patent Application Publication No. 2006/0140007, “Non-Volatile Memory & Method with Shared Processing for an Aggregate on Sense Amplifiers”, published June 29, 2006. The entirety of which is incorporated herein by reference.

  The detection module 1580 includes a detection circuit 1570, which determines whether the conduction current in the connected bit line is higher or lower than a predetermined threshold level. The detection module 1580 further includes a bit line latch 1582, which is used to set a voltage condition on the connected bit line. For example, according to a predetermined state latched in the bit line latch 1582, the connected bit line is set to a state (for example, Vdd) designating program prohibition.

  The common unit 1590 includes a processor 1592, a set of data latches 1594, and an I / O interface 1596 that connects between the set of data latches 1594 and the data bus 1520. The processor 1592 performs the calculation. For example, one of its functions is to determine the data stored in the detected storage element and store the determined data in a set of data latches. A set of data latches 1594 is used to store data bits determined by the processor 1592 during a read operation. It is also used to store data bits captured from the data bus 1520 during program operations. The captured data bits represent the write data that is to be programmed into the memory. The I / O interface 1596 provides an interface between the data latch 1594 and the data bus 1520.

  During reading or detection, the operation of the system is under the control of state machine 1512, which controls the supply of different control gate voltages to the addressed storage element. In going through the various default control gate voltage steps corresponding to the various memory states supported by the memory, the detection module 1580 moves to one of these voltages and from the detection module 1580 to the processor 1592 via the bus 1572. Output is provided. At that point, the processor 1592 determines the memory state obtained by considering information about the detection module move event and the control gate voltage applied via the input line 1593 from the state machine. A binary encoding for the memory state is then calculated and the resulting data bits are stored in the data latch 1594. In another embodiment of the core portion, the bit line latch 1582 provides double duty as both a latch that latches the output of the detection module 1580 and a bit line latch as described above.

  Of course, some implementations may have multiple processors 1592. In one embodiment, each processor 1592 has an output line (not shown in FIG. 7), and each output line is wired-ORed together. In some embodiments, the output line is inverted before connecting to the wired OR line. A state machine that receives the wired OR can determine when all the bits being programmed reach the desired level. This configuration thus allows a quick decision during the program verification process as to when the programming process is complete. For example, as each bit reaches its desired level, a logical 0 for that bit is sent to the wired OR line (or invert data 1). When all bits output data 0 (or invert data 1), the state machine recognizes that it will finish the programming process. As each processor communicates with eight detection modules, the state machine needs to read the wired OR line eight times, or logic is added to the processor 1592 to accumulate the associated bit line results, and the state machine Read the wired OR line only once. Similarly, by choosing the logic level correctly, the global state machine can detect when the first bit changes its state and changes the algorithm accordingly.

  During programming or verification, the data to be programmed is stored from the data bus 1520 into a set of data latches 1594. A program operation under the control of the state machine has a series of programming voltage pulses applied to the control gate of the addressed storage element. Each programming pulse is followed by a readback (verification) to determine if the storage element has been programmed to the desired memory state. The processor 1592 monitors the readback memory state for the desired memory state. If the two match, the processor 1592 sets the bit line latch 1582 and sets the bit line to a state designating program prohibition. This prevents further storage elements connected to the bit line from being programmed even if a programming pulse appears at the control gate. In other embodiments, the processor first loads the bit line latch 1582 and the detection circuit sets it to a prohibited value during the verification process.

  The data latch stack 1594 has a stack of data latches corresponding to the detection module. In one embodiment, there are three data latches per detection module 1580. In some implementations (although not required), the data latch is implemented as a shift register that converts the internally stored parallel data to serial data on the data bus 1520 and vice versa. In the preferred embodiment, all data latches corresponding to the read / write blocks of m storage elements are linked together to form a block shift register so that a block of data can be input or output by serial transfer. In particular, even if the banks of r read / write modules are adjusted and the set of data latches are part of the overall shift register of the read / write block, each of the data latches of the set is in turn connected to the data bus. Allow data to be shifted in and out.

  Additional information on the structure and / or operation of various embodiments of non-volatile storage can be found in (1) US Patent Application Publication No. 2004/0057287, “Non-Volatile Memory And Method With Reduced Source Line Bias Errors”, published. March 25, 2004, (2) US Patent Application Publication No. 2004/0109357, “Non-Volatile Memory And Method with Improved Sensing”, Publication Date June 10, 2004, (3) US Patent Application No. 11 / 015, 199, “Improved Memory Sensing Circuit And Method For Low Voltage Operation”, filing date December 16, 2004, (4) US Patent Application No. 11 / 099,133, “Compensating for Coupling During Read Operations of Non-Volatile Memory ", filing date April 5, 2005, and (5) US Patent Application No. 11 / 321,953," Reference Sense Amplifier For Non-Volatile Memory ", filing Dated December 28, 2005. All five of these patent documents are incorporated herein by reference in their entirety.

  FIG. 18 shows an example of organizing a memory array into blocks for an all bit line memory architecture or for an odd-even memory architecture. An exemplary structure of the storage element array 1400 is described. As an example, a NAND flash EEPROM is described that is divided into 1024 blocks. Data stored in each block can be erased simultaneously. In one embodiment, a block is the smallest unit of storage elements that are simultaneously erased. In this example, each block has bit lines BL0, BL1,. . . There are 8,512 columns corresponding to BL8511. In one embodiment, referred to as an all bit line (ABL) architecture (architecture 1810), all bit lines of a block are selected simultaneously during read and program operations. Storage elements along a common word line and connected to any bit line are programmed simultaneously.

  In the example shown, a NAND string is formed by connecting four storage elements in series. Although four storage elements are shown included in each NAND string, more or less than four can be used (eg, 16, 32, 64, or another number). One terminal of the NAND string is connected to the corresponding bit line via a drain select gate (connected to the select gate drain line SGD), and another terminal (connected to select the gate source line SGS). ) Connected to the c-source via a source select gate.

  In another embodiment, referred to as an odd-even architecture (architecture 1800), the bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In an odd / even bit line architecture, storage elements that are along a common word line and connected to the odd bit line are programmed at a certain timing and are stored along the common word line and connected to the even bit line. Elements are programmed at different times. Data is simultaneously programmed into and read from the various blocks. In this example, each block has 8,512 columns that are divided into even and odd columns. In this example, a NAND string is formed by connecting four storage elements in series. Although four storage elements are shown as included in each NAND string, more or less than four storage elements can be used.

  During one configuration of read and programming operations, 4,256 storage elements are selected simultaneously. The selected storage element has the same word line and the same type of bit line (eg, even or odd). Therefore, 532 bytes of data forming one logical page can be read or programmed simultaneously, and one block of memory stores at least 8 logical pages (4 word lines with odd and even pages, respectively). it can. In the case of four multi-state storage elements, each storage element stores 2 bits of data, and if each of these 2 bits is stored on a separate page, one block stores 16 logical pages. Other sized blocks and pages can also be used.

In either the ABL architecture or the odd-even architecture, the storage element can be erased by raising the p-well to an erase voltage (eg, 20V) and grounding the word line of the selected block. The source line and bit line are floated. Erasing can be performed on the entire memory array, separate blocks, or another unit of storage elements that are part of a memory element. Electrons from the floating gates of the storage elements transferred into p- well region, V _TH of the storage elements becomes negative.

In read and verify operations, the select gates (SGD and SGS) are connected to a voltage in the range of 2.5-4.5V and WL0, when WL2 is the selected word line (eg WL2 WL1 and WL3) are raised to the read pass voltage V _READ (usually in the range of 4.5 to 6V), causing the transistors to operate as pass gates. The selected word line WL2 is connected to a voltage, and the level of that voltage is read to determine whether the _VTH of the associated storage element is above or below such level. And specified for each verification operation. For example, in a read operation for a two level storage element, the selected word line WL2 is grounded, whether V _TH is higher than 0V is detected. The validation operation of the two-level storage element, is connected to the selected word line WL2 for example 0.8V, V _TH is whether reaches at least 0.8V is verified. The source and p-well are at 0V. A selected bit line that is assumed to be an even bit line (BLe) is precharged to a level of, for example, 0.7V. If V _TH is higher than the read or verify level on the word line, the potential level of the bit line (BLe) associated with the target storage element is maintained at a high level for the non-conductive storage element. On the other hand, when V _TH is lower than the read level or the verification level, the conductive memory element discharges the bit line, so that the potential level of the target bit line (BLe) is set to a low level such as less than 0.5V. Decrease. Thereby, the state of the storage element is detected by the voltage comparator sense amplifier connected to the bit line.

  The erase operation, read operation, and verify operation described above are performed according to conventionally known techniques. Accordingly, many of the details described can be changed by one skilled in the art. Other conventionally known erase, read and verify techniques can also be used.

FIG. 19 shows an exemplary set of threshold voltage distributions. An exemplary _VTH distribution of the storage element array is provided for the case where each storage element stores 2 bits of data. A first threshold voltage distribution E is provided for erased storage elements. Three threshold voltage distributions, A, B, and C of the programmed storage element are also shown. In one embodiment, the threshold voltage for the E distribution is negative and the threshold voltages for the A, B, and C distributions are positive.

  Each threshold voltage range corresponds to a predetermined value of a set of data bits. The specific relationship between the data programmed into the storage element and the threshold voltage level of the storage element depends on the data encoding scheme employed for the storage element. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, both published herein on December 16, 2004, are incorporated herein by reference in their entirety. Various data encoding methods of the state flash memory device will be described. In one embodiment, if the threshold voltage of the floating gate is erroneously shifted to its neighboring physical state, the data value is assigned to the threshold voltage range using gray code assignment so that only one bit is affected. An example is “11” for the threshold voltage range E (state E), “10” for the threshold voltage range A (state A), “00” for the threshold voltage range B (state B), and the threshold voltage range C. “01” is assigned to (state C). However, in other embodiments, gray codes are not used. Although four states are shown, the present invention can also be used with other multi-state structures that include more or less than four states.

  Read reference voltages Vra, Vrb, and Vrc are provided for reading data from the storage element. By testing whether the threshold voltage of a given storage element is above or below Vra, Vrb and Vrc, the system can determine the state of the storage element, eg, the programming state.

  In addition, three verification reference voltages Vva, Vvb and Vvc are provided. When programming storage elements to state A, the system tests whether those storage elements have a threshold voltage greater than or equal to Vva. When programming the storage element to state B, the system tests whether the storage element has a threshold voltage greater than or equal to Vvb. When programming the storage element to state C, the system tests whether the storage element has a threshold voltage greater than or equal to Vvc.

  In one embodiment, known as full sequence programming, the storage element is programmed directly from the erase state E to any of the programming states A, B, or C. For example, the set may first be erased such that all storage elements in the set of programmed storage elements are in erased state E. Next, a series of programming pulses as shown in the control gate voltage sequence of FIG. 23 is used to program the storage element directly into state A, B or C. Some storage elements are programmed from state E to state A, and other storage elements are programmed from state E to state B and / or from state E to state C. When programming from state E to state C on WLn, the change in charge at the floating gate under WLn is compared to the change in voltage when programming state E to state A or state E to state B. The amount of parasitic coupling to the adjacent floating gate under WLn-1 is maximized. When programming from state E to state B, the amount of coupling to the adjacent floating gate is reduced but still large. When programming from state E to state A, the amount of coupling is even smaller. As a result, the correction amount required to read each state of WLn−1 later varies depending on the state of the adjacent storage element on WLn.

  FIG. 20 shows an example of a two-pass technique for programming a multi-state storage element that stores data for two different pages (a lower page and an upper page). Four states, state E (11), state A (10), state B (00), and state C (01) are shown. In state E, both pages store “1”. In the state A, the lower page stores “0” and the upper page stores “1”. In state B, both pages store “0”. In the state C, the lower page stores “1” and the upper page stores “0”. Note that although a specific bit pattern is assigned to each state, a different bit pattern can be assigned.

In the first programming path, the threshold voltage level of the storage element is set according to the bits programmed into the lower logical page. If the bit is a logic “1”, the threshold voltage is not changed because it is in the proper state as a result of being previously erased. However, if the bit being programmed is a logic “0”, the threshold level of the storage element is increased to state A as indicated by arrow 1100. This ends the first programming path.

  In the second programming path, the threshold voltage level of the storage element is set according to the bit programmed in the upper logical page. If the upper logical page bit stores a logic “1”, the storage element is in one of states E or A depending on the programming of the lower page bit, both of which are programmed because the upper page bit holds “1”. Does not occur. If the upper page bit is a logic “0”, the threshold voltage is shifted. If the memory element remains in the erased state E by the first path, the memory element is programmed in the second stage, and the threshold voltage is increased so as to be within state C as indicated by arrow 2020. If the storage element is programmed in state A as a result of the first programming path, the storage element is further programmed in the second path, increasing the threshold voltage to be in state B as indicated by arrow 2010. The result of the second path is to program the storage element to the state specified to store the logic “0” of the upper page without changing the data for the lower page. In both FIGS. 19 and 20, the amount of coupling to the floating gate on the adjacent word line depends on the final state.

  In one embodiment, if enough data is written to fill an entire page, the system is set to perform a full sequence write. If insufficient data has been written to all pages, the programming process can perform lower page programming with the received data. When the next data is received, the system programs the upper page. In yet another embodiment, if the system starts writing in a mode that programs the lower page and receives the next sufficient data to fill all (or most) of the word line storage elements, Convert to sequence programming mode. Further details of such an embodiment are disclosed in US Patent Application Publication No. 2006/0126390, “Pipelined Programming of Non-Volatile Memories Using Early Data”, published June 15, 2006. The entirety of which is incorporated herein by reference.

  21a-c reduce the effect of coupling between floating gates on a particular storage element by writing that particular storage element to a particular page after writing to the adjacent storage element of the previous page. Another method of programming non-volatile memory is disclosed. In one example of implementation, the non-volatile storage element stores two bits of data for each storage element using four data states. For example, assume that state E is an erased state and states A, B, and C are programmed states. State E stores data 11. The state A stores data 01. State B stores data 10. State C stores data 00. This is an example of non-Gray coding since both bits change between adjacent states A and B. Other encodings of the data into the physical data state can also be used. Each storage element stores two pages of data. For reference purposes, the data on these pages is called the upper page and the lower page, but other labels can be given. Referring to state A, the upper page stores bit 0 and the lower page stores bit 1. Referring to state B, the upper page stores bit 1 and the lower page stores bit 0. Referring to state C, both pages store bit data 0.

  The programming process is a two step process. In the first step, the lower page is programmed. If the lower page remains data 1, the storage element state remains in state E. If the data is programmed to 0, the threshold voltage of the storage element increases and the storage element is programmed to state B '. Thus, FIG. 21a shows the programming of the storage element from state E to state B '. State B 'is provisional state B, so the verification point is shown as Vvb' and is lower than Vvb.

  In one embodiment, after programming the storage element from state E to state B ', the adjacent storage element (WLn + 1) in the NAND string is programmed to its lower page. For example, reviewing FIG. 2, after programming the lower page for storage element 106, the lower page of storage element 104 is programmed. If the storage element 104 has a threshold voltage that has increased from state E to state B ′ after programming the storage element 104, the effect of the coupling between the floating gates increases the apparent threshold voltage of the storage element 106. This has the effect of expanding the threshold voltage distribution in state B 'as shown by the threshold voltage distribution 2150 in FIG. 21b. This apparent expansion of the threshold voltage distribution is corrected when programming the upper page.

  FIG. 21c shows the process of programming the upper page. If the storage element is in erased state E and the upper page remains at 1, the storage element remains in state E. If the storage element is in state E and its upper page data is programmed to 0, the threshold voltage of the storage element increases and the storage element goes to state A. If the storage element has an intermediate threshold voltage distribution 2150 and the upper page data remains at 1, the storage element is programmed to the final state B. When the storage element has an intermediate threshold voltage distribution 2150 and the upper page data becomes data 0, the threshold voltage of the storage element increases and the storage element enters state C. Since only the upper page programming of an adjacent storage element affects the apparent threshold voltage of a given storage element, the process shown in FIGS. 21a-c reduces the coupling effect between floating gates. Another example of state encoding is to move from distribution 2150 to state C when upper page data is 1, and to move to state B when upper page data is 0.

  Although FIGS. 21a-c provide an example for four data states and two page data, the disclosed concept is more or less than four states and other implementations with different pages than the two pages It can also be applied to forms.

FIG. 21d illustrates the coarse / fine programming process. As described above in connection with FIG. 12, the storage element is first moved quickly toward the target program state by the coarse mode, and then moved precisely and slowly by the target program state by the fine mode, To be programmed. The fine programming mode may include, for example, reducing the step size with a _VPGM pulse train and / or applying a forbidden voltage to the bit line of the selected NAND string. Further, in coarse / fine programming, one-pass programming or multi-pass programming may be performed. In one-pass coarse / fine programming, as shown in FIG. 23, switching from coarse programming to fine programming is performed in the _VPGM pulse train. In contrast, in multi-pass coarse / fine programming, for example, coarse programming is used during the first pass and fine programming is used during the second pass. The switching from coarse programming to fine programming is performed between complete _VPGM pulse trains, for example, as shown in FIG. In the V _PGM pulse train, additional or alternatively, a lower value range may be used in the second pass or other additional programming passes. Multi-pass coarse / fine programming may be considered a special type of multi-pass programming that typically involves programming a storage element to a target program state in multiple passes, such as using multiple pulse trains.

For example, the storage element may be programmed from an erased state, ie, state E, to a target program state A, B, or C. In one approach, coarse programming is used to program a storage element into an intermediate state A ′, B ′, or C ′ having an associated verification level of Vva _L , Vvb _L, or Vvc _L , respectively. The subscript “L” indicates that the verification level is associated with a lower state that is below the target state. Later, fine programming is used to program the storage element from the intermediate state to state A, B or C with an associated verification level of Vva _H , Vvb _H or Vvc _H , respectively. The subscript “H” indicates that the verification level is associated with a higher state that is the final target state. Accordingly, the threshold voltage of the programmed storage element is changed from a first level (eg, state A) to a second level (eg, Vva _L , Vvb _L, or Vvc _L ) during the first programming phase. Is increased from the second level to the third level (eg, Vva _H , Vvb _H or Vvc _H ) during the programming phase.

  FIG. 22 is a flowchart describing one embodiment of a method for programming non-volatile memory. In one implementation, the storage element is erased (in blocks or other units) prior to programming. In step 2200, a “load data” command is issued by the controller and the input is received by the control circuitry 1510. In step 2205, address data specifying a page address is input from the control unit or host to the decoding unit 1514. In step 2210, a page of program data for the addressed page is input to a data buffer for programming. That data is latched into the appropriate set of latches. In step 2215, a “program” command is issued to state machine 1512 by the controller.

By being triggered by the “program” command, the data latched in step 2210 is applied to the appropriate selected word line and the stepped program pulses 2305, 2310, 2315, 2320, 2325, FIG. 2330, 2335, 2340, 2345, 2350. . . Is used to program selected storage elements controlled by state machine 1512. In step 2220, the program voltage V _PGM is initialized to a start pulse (eg, 12V or other value) and a program counter (PC) maintained by the state machine 1512 is initialized to zero. In step 2225, an initial boost mode is applied, and in step 2330, a first pulse _VPGM is applied to the selected word line and programming of the storage element associated with the selected word line is initiated. If a logic “0” is stored in a particular data latch to indicate that the corresponding storage element is to be programmed, the corresponding bit line is grounded. On the other hand, if a logic “1” is stored in a particular latch, indicating that the corresponding storage element should remain in its current data state, the corresponding bit line is Vdd to inhibit programming. Connected to.

  In step 2235, the state of the selected storage element is verified. When it is detected that the target threshold voltage of the selected storage element has reached an appropriate level, the data stored in the corresponding data latch is changed to logic “1”. If it is detected that the threshold voltage has not reached an appropriate level, the data stored in the corresponding data latch is not changed. In this way, bit lines that have a logic “1” stored in the corresponding data latch need not be programmed. When all of the data latches store a logic “1”, the state machine knows (via the wired OR type mechanism described above) that all selected storage elements are programmed. In step 2240, a check is made as to whether all of the data latches are storing logic "1". If all of the data latches are storing logic “1”, then the programming process is completed with success because all selected storage elements have been programmed and verified. At step 2245, a “pass” status is reported.

If, at step 2240, it is determined that not all of the data latches are storing logic “1” s, the programming process continues. In step 2250, the program counter PC is checked against the program limit value PCmax. An example of the program limit value is 20. However, other numbers can be used. If the program counter PC is not less than PCmax, the program process fails and a “failed” status is reported at step 2255. If the program counter PC is less than PCmax _{is, V PGM} is increased by the step size, the program counter PC is incremented at step 2260. At step 2265, a determination is made as to whether the boost mode switching criteria are met (see, eg, FIG. 4). If such criteria are met, the boost mode is switched at step 2270, the process loops back to step 2230, and the next pulse V _PGM is applied. If the boost mode switching criteria is not met at step 2265, the process loops back to step 2230 and the next _VPGM pulse is applied without changing the boost mode.

FIG. 23 illustrates the pulse train 2300 applied to the control gate of the non-volatile storage element during programming and the boost mode switching performed in the pulse train. The pulse train 2300 is a series of program pulses 2305, 2310, 2315, 2320, 2325, 2330, 2335, 2340, 2345, 2350,... Applied to the word line selected for programming. . . Is included. In one embodiment, the programming pulse has a voltage V _PGM that starts at 12V and increases by, for example, 0.5V for each successive programming pulse until a maximum value of 20V is reached. There is a verification pulse between program pulses. For example, the verification pulse set 2306 includes three verification pulses. In some embodiments, for example, for each state where data is programmed into states A, B, and C, there is a verify pulse. In other embodiments, there are more or fewer verify pulses. Each set of verification pulses is, for example, Vva, Vvb and Vvc (FIG. 20), Vvb ′ (FIG. 21a), Vva _L , Vvb _L and Vvc _L , or Vva _H , Vvb _H and Vvc _H (FIG. 21d). May have an amplitude.

  The switching of the boost mode is shown to take place before the program pulse 2335 is applied. The first boost mode is applied before switching, and the second boost mode is applied after switching. As mentioned, the voltage applied to the word line to realize the boost mode is applied when programming occurs, such as when a program pulse is applied. In practice, the boost voltage in boost mode is initialized slightly before each program pulse and deleted after each program pulse. Thus, for example, no boost voltage is applied during the verification process that occurs between program pulses. Instead, a read voltage, usually less than the boost voltage, is applied to the unselected word lines. The read voltage has sufficient amplitude to maintain the already programmed storage elements in the NAND string when the threshold voltage of the currently programmed storage element is compared to the verify level.

  Thus, in one approach, a first subset of program pulses (eg, pulses 2305, 2310, 2315, 2320, 2325, and 2300) in pulse train 2300 are transferred to one or more storage elements during a first programming phase. Applied, in a second programming phase, a second subset of pulses of a pulse train (eg, pulses 2335, 2340, 2345, 2350) is applied to one or more storage elements. Thus, each programming pass includes multiple programming steps.

  FIG. 24 illustrates the pulse train applied to the control gate of the non-volatile storage element during programming and the boost mode switching that occurs between the pulse trains. In particular, the switching of boost mode is shown as occurring between pulse trains 2400 and 2450. In the first pulse train 2400 before switching, the first boost mode is applied. On the other hand, the second boost mode is applied during the second pulse train 2450 after switching. For example, pulse train 2400 is applied during the first pass of the multi-pass programming process, and pulse train 2450 is applied during the second pass of the programming process. Thus, in one approach, in a first programming phase, a first pulse train (eg, pulse train 2400) is applied to one or more storage elements on a selected word line and in a second programming phase, Two pulse trains (eg, pulse train 2450) are applied to one or more storage elements. Thus, each programming pass is synchronized with the programming phase.

  The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many variations and modifications are possible in light of the above teaching. The described embodiments best describe the invention and its practical application, so that those skilled in the art will be able to use the various embodiments and various modifications to suit the particular use intended. It was chosen to make the best use of the present invention. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (8)

A method of operating a NAND nonvolatile memory device,
In a non-volatile storage device, wherein a set of non-volatile storage elements communicates with a plurality of word lines and at least one storage element of the set of non-volatile storage elements communicates with a selected word line of the plurality of word lines Programming the at least one storage element;
During the programming step, a first set of voltages is applied to unselected word lines of the plurality of word lines, and the voltage of the unselected word lines is determined based on a boost mode switching criterion. Switching from applying a first set to applying a second set of voltages;
The first set of voltages is at least partially different from the second set of voltages;
The method of claim 1, wherein the boost mode switching criterion is based on a position of the selected word line among the plurality of word lines. A method of operating a NAND nonvolatile memory device,
In a non-volatile storage device, wherein a set of non-volatile storage elements communicates with a plurality of word lines and at least one storage element of the set of non-volatile storage elements communicates with a selected word line of the plurality of word lines Programming the at least one storage element;
During the programming step, a first set of voltages is applied to unselected word lines of the plurality of word lines, and the voltage of the unselected word lines is determined based on a boost mode switching criterion. Switching from applying a first set to applying a second set of voltages;
The first set of voltages is at least partially different from the second set of voltages;
The method characterized in that the programming comprises coarse programming performed before the switching step and fine programming performed after the switching step. A method of operating a NAND nonvolatile memory device,
In a non-volatile storage device, wherein a set of non-volatile storage elements communicates with a plurality of word lines and at least one storage element of the set of non-volatile storage elements communicates with a selected word line of the plurality of word lines Programming the at least one storage element;
During the programming step, a first set of voltages is applied to unselected word lines of the plurality of word lines, and the voltage of the unselected word lines is determined based on a boost mode switching criterion. Switching from applying a first set to applying a second set of voltages;
The first set of voltages is at least partially different from the second set of voltages;
The method wherein the boost mode switching criteria is based on when at least one other storage element of the set of non-volatile storage elements reaches a particular programming state. A method of operating a NAND nonvolatile memory device,
In a non-volatile storage device, wherein a set of non-volatile storage elements communicates with a plurality of word lines and at least one storage element of the set of non-volatile storage elements communicates with a selected word line of the plurality of word lines Programming the at least one storage element;
During the programming step, a first set of voltages is applied to unselected word lines of the plurality of word lines, and the voltage of the unselected word lines is determined based on a boost mode switching criterion. Switching from applying a first set to applying a second set of voltages;
The first set of voltages is at least partially different from the second set of voltages;
The method wherein the boost mode switching criteria is based on the number of programming cycles experienced by the set of non-volatile storage elements. A NAND-type non-volatile storage system,
A set of non-volatile storage elements;
A plurality of word lines in communication with a set of non-volatile storage elements, wherein at least one storage element communicates with a selected word line of the plurality of word lines;
Having one or more control circuits in communication with the set of non-volatile storage elements;
The one or more control circuits are
Programming the at least one storage element;
During the programming, a first set of voltages is applied to unselected word lines of the plurality of word lines, and the first voltage of unselected word lines is applied based on a boost mode switching criterion. Performing a step of switching from applying a set of voltages to applying a second set of voltages;
The first set of voltages is at least partially different from the second set of voltages;
The NAND-type nonvolatile memory system, wherein the boost mode switching reference is based on a position of the selected word line among the plurality of word lines. A NAND-type non-volatile storage system,
A set of non-volatile storage elements;
A plurality of word lines in communication with a set of non-volatile storage elements, wherein at least one storage element communicates with a selected word line of the plurality of word lines;
Having one or more control circuits in communication with the set of non-volatile storage elements;
The one or more control circuits are
Programming the at least one storage element;
During the programming, a first set of voltages is applied to unselected word lines of the plurality of word lines, and the first voltage of unselected word lines is applied based on a boost mode switching criterion. Performing a step of switching from applying a set of voltages to applying a second set of voltages;
The first set of voltages is at least partially different from the second set of voltages;
The NAND-type nonvolatile memory system, wherein the programming includes coarse programming performed before the switching step and dense programming performed after the switching step. A NAND-type non-volatile storage system,
A set of non-volatile storage elements;
A plurality of word lines in communication with a set of non-volatile storage elements, wherein at least one storage element communicates with a selected word line of the plurality of word lines;
Having one or more control circuits in communication with the set of non-volatile storage elements;
The one or more control circuits are
Programming the at least one storage element;
During the programming, a first set of voltages is applied to unselected word lines of the plurality of word lines, and the first voltage of unselected word lines is applied based on a boost mode switching criterion. Performing a step of switching from applying a set of voltages to applying a second set of voltages;
The first set of voltages is at least partially different from the second set of voltages;
The NAND nonvolatile storage system, wherein the boost mode switching criteria is based on when at least one other storage element of the set of nonvolatile storage elements reaches a particular programming state. A NAND-type non-volatile storage system,
A set of non-volatile storage elements;
A plurality of word lines in communication with a set of non-volatile storage elements, wherein at least one storage element communicates with a selected word line of the plurality of word lines;
Having one or more control circuits in communication with the set of non-volatile storage elements;
The one or more control circuits are
Programming the at least one storage element;
During the programming, a first set of voltages is applied to unselected word lines of the plurality of word lines, and the first voltage of unselected word lines is applied based on a boost mode switching criterion. Performing a step of switching from applying a set of voltages to applying a second set of voltages;
The first set of voltages is at least partially different from the second set of voltages;
A NAND nonvolatile memory system, wherein the boost mode switching criterion is based on the number of programming cycles experienced by the set of nonvolatile memory elements.

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