WO2008042591A3 - Local channel-boosting control implant for nand memory - Google Patents

Local channel-boosting control implant for nand memory Download PDF

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Publication number
WO2008042591A3
WO2008042591A3 PCT/US2007/078815 US2007078815W WO2008042591A3 WO 2008042591 A3 WO2008042591 A3 WO 2008042591A3 US 2007078815 W US2007078815 W US 2007078815W WO 2008042591 A3 WO2008042591 A3 WO 2008042591A3
Authority
WO
WIPO (PCT)
Prior art keywords
word lines
end word
substrate
deeply implanted
channel
Prior art date
Application number
PCT/US2007/078815
Other languages
French (fr)
Other versions
WO2008042591A2 (en
Inventor
Fumitoshi Ito
Original Assignee
Sandisk Corp
Fumitoshi Ito
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/536,416 external-priority patent/US7705387B2/en
Priority claimed from US11/536,389 external-priority patent/US7977186B2/en
Application filed by Sandisk Corp, Fumitoshi Ito filed Critical Sandisk Corp
Publication of WO2008042591A2 publication Critical patent/WO2008042591A2/en
Publication of WO2008042591A3 publication Critical patent/WO2008042591A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Abstract

A substrate of a non-volatile storage system includes selected regions in which additional ions are deeply implanted during the fabrication process. NAND strings (1000, 1010, 1020) are formed over the selected regions such that end word lines of the NAND strings are over the deeply implanted ions (810, 820). The presence of the deeply implanted ions below the end word lines increases a channel capacitance of the substrate under the end word lines. Due to the increased capacitance, boosting of a channel in the substrate below the end word lines is reduced, thereby reducing the occurrence of gate induced drain leakage (GIDL) and band-to-band tunneling (BTBT) and, consequently, program disturb. A shallow ion implantation (610) may also be made to set a threshold voltage of storage elements of the NAND string.
PCT/US2007/078815 2006-09-28 2007-09-19 Local channel-boosting control implant for nand memory WO2008042591A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/536,416 US7705387B2 (en) 2006-09-28 2006-09-28 Non-volatile memory with local boosting control implant
US11/536,389 US7977186B2 (en) 2006-09-28 2006-09-28 Providing local boosting control implant for non-volatile memory
US11/536,389 2006-09-28
US11/536,416 2006-09-28

Publications (2)

Publication Number Publication Date
WO2008042591A2 WO2008042591A2 (en) 2008-04-10
WO2008042591A3 true WO2008042591A3 (en) 2008-06-12

Family

ID=39247810

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/078815 WO2008042591A2 (en) 2006-09-28 2007-09-19 Local channel-boosting control implant for nand memory

Country Status (2)

Country Link
TW (1) TWI352404B (en)
WO (1) WO2008042591A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102094535B1 (en) 2014-03-21 2020-03-30 삼성전자주식회사 Transistor and method for fabricating the same
US11810982B2 (en) 2021-08-02 2023-11-07 Globalfoundries Singapore Pte. Ltd. Nonvolatile memory device with a doped region between a source and a drain and integration schemes

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050099847A1 (en) * 2003-02-05 2005-05-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems
US20050104120A1 (en) * 2001-05-28 2005-05-19 Masayuki Ichige Non-volatile semiconductor memory device with multi-layer gate structure
US20060011991A1 (en) * 2001-01-31 2006-01-19 Toshitake Yaegashi Non-volatile semiconductor memory device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060011991A1 (en) * 2001-01-31 2006-01-19 Toshitake Yaegashi Non-volatile semiconductor memory device and method of manufacturing the same
US20050104120A1 (en) * 2001-05-28 2005-05-19 Masayuki Ichige Non-volatile semiconductor memory device with multi-layer gate structure
US20050099847A1 (en) * 2003-02-05 2005-05-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems

Also Published As

Publication number Publication date
WO2008042591A2 (en) 2008-04-10
TWI352404B (en) 2011-11-11
TW200834825A (en) 2008-08-16

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