TW200903499A - Non-volatile storage with boosting using channel isolation switching and method thereof - Google Patents

Abstract

Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

Description

200903499 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory. This application is related to the title "Ncm-Volatile Storage With

Boosting Using Channel Isolation Switching, U.S. Patent Application Serial No. __ (file No. SAND-1229US1), which is incorporated herein by reference.

Semiconductor memory has become increasingly popular in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital phase non-mobile computing devices, and their personal personal assistants, mobile computing devices, and other devices. Among the most popular non-volatile semiconductor memories are electronically erasable programmable read-only memory (EEPR〇M) and flash memory. In contrast to the conventional fully characterized EEPR0M, in the case of flash memory (also of the EEPROM type), the content of the entire memory array or the contents of one part of the memory can be erased in a single step. Both conventional EEPROM and flash memory utilize a floating closed-pole that is positioned above the channel region in the semiconductor substrate and insulated from the channel region. The movable gate is positioned between the source region and the drain region. The control gate is provided above the float and insulated from the floating open. The threshold voltage (VTH) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the gate before the transistor is allowed to conduct between its source and drain is the charge on the floating gate (4)_. Some EEPR〇M and flash memory devices have two states for storing two charges 131225.doc 200903499, and thus can be in two states (eg, erased state and stylized state) Stylize/erase memory components. This flash memory device is sometimes referred to as a binary flash memory device. A memory device can store a data bit. The ',' and parent multi-state (also referred to as multi-level) flash memory devices are implemented by a different allowable/effective programmed threshold voltage range. ^ A small threshold voltage range corresponds to a predetermined value of the coded = in the memory device. For example, when each memory component can be placed in: four discrete charge bands of four distinct threshold voltage ranges, the two-bit elements can store two data bits. The crane will apply force to the control during the operation of the program.] The program of the idle pole vPGM is applied as a series of pulses that increase with time. In the "energy method", the magnitude of the pulse is increased by a predetermined step and length with each successive pulse, for example, '0·2-〇·4 V. VpGM can be applied to the control gate of the flash memory device. The verification operation is performed during the period between the program pulses. That is, the continuous stylized pulse (4) takes the stylized level of each component of the parallel-programmed component group to determine whether it is equal to or greater than the verify level to which the component is programmed. For a multi-state flash memory S-piece array, a verification step can be performed for each state of the component to determine if the component = reaches its data association verification level. For example, a multi-state memory component capable of four-segment data storage may need to perform verification operations for three comparison points. In addition, when stylized EEPROM or flash memory devices (such as the gambling flash memory device in N gamma series), v_ is usually applied to 131225.doc 200903499 to the control gate and the bit 7L line is grounded. Thereby electrons from channels of cells or memory elements (eg, storage elements) are injected into the floating gate. When electrons accumulate in the floating gate, the floating closed-pole becomes negatively charged, and the threshold voltage of the memory element rises, making the memory element considered to be in a stylized state. Available under the heading "source Side Self Boosiing

Technique For Non-Volatile Memory" US Patent 6,859,397 and February 3, 005, titled "(10)(9) by 叩ο· pr〇grammed

More information on this stylization can be found in the US Patent Application Publications of Memory; the manner in which these cases are applied is incorporated in this article in its entirety. The problem is program disturb. However, program disturb can occur at the suppressed nand string during the NAND string that continues to be problematic, and sometimes program disturb occurs at the programmed post itself. Program disturb occurs when the threshold voltage of the unselected non-volatile storage element is shifted due to the stylization of other non-volatile storage elements. The 7C pieces can be stored in the previous process and the erased storage elements that have not yet been programmed can be interfered with. BACKGROUND OF THE INVENTION The present invention addresses these and other problems by providing a method for reducing interference in a non-volatile reservoir. In the practical package, a == line on the side of the line for operating the non-volatile memory is raised at least -_ string before the first: '~ ^ ^ at least one NAND string is lifted - wherein The first sub-line is on the non-polar side of the first word line. Including the first word line and the second word 131225.doc 200903499 The multi word line is associated with at least a letter (four), and at least one _d two = multiple non-volatile storage elements. The method further includes first applying a voltage to the first word line in the first mid-disc for providing a first non-volatile storage element associated with the conduction state::, two-pre-line; and applying a voltage: The two-word line is used to provide a first-non-volatile storage element associated with the (four) two-word line in the conductive state. # ^ ^ 运 运 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The medium and non-volatile storage elements, and simultaneously apply the program voltage to the first sub-line. Therefore, the source side rise occurs before the program pulse is applied. Implementing a method for operating a non-volatile memory is at least the first non-volatile storage in the NAND string: the first-elevation of the string, which is in the volatile storage element in the stylized sequence. prior to. The method further comprises a first non-volatile storage element on the first-lift two = one less and a second non-volatile storage element on the side of the pure storage element, wherein the sequence is in the first - non-volatile The storage element I# method further includes a side of the second non-volatile storage after the first promotion [•拙s, in the sequence of the second: non-string second promotion' After storing 7L pieces, the first storage element is provided in the conduction. In another embodiment, Yin includes (a) a first method for operating a non-volatile memory on a source side of a word line in a first period - '(i) applying a voltage to a word line set a particular set of word lines for boosting at least the first channel region of the -nand I3I225.doc •10.200903499 string; (ii) applying a voltage to the set of word lines including the particular word line to provide at least a -NAND string a: a set of word lines associated with a non-volatile storage element in a conductive state, a second set of word lines being on a drain side of the first set of word lines; and (iii) applying a voltage to the second set of word lines The third set of word lines on the drain side avoids lifting the second channel region of at least one nand string. The method further includes (b) in a second time period following the first time period: (1) applying a voltage to the third set of word lines for boosting the second channel region of the at least one NAND string; (ii) applying a program voltage to the Two word line

And a word line in the set; and (iii) applying a voltage to the particular word line to isolate the first channel region from the second channel region. [Embodiment] The present invention provides a method for reducing program disturb in a non-volatile memory. One example of a memory system suitable for use in practicing the present invention utilizes a nani^ flash memory structure that includes a plurality of transistors arranged in series between two select gates. The series transistor and the select gate are referred to as NAND strings. Figure i is a top plan view showing a NAND string. Figure 2 is its equivalent circuit. The NAND strings depicted in FIG. 1 and FIG. 2 include four transistors 1〇〇, 1〇2, 1〇4, and 1〇 connected in series and sandwiched between the first selection gate 12〇 and the second selection gate 122. 6. The NAND string connection of the gate 120 gate to the bit line 126 is selected. The gate 122 is gated to the NAND string connection of the source line 128. The selection gate 12 is controlled by applying an appropriate voltage to the control gate 120CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 1, 102, 104, and 106 has a control gate and a floating gate. Electric 131225.doc 200903499 The crystal 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is coupled to (or) word line WL3, control gate 102CG is coupled to word line WL2, control gate 104CG is coupled to word line WL1, and control gate 106CG is coupled to word line WL0. In one embodiment, transistors 100, 102, 104, and 106 are each a storage element, also referred to as a memory unit. In other embodiments, the storage element may comprise a plurality of transistors, or may be different from the storage elements depicted in Figures 1 and 2. The selection gate 120 is connected to the selection line SGD. The selection gate 122 is connected to the selection line SGS. Figure 3 is a circuit diagram depicting three NAND strings. A typical architecture for a flash memory system utilizing a NAND structure would include several NAND strings. For example, three NAND strings 320, 340, and 3 60 are shown in a memory array having many other NAND strings. Each of the NAND strings includes two select gates and four storage elements. Although four storage elements are illustrated for simplicity, modern NAND strings can have up to, for example, thirty-two or sixty-four storage elements. For example, NAND string 320 includes select gates 322 and 327 and storage elements 323-326, NAND string 340 includes select gates 342 and 347 and storage elements 343-346, NAND string 360 includes select gates 362 and 367 and storage Elements 363-366. Each NAND string is connected to the source line by its select gate (e.g., select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. The various NAND strings 320, 340, and 360 are connected to respective bit 7L lines 321, 341, and 361 by selecting a selection transistor in gates 322, 342, 362, etc., by I31225.doc -12-200903499. These selective transistors are controlled by the drain select line SGD. In other embodiments, the select lines do not necessarily need to be common in the nand string; that is, different select lines can be provided for different NAND strings. The sub-line WL3 is connected to the control gates of the storage elements 323, 343 and 363. Word line WL2 is coupled to the control gates of storage elements 324, 344 and 364. Control gate WL0, to which word line WL1 is coupled to storage elements 325, 345, and 365, is coupled to the control gates of storage elements 326, 346, and 366. It can be seen that each bit line and each NAND string contains a row of storage element arrays or sets. The word lines (WL3, WL2, wl^wl〇) contain arrays or arrays. Each word line connects each of the columns to the control element of the storage element. Or the 'control gate' can be provided by the word line itself. For example, word line WL2 provides control gates for storage elements 324, 344, and 3M. In practice, there can be thousands of storage elements on a sub-line. Each storage element can store data. For example, when storing a bit of data bits, the range of possible threshold voltages (VTH) of the storage elements is divided into two ranges', which are assigned logical data "i,,,,'". In an example of a NAND type flash memory, 'Vth is negative after erasing the storage element and is defined as a logical "1". In the program operation έ . The vTH after the game is positive and is defined as a logical "〇". When the vTH is negative and an attempt is made to read, the storage element will be logically stored. When the vTH is positive and an attempt is made to read the material, the storage component will not be turned on, and the indication logic is stored. The storage component can also store multiple messages (4), such as 'multiple digit data bits. In this case, divide the value into the number of data levels. For example, if you store four 131225.doc -13-200903499, you will be assigned the data value "11"," 1〇 ", "01" and the four vTH ranges of 〇〇. In one example of a NAND type memory, the VTH after the erase operation is negative and is defined as "u". The positive Vth value is used for the shape L 10 , "01" and "〇〇". The specific relationship between the data programmed into the storage element and the component's threshold voltage range is used for the storage of the piece. Depending on the data encoding scheme, for example, 'US Patent No. 6,222,762 and US Patent Application Publication No. 2_/G255G9G are described for multi-state fast

Various data encoding schemes for flash storage of 7L pieces are incorporated herein by reference. Examples of NAND type flash memory and its operation are provided in U.S. Patent Nos. 5,386,422, 5,522,58, 5,57,315, 5,774'397, 6, 6, 46,935 &帛M56, 528 and M22, each of which is incorporated herein by reference. * When the flashing component is programmed, the program dust is applied to the control gate of the storage component, and the bit line of the storage component is grounded. In the future = the electronic injection of the road into the floating gate. When the electrons accumulate in the floating idle pole, the oceanic gate becomes negatively charged, and the storage element rises and the known voltage is applied to the sister-V'/μ々·', "the storage element of the king." The gate is controlled and the program is applied to the appropriate word line. As discussed above, one of the storage elements of the ^ share the same word line. For example, the storage element 324 of Figure 3 is programmed. At the same time, the program is also applied to the control gates of the two pieces 344 and 364. However, during the stylization of the other strings, program disturb occurs at the suppressed Nand 13I225.doc -14- 200903499 string, and there is Private interference occurs at the programmed nand string itself. When the threshold voltage of the unselected non-volatile storage element is shifted due to the stylization of other non-volatile storage elements (4), program disturb occurs. Program disturb occurs on stylized storage elements and erased storage elements that have not yet been programmed. Various program interference mechanisms may limit the available operations for = volatile storage devices (such as NAND flash memory). String 320 is suppressed (for example, it is an unselected paste string that does not contain pre-programmed storage elements) and the secondary (four) state: stylized (for example, it is a selected NAND string containing the current, "typed storage element", Program disturb can occur at NAN"32G. For example, if the pass VGltage VpAss is low, it is suppressed. The channel of the string is not well boosted, and the selected word line of the (four) gamma string can be unintentionally programmed. In another-possible scenario, the boosted voltage can be reduced by the gate-induced immersion, __ or other _ system, which causes the same problem. Other effects, such as the VTH shift of the charge storage element due to the capacitance of other adjacent storage elements that are later programmed, may also contribute to program disturb. Figure 4 depicts a cross-sectional view of a Nand string showing the program interference mechanism. The revised erase area self-boosting (SB) mode 6-her view, such as depicted in Figure 5c, is simplified and not to scale. The NAND string 400 includes a source side selection gate 4〇6 formed on the substrate 490, a drain side selection pole, and eight storage elements, 410, 412, 414, 416, 418, 420, and 422 p wells. The zone self-forming component can be formed on the p-well region 131225.doc 15 200903499 in the n-well region of the substrate. The n well can be formed in the p substrate. In addition to the bit line 426 having the potential VBL, a source supply line 404 having a potential is provided. During stylization, VpGM is provided on the selected word line (in this case, yang) associated with the selected storage element 418. Additionally, it is recalled that the control gate of the storage element can be provided as part of the word line. For example, 'WLO, WL1, WL2, WL3, WL4'wu, wm, and WL7 may extend through the control gates of storage elements 4〇8, 4l〇, 4i2, am, ye, 418, 420, and 422, respectively. In the - instance boost mode, when the storage element 418 is the selected storage element, a relatively lower voltage VL0W (eg, 2_6 v) is applied to the adjacent source side word line (WL3), and the isolation voltage Vis is (eg, , 〇_4 v) is applied to the other-source side word line (WL2), which is referred to as an isolated word line, and v(10) is applied to the remaining word lines associated with the 盥 NAND string 400 (ie, WL0, WL1, machine 4. WL6 and WL7). Although the absolute values of ^ 〇 and % (10) may vary over a relatively large and partially overlapping range, in a possible embodiment, the value of vlso is always lower than Vlow. Vsgs is applied to select gate 4〇6 and VSGD is applied to select closed pole 424. The source side of the word line or non-volatile storage element refers to the side facing the source terminal of the NAND string (eg, at the source supply line _), while the drain side of the word line or non-volatile storage element refers to The side facing the extreme of the NAND string (eg, at bit line 426). Figures 5a through 5h depict different examples of self-elevation modes. Note that the voltage of the indicated voltage indicates the voltage used during the drain side lift occurring after the source side is boosted. See also Figures 6 to 9. Various other methods are also available. In general, various types of boost modes have been developed to combat program disturb. During the stylization of the storage elements on the selected 131225.doc -16 - 200903499 word line, to the currently unprogrammed storage elements, 隹...voltage set ^ 提提井槿..., unselected words of Ding Communication The line is ", & stylized storage elements associated with the selected NAND string V, the storage element is associated with the unselected NAND string. In the example provided, the word line is (4) to WLn, the source side selects the gate control 圯 to the 踝马 帝 J line is SGS, and the drain side select gate control line is SGD. The set of voltages applied to the control line is also depicted. The stylization can be performed from the source side to the immersed side of the NAND string in a sequence of - word lines. However, other stylized sequences can also be utilized. For example, in the two-step programming technique, the storage element of the NAND string can be partially programmed in the first process from the source side of the nand string to the bottom side of the nand string in the first process. Conducted. Then, the stylization is completed in the second process, and in the second process, the word line is also performed one line at a time from the source side to the drain side of the NAND string. In another option, the storage elements are stylized in two previous processes, for example, in the following sequence: WL〇 (partially stylized), WL1 (partially stylized), WL〇 (completed stylized), WL2 (partial program) , WL1 (completed stylization), WL3 (partially stylized), and so on. In the example shown in Figure 5a, the applied voltage includes: vSGs applied to the source side select gate control line SGS; pass voltage VPASS applied to the unselected word lines WL0 to WLn-2 and WLn+Ι To each of WLi; a program voltage VpGM applied to the selected word line WLn; an isolation voltage VIS〇 applied to the word line WLn-Ι adjacent to the selected word line on the source side; and VSGD 'It is applied via the drain side selection gate control line SGD. Normally, VSGS is 0 V ', so that the source side selection gate is closed and can be applied within the range of 〇5-1 $131225.doc -17- 200903499 v The additional source bias voltage Vs〇urce further improves the switching behavior of the source side select gate. The VSGD is about 15_3 V such that the drain side select gate of the selected NANE) string is turned on due to the application of the corresponding low bit line voltage Vbl (such as οι V). The unselected/suppressed NAND string's drain side select gate is turned off due to the application of two more VBLs (such as 1.5-3 V). In the example of Figure 5a, a low isolation voltage να 典型 within a typical range of 〇_4 v is applied to the word line adjacent to the selected word line on the source side. In addition, VPASS can be about 7_1 〇 v, and VpGM can vary from about 12 _25 v. In a stylized scheme, a pulse of program voltage is applied to the selected word line. See Figure 20. The amplitude of each successive program pulse in the burst is increased in a stepwise manner, typically by about 〇 3_〇 5 v per pulse. Alternatively, a verify pulse can be applied between the program pulses to verify that the selected storage element has reached the target stylized condition. Also note that each individual program pulse may have a solid amplitude or may have a varying amplitude. For example, some stylization schemes apply pulses with amplitudes that vary like ramps or steps. Any type of program pulse can be utilized. In the case where WLn is a stylized word line and the stylization is performed from the source side to the secret side of each nand string, the storage element associated with WLOS WLn_i has been at least partially since the last wipe (4) Stylized, and when the storage elements on WLn are programmed, the storage elements associated with WLn+i to; U= will be erased or at least not fully programmed. The pass voltage on the unselected word line is coupled to the channel associated with the unselected NAND string, thereby causing a voltage in the channel of the unselected NAND string, which tends to reduce the electrical charge across the oxide of the memory element Dust to reduce program interference. 13I225.doc •18- 200903499 Figure 5b depicts the revised erased area self-elevation mode. In this case, the isolated electric magic VIS0 is applied to WLn-2, and the low voltage VL0W between 〇 and 乂 (10) is applied to WLn-丨. Vl〇w can also be considered as an isolation voltage, however, in a possible embodiment, 乂_ is always higher than Vis 〇 and lower than ν_. In this method, vL0W acts as an intermediate voltage such that there is less abrupt voltage change in the channel between the selected word line (wLn) and the adjacent source side word lines (WLn_丨 and WLn_2). For example, Vl〇w can be, for example, 2_6 v, and VIS0 can be, for example, 〇-4 V. Less abrupt changes in channel voltage result in lower electric fields and lower channel potentials in the channel region, especially at the storage elements associated with the U-line. The high channel voltage at the drain side or source side of the stored 7L piece associated with the Vis 〇 word line (as shown in the figure) allows charge carriers (electrons and holes) to cause a drain leak through the gate Produced by (GIDL). The electrons generated by GIDL can then be in the selected word line with Vis. Acceleration in a strong electric field in the region between the word lines' and subsequent injection (via hot electron injection) into the memory elements associated with the selected word line and thus causing program disturb. This program disturbing mechanism can be avoided or reduced by reducing the electric field, such as by adding one (or more) word lines biased by an intermediate voltage between the voltage of the selected word line and Vis. The remaining unselected word lines receive VpASs. Specifically, VPASS is applied to the first-storage element group associated with WL 〇 to U, where the first-group is adjacent to the source side: 4 is the gate and is on the source side of the isolated word line WLn_2. Further, VPAS0& is applied to the second storage element group associated with WLn+1 to WU, wherein the second group is adjacent to the drain side select idle and on the bottom side of the selected word line WLn. 131225.doc 19 200903499 Figure 5c depicts another revised erased area self-elevation mode. In this case, the source side word line (wLn-Ι) adjacent to the selected word line (WLn) receives Vpass, and the next word line (WLn-2) receives VL0W, and the next word line after the other (WLn-3) receives V1S0. The remaining unselected word lines receive VpAss. This lifting mode is also discussed in conjunction with FIG. In particular, VPASS is applied to the first set of storage elements associated with WL0 through WLn-4, wherein the first group is adjacent to the source side select gate and on the source side of the isolated word line WLn-3. Further, VpAs^fc is applied to the second storage element group associated with WLn+1 to WLi, wherein the second group is adjacent to the drain side selection gate and on the drain side of the selected word line WLn. The advantage of this method is that the selected word line (which is most sensitive to program disturb due to the high program voltage VPGM applied to the word line) is further away from να. And word line. The storage element associated with the selected word line is less likely to be disturbed by hot electron injection because the electric field of the hot carrier generated by the negative shell is located further away from the selected word line. Figure 4Cufe depicts another modified erase area self-boost mode. In this case, the source side word line adjacent to the selected word line (WLn) (U receives VPASS 'the next word line (WLn_2) receives Vl〇w, and the lower-word line (wLn_3) receives vIS0' and A word line receives Vl〇w. Multiply the m unselected word line to receive v. Specifically, 'vPASS is applied to the first storage element group associated with machine 0 to heart_5, * the first group is adjacent to the source The pole side selects the gate and is on the source side of the isolation word line WLn-3. Further, VpAss is applied to the second group adjacent to the first group of the first storage element group 'I. Select the gate and on the drain side of the selected word line WLn. Providing vLOW at both sides of the isolated word line can be reduced due to the height of the boosted source side (eg 'in w1〇 to 13I225.doc •20 - 200903499 WL5 associated channel of all the eight nan, τ π < nj 4 points) and the probability of gidl occurring in the isolated word line. Figure (4) painted another - revised erase area self-improvement mode. In this situation Next, the source side word line adjacent to the selected word line (WLn) receives VPASS.HIGH, and the lower-word line (WLn_2) receives v with circle_, and the next word line (WLn-3) receives VPAS S_L0W, the lower-word line (WLn_4) receives Vl〇w, the next word line (WLn-5) receives VISO, and the next word line (WLn_6) receives Vl〇w. The remaining unselected word lines receive VpASS. VpAss is applied to the first storage element group associated with wL〇 to WLn-7, wherein the first group is adjacent to the source side selection gate and on the source side of the isolation word line WLn_5. a second storage element group associated with WLn+Ι to WLi, wherein the second group is adjacent to the drain side selection gate and on the drain side of the selected word line WLn. Therefore, multiple vPASSs can be utilized simultaneously For example, different VpAss values can be used for the drain side and the source side of the NAND string. In addition, multiple VpAss voltages can be utilized at both the drain side and the source side. For example, as depicted, it can be tight Higher VpAss (VpAss_) are used for programming when connected to the selected word line. For word lines between the selected word line and the isolated word line, there may be biased to *with VpASS values (eg, Multiple word lines of VpAss__, ~face-like and VPASS-HIGH. In one embodiment, VpGM>VpAss.hIGH>VPASS-MEDIUM>Vpass_l〇w>Vl 〇w>Vis〇. Note that multiple values of & (iv) and vIS〇 are also possible. Typically, all Vis〇 voltages are less than all VL0W voltages, and all vL〇w voltages are less than all VPASS voltages. The number of word lines between the selected word line and the VIS0 word line, and by gradually reducing the bias voltage on the word lines, the selected word line can be reduced from the v s 〇 word line 131225.doc 21 200903499 The electric field and therefore the ripple interference can be reduced. Figure 5f depicts another revised erased area self-elevation mode. In this case, the source side word line (WLn_丨) adjacent to the selected word line (WLn) receives VPASS-HIGH'. The next word line (WLn-2) receives VPASS-MEDIUM, the next word line ( WLn-3) receives VPASS_L0W, the next word line (WLn_4) receives Vl〇w, the next word line (WLn-5) receives VIS0, the next word line (WLn_6) receives Vl〇w, and the next word line (WLn) -7) Receive VPASS.L〇w. The remaining unselected word lines are received. Specifically, vPASS is applied to the first group of storage elements associated with WL0 through WLn_8, wherein the first group is adjacent to the source side select gate and on the source side of the isolated word line WLn-5. Further, vPASS is applied to the second storage element group associated with WLn + Ι to WLi, wherein the second group is adjacent to the drain side selection gate and on the bottom side of the selected word line WLn. Figure 5g depicts another revised erased area self-elevation mode. This condition differs from the condition of Figure 5f in that the drain side word line (WLn+Ι) adjacent to the selected word line (WLn) receives VPASS.H1GH instead of VpASS 0. Figure 5h depicts another modified erase Regional self-upgrading mode. In this case, additional isolation word lines are provided on the drain side of the programmed word line. For example, in a possible embodiment, WLn+1 receives VPASS-HiGH and WLn+3 receives V丨s, as compared to the boost mode of Figure 5c. . WLn + 2 receives VPASS, where VPASS-HIGH>vPASS. Three elevated channel regions are provided in the NAND string due to the applied boost voltage and two isolation voltages'. For example, the first elevated channel region is in the region of WL0 to WLn-4, the first elevated channel region is in the region of WLn-1 to WLn+2, and the third elevated channel region is in WLn. +4 to the area of WLi. (such as) When the WDn+1 can be partially programmed by J31225.doc •22-200903499 (see, for example, Figure 1 for the Βι state), the use of Vpass-high removes the WLn+ Data dependency. The lifting mode of Figures 5d to 5g can be similarly modified. Various other practical examples are possible. For example, different elevated channel areas can be raised to different levels. Also, the number of word lines between the selected word line and the extra drain side isolation word lines can vary. The voltage applied to the unselected word lines in the different elevated channel regions can also vary. Embodiments having more than two isolation voltages and three elevated channel regions are also provided. For other details, refer to the title of “Reducing” on September 2, 2006.

U.S. Patent Application Serial No. 11/535,628, the disclosure of which is incorporated herein by reference. Various embodiments are possible with respect to timing of boosting of different channel regions. Consider the first channel region between WL0 and WLn-4, the second channel region between WLn-Ι and WLn+2, and the third channel region between WLn+4 and WLi. In a method, the first channel zone and the third channel zone are jointly raised, and thereafter the second channel zone is raised. In one method, the first channel area is raised, and thereafter the channel area and the third channel area are jointly raised. In one method, the first channel area is raised, and thereafter the third channel area is raised, and thereafter the second channel area is raised. In general, it is preferred that the second channel region be not raised prior to the third channel region because electrons from the second channel region will be attracted to the elevated second channel region, thereby reducing the elevated channel potential in the second channel region while Increase the third channel area slightly. This is an improper effect' because the reduced increase can cause program interference. Note that 'all of the above examples are for illustrative purposes only, as other bias conditions and different combinations of 131225.doc •23·200903499 bias conditions are possible. Referring again to Figure 4, it is assumed that the stylization of the storage elements along the Nand string 400 is From the staging sequence of storage element 408 to storage element 422, storage element 408-4 1 将 will have been at least partially programmed, and storage elements 42 and 422 will not yet be fully programmed. Thus, all or some of the storage elements 408·416 will have programmed and stored in their respective floating gate electronics and can erase or partially program the storage elements 420 and 422, depending on the stylized mode. For example, storage elements 420 and 422 may be partially programmed when the storage elements 42 and 422 have been previously programmed in the first step of the two-step stylization technique. In the case of EASB or REASB boost mode, VIso^ is added to one or more source side neighbors of the selected word line at a temple after the initial boost, and Vis is low enough to isolate the program in the substrate. The channel area and the erased channel area. That is, the substrate region of the substrate 490 on the source side of the isolation word line 412 is isolated from the channel region of the substrate on the drain side of the isolation word line 412. The source side can also be considered as a stylized side because the stylized association stores most or all of the π pieces, and the drain side can also be considered unstylized side 'because the associated storage elements have not been programmed yet . In addition, the pass on the source side is the first lifted region of the substrate 49 which is raised by applying v(10) to WLG and wu, and the channel region on the drain side is the substrate 49. A VpGM is applied to WL5 and a second lifted area that is lifted as a percentage is applied to WL4, WL6, and machine 7. In general, the stylized area has been improved less because the channel potential under the stylized storage element is only 〇pAss at a high enough level to open the 131225.doc -24-200903499 scripted storage element. Can start to increase (for example, improved). On the other hand, the channel potential of the storage element under erased conditions will begin to increase (almost) immediately after VPASS is applied, since most, if not all, of the erased storage elements will be on, even when applied When the vPASS voltage of the corresponding word line is still very low (the ramping of the Vpass voltage (ramping)

Up)). Therefore, when the channel region on the gate side of the isolation word line and the channel region at the source side of the isolation word line are isolated from each other, the channel region on the drain side of the isolation word line and the source side of the isolation word line The channel area will be boosted to a higher potential. In some embodiments, the programmed voltage VpGM applied to the selected word line will be applied after the two channels are sufficiently boosted. Although the above embodiment can reduce the specific program interference mechanism, there is indeed a / program interference mechanism. When vPASS is relatively high, one other program interference failure mode tends to occur on higher word lines. This failure mode occurs on the '' to the stylized NAND string (e.g., the selected NAND string) and is caused by hot carrier injection from the drain side of the selected NAND string channel. When VPASS reaches a certain level, this hot carrier injection is caused by the same boosting potential in the source side channel. In particular, in the case of EASB and REASB, the NAND string is divided into a source side and a drain side by applying an isolation voltage vis 于 to the word line below the selected word line as discussed. In the selected NAND string, for example, during boost, the gate side potential will remain at 0 1 V. However, on the source side, since the storage element receiving the ναό is cut (1) as provided in the non-conducting state, assuming that Viso<VTH, where VTH is the threshold voltage for storing tl pieces, the channel is still raised. When the source side raises 131225.doc -25-200903499, the potential of the rise becomes high and the drain side channel power is maintained at 0v, the large-horizontal and the storage element on the source side is generated. The hotter carrier injection is more. This is depicted in the figure "," in which the arrow moves over the channel under the isolation element 412 and moves to the sub-closed pole of the storage element to raise the threshold voltage of the storage element by 0. This enchantment in the NAND string recognizes that the other program of the cheek interferes with the better, and the better 疋 does not isolate the source side channel from the immersed side channel during the & liter. In the absence of isolation, there is no isolation. In the suppressed NAND string channel, the immersed side will be significantly reduced by the source side of the stylized storage element. In detail, when the high word line is programmed and the source side and drain side channel capacitance ratio changes In the case of this method, the isolation word line is kept in the case of the method of the method. In order to overcome this dilemma (10) emma), the channel isolation switching method is proposed based on the source side early promotion scheme. A relatively high current VC such as 4 V) is sufficient to open the isolated storage element (even if the isolated storage element is in the highest programmed state), thereby connecting the source side channel and the 在 during source side lift Extreme side channel. For further assurance The connection of the source side channel and the drain side channel in the selected NAND string may also apply VC0ND to the word line on the drain side of the isolation storage element until the selected word line opens the associated storage element, for example, It is in a conductive state or on. In addition, if a stylization technique that at least partially programs the storage elements on the drain side of the selected storage element is utilized, VC(10)〇 can also be applied to the storage elements to The source side channel is kept open during the boosting. Since the source side channel and the drain side channel are connected, in the selected 131225.doc •26·200903499 NAND string, the material potential will be (4)(4)·iv and the material is raised to the source side. It will eliminate or reduce the transfer of hot electrons from the non-polar side to the source side of the channel and the drain type (4). In order to ensure that the source side channel is connected to the drain side channel when the source is stepped up, vC0ND is applied later than Vpass. In order to provide a safety margin, vCC)ND may be applied shortly before VPASS begins to ramp up on the source side. After the source side boost is completed, it shall be isolated before the drain side lift begins. Word line The voltage is reduced to VIS. In this way, the dead-side side of the suppressed channel (in the unselected NAND string) remains isolated from the source side. In addition, the improved efficiency of the suppressed channel is improved because during source-side boosting Many of the electrons in the drain ^ channel will flow to the source side, effectively causing some boosting of the drain side channel before applying Vmm to the drain side word line. On the other hand, in the selected NAND string The channel potential on the source side and the drain side remains at 0·1 V, and the type of implant interference on the drain side is prevented or reduced again. Figure 6 depicts the time of the word line and other voltages based on the self-boost mode of the figure. line. The period shown depicts a single boost and stylized loop with a single stylized pulse. This loop is typically followed by a verification pulse sequence to determine if the stored 7L piece has reached the desired stylized state. The lifting and stylizing cycles are then repeated using another stylized pulse, usually under enhanced vibration. See also Figure 2 〇 ° Also note that the optional pre-charge period may precede the period shown, during the pre-charge period, the drain side channel may be partially charged (precharged) (for example) 丨 5_ 3 V bits The line voltage is transferred to the channel by opening (provided in the conduction state) the drain select gate. Typically, 〇 V is applied to 131225.doc -27- 200903499 during pre-charging:: The bit line voltage of the selected NAND string does not always have to be. / In other words, the v- of the selected NAND string can be (for example) (MV. For the = suppression NAND string, in the case of pre-charging the channel, even before the start of the upgrade, V - Γ CH-DRA1N can be south At 0 V, but not necessarily equal to i 5_3 V, because the amount of pre-charge depends on the storage (4) of the erased VTH; t. If the storage element is wiped off very cold, the pre-charge can actually reach the ...v level. Typical precharge levels are in the range of 1 _2 v.

Waveform 800 depicts, in a simplified representation, a bit line voltage VBL for a suppressed (unselected) nand string, a drain select voltage V(10) for a (four) nanostring set, and a (four) set of The common source is the electric left VS0URCE. In practice, 'Vs〇urc—needs equal to V(10) and there may be a timing difference between these waveforms. Waveform 805 depicts the bit line voltage Vbl for the selected NAND string and the source select gate voltage Vsgs that are common to the set of strings. In an alternative, the VBL of the selected bit line may have more than one level. For example, in a fast pass write embodiment, two levels are typically utilized, such as 〇 ¥ and a higher level, typically V. First, 0 V is used to allow for faster stylization, and then a more accurate level is used to provide more precise control of the threshold voltage of the programmed storage element that has reached the target threshold voltage. Waveform 810 depicts the voltage applied to the word lines on the drain side of the selected word line. WLi represents the second or highest word line, and WLn+1 represents the word line adjacent to the selected word line (WLn) on the drain side. Waveform 8 1 5 depicts the voltage applied to the selected word line (WLn). Waveform 82 〇 depicts the voltage applied to the isolated word line (WLn - 丨) of the selected word line on the source side. Waveform 825 depicts the voltage applied to the word line (trade 〇 to WLn_2) on the source side of word line WLn-1 from 131225.doc -28-200903499. Waveforms 830 and 835 depict channel potentials (Vch-source) in the channels of the suppressed NAND string and the selected NAND string present on the source side of the isolated word line, respectively. Waveforms 840 and 845 depict channel potentials (vCH_DRA1N) for the suppressed NAND string and the selected NAND string in the channel of the substrate on the drain side of the isolated word line, respectively. Note how Vchdrain (waveform 84〇) is tracked, / And the extreme side k-liter voltage (waveform 8 1 〇) and the program voltage (waveform 8 1 5). The extent to which the program voltage contributes to the buckle side lift depends on the number of storage elements at the drain side. In the case of fewer storage elements at the drain side, the program voltage has a greater effect on the trip side lift. In addition, note that during source side boost, Vchdrain (waveform 84〇) increases slightly at t1 because the electrons in the drain side channel flow to the source side, effectively before VPASS is applied to the pole side word line. This causes some elevation of the drain side channel, as discussed previously. Along the bottom of the timeline is the time point t〇_t9. In detail, at (7), as indicated by the waveform scheme, the VBL and VsGD of the suppressed (unselected) nand string are increased from 0 v to, for example, 1.5.3 V. Also, VS0URCE is increased from, for example, 0·5 1.5 to 1.5 V in the case of VSGS4〇 ν (waveform 8〇5), which ensures that the source selection of all NAND strings is kept off and & For the selected nand string, Vbl=〇 (or slightly higher for the fast-read bucket λ Γ, 迷 by the writing embodiment), so that VSGD=1 ·5-3 V 愔 丁, η

In the case of '> and the pole selection gate is opened to allow for stylization. Although the example of the tampering corresponds to the boost mode of Figure 5a, substantially any type of tampering scheme utilizing one or more of the selected word, wrap/origin side or one of the isolated word lines can be utilized. For example, the example can be utilized in combination with the region 131225.doc -29-200903499 Self Lifting (LSB) and/or Revised LSB (RLSB) boost mode. In the LSB-like mode, one or more isolated word lines may also be present on the non-polar side such that the word lines adjacent to the selected word line are Qv or other isolation voltage, and VpAss or the supply is supplied to the remaining unselected word lines. Other voltages as described. R L S B is similar to R E A S B. The intermediate voltage VLQW is supplied to the tight (four) and source side word lines of the isolated word line, and the other voltages described in the VpAssg text are supplied to the remaining unselected word lines. At ti, vC0ND is applied to the hunger machine "so that the associated storage element is turned on (eg, provided in a conductive state). This allows the source side of the isolated word line (WLn_1) and the selected word in the NAND string) Charge transfer between the line side of the line (WLn). At t2, the boost of the source side channel (waveform 825) is initiated by applying VpASS to WL〇iWLn_2. As depicted, relative to Vc〇nd The VPASS is delayed to ensure that the source side channel is connected to the drain side channel when the source side is lifted. The nand string channel on the source side of the isolation word line is isolated by voltage boosting. Note that the corresponding increase of vCH-S0URCE (waveform 83) 〇). In the channel region associated with +1 to WLi in the stylized sequence on the side of the selected word line after the selected word line, due to, for example, the applied 〇¥ The voltage is prevented from increasing. However, some improvement may have occurred due to the flow from the drain side to the electrons on the boosted source side. Between 12 and 〇, the source side channel is k liters. After t3 Applying vIS0 to close the associated storage element of the isolated word line (WLn_i), thereby blocking the NAN The charge transfer between the source side of the isolated word line (1^_1) and the drain side of the selected word line (WLn) in the D string. In order to ensure that js WLn-1 has reached the VIS0 level After the delay, and 131225.doc -30- 200903499 starts at the Η, the lifting of the immersed side channel is initiated by the application (waveform 8(9). Note the corresponding increase of VCH-DRAiN (waveform please). Source and drain The lifting of the side channel continues until and until t8. In addition, at t5, VpGM1 is applied to WLn, and at 16, νρ_ is applied to ·. Therefore, initially at the first level and then at a higher level The second level applies a program voltage. This method avoids a sudden change in vCH_DRAIN 'which can be caused by a sudden change in ν_. However, a single stepped %(10) pulse can be utilized. Also note that in some embodiments, VpGMi can be equal to And in this case, the time between Η and t5 may be equal to zero, such that υν_ is substantially ramped up by %. At t7, the program voltage is removed, the boost voltage is removed at 'where, and at t9, The promotion and stylization loop ends. Therefore, the source side rise occurs between tl and And the application of the voltage of the storage element associated with the I and WLn-Ι between the (10)^ is caused by the application of the voltage between the source side and the (10)^. Charge transfer can occur between the source side channel and the drain side channel. For example, many of the electrons in the drain side channel will flow to the source side, effectively causing VPASS to be applied to the drain side word line. Some lifting of the bungee side channel. In addition, the removal of the 乂(3) 仙 before the start of the bungee side lift is used to isolate the subsequent drain side lift of the suppressed channel from the source side. Figure 7 depicts a timeline of word lines and other voltages based on the self-boost mode of Figure 5b. The time line of FIG. 7 differs from the time line of FIG. 7 in that the word line WLn+i on the drain side of the selected word line WLn and adjacent to the selected word line is received between 11 and 13\ ^〇1>113 instead of 〇\^ (waveform 812). This method can be utilized, for example, in the partial programming of non-volatile storage elements associated with WLn+1 at 131225.doc -31 - 200903499. In addition, word line 1 between the selected word line WLn and the isolated word line WLn-2 receives V_ between Μ and t8, where V_>Vls. (Waveform 8i7). This is provided on the - or multi-time line from ν_2 to ~. Gradually change. The shape 810 is then applied to WLn+uWu, the waveform 82〇 is applied to WLn-2, and the waveform 825 is applied to WL〇 to WLn_3.

It is also possible to change the level of the VC0ND for the different word lines to which it is applied. For example, vCOND can be set based on the stylized state of the corresponding non-volatile storage element. vCOND can be higher when the associated non-volatile storage element has a higher programmed state and can be lower when the associated non-volatile storage element has a lower programmed state. The VC0ND only needs to be high enough to create a conduction path between the source side channel region and the drain side channel region. Provides flexibility for different Vc〇ND levels to resolve data type dependencies. Depending on the type of the back (eg, data type), as an example, WLn+1 can be in the lower-middle state B' (Fig. 18a), while the word lines below WLn and WLn can be in the shape of C (Figure 1). 8 c) 'It is the highest stylized state. In this case, VC0ND_L0W& can be added to WLn+Ι' and 乂(3)-- can be applied to WLn_ 2 to WLn ' where Vc 〇 ND - HIGH > Vc 〇 lSiD - LOW. Figure 8 depicts a timeline of word lines and other voltages based on the self-boost mode of Figure 5C. The time line of FIG. 8 differs from the time line of FIG. 7 in that the word line wLn-1 on the source side of the selected word line WLn and adjacent to the selected word line receives VpAss between t4 and t8. Instead of Vlow (waveform 8 1 6). Waveform 8 17 is then applied to WLn-2, waveform 820 is applied to WLn-3, and waveform 825 is applied to WL0 through WLn-4. This provides an even higher gradual transition from 131225.doc -32 - 200903499 VPGM2 to vIS0 on one or more intermediate word lines. As an alternative to being available'', for example, when not associated with a non-volatile storage element, w can be applied to WLn+1 between t_3. Figure 9 depicts green as a timeline for word lines and other voltages as an alternative to the timeline of Figure 8. The timeline of Figure 9 differs from the timeline of Figure 8 in that the voltage is gradually changed from 乂(3)(4) to the subsequent voltage, for example, on the why from %_ to VpASS (waveform 9 i 2) and on the machine i From %_ to (waveform 916), from Vc〇ND to VpG(4) (waveform 915) on WLn, and/or from Vcond to VL0W (waveform 917) on WLn. During the period between t3 and ’, the voltage can therefore ramp up or down from v_d to VPASS or vLOW between the source and the immersion side boost transition. The advantage of this method is that it prevents or reduces the GIDL at the VIS0 and/or VL0W word lines. In the above examples of Figures 7 and 8, the VL0W word line is pulled down to 〇 v before the voltage is applied, (10). This can lead to an increase in GIDL, especially in combination with some of the lifting models. The purpose of applying Vl〇w is to reduce the electric field during the boost. However, when the voltage on the Vl〇w word line is reduced from Vc〇nd to 〇 V, the electric field in the neighbor of the sub-line is increased due to the boosted source side, and GIDL can occur. This increase in electric field can be prevented by ramping the signal on the Vl〇w word line directly from Vc〇nd to VLOW. In addition, if VL 〇 w > VCOND, Bessie (for example) may advantageously apply vL0W instead of vC0ND to the word line in the case of the "improvement scheme" of the figure, in which VL0W is applied to WLn-4 And WLn-2, and VIS0 is applied to WLn-3. In this case, in order to reduce the occurrence of 131225.doc -33-200903499 GIDL on WLn_3 (although the word line voltage is changed from Vc〇ND to V丨s〇) Time) or the probability of GIDL (known as Vc〇nd) occurring on wLn_4, it may be preferable to keep wLn_4 biased from the beginning. The similar timeline discussed herein can be used to similarly implement the diagram & The remaining boost mode to % and other boost modes. For example, in the case of the graph % boost mode, as discussed, three or more different channel zones can be upgraded. The third channel region, and thereafter the condition of the second channel region is raised, the first channel region and the third channel region may be raised in the period of the source side lifting in FIGS. 6 to 9, and is referred to as Raising the second passage zone during the bungee side lift period. For lifting the first passage zone, Thereafter, the conditions of the second channel region and the third channel region are jointly raised, and δ' can raise the first channel region in a period called the source side lifting, and can be upgraded in a period called the bungee side lifting. The second channel zone and the third channel zone. For the condition that the first channel zone is raised, and thereafter the third channel zone is raised, and then the second channel zone is raised, the first channel zone can be raised in a period called the source side lifting. The third channel region may be raised in a period after the period called the source side boost and before the period called the drain side lift, and may be raised in the period called the drain side lift Channel area. Figure 10 depicts the stylized process of the source side of the NAND string before the drain side of the NAND string. This process is illustrated in conjunction with the lifting scheme of Figure 8, but many variations are possible. Stylized in steps丨The beginning begins and the word line for stylization is selected at step 1005. The source side boost begins at step 丨〇j 。. At step 1〇丨5, 'VCOND is set to the isolated word line (wLn_3) ) to the drain side of the isolated word line For the stylized farthest word line 131225.doc -34- 200903499 (Ln 1). At step ίο?, set vpAss on the word line on the source side of the isolated word line. In step 1〇25 At this point, 〇v is set on the remaining drain side word lines, for example, WLn+2 to WLi, and at step 1030, the source side boost ends. That is, generally, the raised source side position is maintained but not further boosted. The dipole side lift begins with stylization at step 1035. As explained previously, the drain side lift can be initiated prior to stylization. At step 1040, the voltage is applied to the selected boost mode. Select the word line. At step 1045, a stylized pulse is applied to the selected word line. The bungee side lift and stylized pulses end at step 1〇5〇. A verify operation is performed at step 1055 to determine if the selected storage element has been programmed to a desired target threshold voltage level, for example, Vva, Vvb, or

Vvc (Figure 16). At decision block 1060, if the programming for the current word line is not complete, then at step 1010, the additional source side boost is repeated followed by the bungee side boost and stylized loop. If the stylization for the current word line is completed 'but the stylization for all word lines is not completed, then at decision step 1065', a word line for stylization is selected at step 1 〇 75. If the stylization of the current word line and all of the word lines is completed, the stylization ends at step 1070. Note that in alternative embodiments, word line dependencies may be utilized where a source side boost followed by a drain side boosting boost scheme is used for lower word lines, such as WL0 in a '32 word line NAND string. WL22. A boost scheme that utilizes source side boost followed by a drain side boost can then be used for higher word lines, such as WL23-WL31, where the type of program disturb solved is more problematic. I31225.doc 35- 200903499 Figure 11 - Example of an array 11GG of storage elements (such as Figure} and storage elements shown in Figure 2). Along the line-by-row, bit line 11()6 is summed to the drain terminal i% of the drain select gate of NAND string 11 50. Along each column of the NAND string, the source line 丨丨〇4 can be connected to all of the source terminals (10) of the sinister source selection. An example of a NAND architecture array and its operation as part of a memory system is found in U.S. Patent Nos. 5,57,350, 315, 5,774,397, and 6,046,935.

The array of storage elements is divided into a plurality of storage element blocks. As is common for flash EEPROM systems, the block is an erase unit. That is, each block contains a minimum number of storage elements that are collectively erased. Each block L Wei knife into π no more than one page. The page is a stylized unit. In one embodiment, individual pages may be divided into segments, and the segments may contain a minimum number of storage elements that are written once as a basic stylized operation. One or more data pages are typically stored in a storage element column. One page can store one or more sections. The section includes user data and additional items. The additional item data usually includes the error correction code (Ecc) calculated from the user data of the area. One of the controllers (described below) calculates the ECC when the data is programmed into the array, and also checks the ECC when reading data from the array. Alternatively, the ECC and/or other additional data may be stored in a different page from the user's profile than the user's profile. The user profile section is typically 5 12 bytes, which corresponds to the size of the zone in which the disk drive is stolen. The additional item data is usually an extra 6 to 2 bytes. A large number of pages form a block from any number of 8 pages (for example) up to 32, 64, 12 8 or more pages. In some embodiments an n string 131225.doc -36- 200903499 column contains a block. In the real-off, the memory storage element is erased by: = liter / to erase „ (for example, 14_22v) holding __ ^ the word line of the selected block is grounded, and the source line and the bit line The line is floating. Due to the coupling of the electric valley, the unselected word lines, bits, the selection line and the common source are also as high as the effective part of the erase voltage. Therefore, when the floating pole is electronically suspended by F - Wear: When the 'strong electric field is applied to the selected storage element, the oxidation of the selected storage element. Erasing the data of the selected storage element. When the electron is transferred from the sub-gate to the Sakai area, the selected storage element is limited. The house is lowered. The entire memory array, independent block or another storage element unit can be erased. Figure 12 is a block diagram of a non-volatile memory system using a single column/row decoder and a read/write circuit. The figure illustrates a memory device 1296 having a read/write circuit for reading and storing component pages in parallel, in accordance with an embodiment of the present invention. The memory device (10) can be ... or more Memory die 1298. Memory die 1298 includes two-dimensional memory array array, control The circuit 121 and the read/write circuit =. In some embodiments, the 'storage element array can be three-dimensional. The memory array U00 can be addressed by the word line via the column decoder and can be passed by the bit line via the row decoder. (4) Addressing. The read/write circuit 1265 includes a plurality of sensing blocks 12 () and allows reading or programming of the storage element pages in parallel. The pass control 1250 is included in - or a plurality of memory crystals In the same memory device 1296 (eg, removable memory card), the command and data are transferred between the host and the controller (10) via line 1220 and via the line 131225.doc-37-200903499 way 1218 in the controller Transferring between one or more memory grains a%. The control circuit 丨21〇 cooperates with the read/write circuit 1265 to perform a memory operation on the memory array 1100. The control circuit 121 includes a state machine 1212, a wafer The upper address decoder 1214, the boost control 1215, and the power control module 1216. The state machine 1212 provides wafer level control of the memory operation. The on-chip address decoder 12 14 is located at the address utilized by the host or the memory controller. Decoder 1 An address interface is provided between the hardware addresses utilized by 230 and 1260. The boost control can be used to set the boost mode, including determining the timing for the deceleration side and the bungee jump, as discussed herein. Power Control Module 1216 Controlling the power and voltage supplied to the word lines and bit lines during memory operation. In some embodiments, the components of Figure 12 can be combined. In various designs η, components can be excluded from the components. One or more of the array coffees (either alone or in combination) are considered as management circuits. For example, one or more management circuits may include control circuit 1210, state machine, decoding ^ 1214/126G, power control module (2) 6. Sensing block 丨, read/write circuit 1265, controller 125 〇, etc., or a combination thereof. The figure shows a block diagram of a non-volatile memory system using a dual column/row decoder and a read/write circuit. Here, another configuration of the memory device 1296 shown in Fig. 12 is provided. Access to the memory array and (10) by various peripheral circuits is performed in a symmetrical manner on the opposite side of the array such that the dense lines of the access lines and circuits on each side are reduced by a factor of one. Therefore, the column decoder is divided into column decodings W23 0A and (2) (10), and the row decoder is divided into row decoders 鸠 and 126 〇Β. Similarly, the read/write circuit is divided into a read/write circuit 1265A connected to the bit line from the bottom of the array U00, and a read/write circuit 1265A connected to the bit line from the top of the array U00. The read/write circuit 丨 265B. In this way, the degree of reading/writing of the module is substantially reduced by half. The apparatus of Fig. 13 as described above with respect to the apparatus of Fig. 12 may also include a controller. 14 is a block diagram depicting one embodiment of a sensing block. The individual sensing blocks 1 200 are divided into a core portion called a sensing module 128 and a common portion 1290. In one embodiment, an independent sensing module 1280 will be present for each bit line, and a common portion 1290 will exist for the collection of multiple sensing modules 128A. In one example, a sensing block will include a common portion 1290 and eight sensing modules 128A. Each of the sensing modules in the group will communicate with the associated common portion via the data bus 272. For other details, refer to the US Patent entitled "N〇n_v〇latile Memory and Method with Shared Processing for an Aggregate of Sense Amplifiers" published on the following day of June, 6th, and is incorporated by reference in its entirety. The application publication No. 2〇〇6/〇14〇〇〇7. The sensing module 1280 includes a sensing circuit 127〇, and the sensing circuit 127 determines whether the conduction current in the connected bit line is higher or lower. The sensing module 1280 also includes a bit line latch 丨282, and the bit line latch 1282 is used to set the voltage condition on the connected bit line. For example, The predetermined state latched in the bit it line latch 1282 will cause a connection: the element line is pulled to a specified program suppressed state (eg, 1 5_3 V). The common part i 290 includes the processor 1292, the data latch The set of devices 1294, and the I/O interface 1296 coupled between the data latch set 1294 and the data bus a: The processor 1292 performs the calculation. For example, its function 131225.doc -39- 200903499 In order to determine the γ judgment in the residual measurement, the test is stored. The data in the component, and the d 疋 疋 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 It is also used to store the shells imported from the data bus 1220 during the program operation. The m-bed field in the imported entity indicates that the desire is stylized to memory from the bedding. 1/〇 interface 1296 provides an interface between the data latch 1294 and the data bus 1220. During the reading or sensing period, the dozer 4 is under the control of the state machine 1 2 1 2 'state machine 1 2 12 control Different #打,丨斗么U衩 gate voltage to the supply of the addressed storage element. Because the sensing module 12 8 0 step 诵Μ # $ < 7 retreat corresponds to the various memories supported by the memory The various states of the body state pre-modulate the gate voltage, so the sensing module 1280 can trip under one of the voltages and will output the self-sensing mode via the busbar 272. Group 128〇 is provided to the processor (4). In the case of the processor 1292, by considering the sensing module The off event and the information about the control gate voltage applied from the state machine via input line 1293 determine the state of the memory. It then calculates the binary encoding for the memory state and stores the resulting data bit to the data latch. In another embodiment of the core portion, bit line latch 1282 provides dual use as both a latch for latching the output of sensing module 1 280 and also as described above. The bit line latch. It is contemplated that some embodiments will include multiple processors 1292. In one embodiment, each processor 1292 will include an output line (not depicted) such that each of the output lines is wired-OR. In some embodiments, the rounds are inverted before being connected to a line or line. This configuration enables a quick determination of when the stylization process has been completed during the verification process of the program 131225.doc -40. 200903499, since the receive line or state machine can determine when all of the stylized bits have reached the desired level. For example, when each bit has reached its desired level, the logic used for that bit will be sent to the line or line (or the data is inverted). When all bits output data 0 (inverted data lm, the state machine knows to terminate the stylization process. Because each processor communicates with eight sensing modules, the state machine needs to read lines or line people, Or adding the logic to the processor 2 to accumulate the result of the associated bit line 'so that the state machine only f reads the line or line-time. Similarly, by correctly selecting the logic level, the global state machine can accumulate the first - When bit it changes its state and changes the algorithm accordingly. During program or verification, the data to be programmed is stored in data latch set 1294 from data bus 1220. Under the control of the state machine, the program operates A series of patterned electric house pulses applied to the control closed end of the addressed storage element. Each stylized pulse is then read back (verified) to determine if the storage element has been programmed to the desired memory state. 292 monitors the read back memory state relative to the desired memory state. The two 'processors' 292 set the bit line latches so that the bit lines are pulled to the state of the program suppression. (4) The heart-to-line storage component enters the syllabic pulse on its control electrode. In other embodiments, during the verification process, the processor initially loads the bit line to latch the crying 9 s 9 α Sub-1282, and the sensing circuit sets it to a value. The lean latch stack 1294 contains a data latch number stack corresponding to the sense group. In the embodiment, each sensor module 128 is Three data latches 131225.doc • 41 - 200903499. In some embodiments, (but not the required shift temporary), so that it will be implemented in the following:: sentence storage 11 is implemented as a series of material bus 1220 The secondary pole, the 仃 data is converted into the capital, and the slanting ridge, the scallop, and vice versa. In the preferred embodiment, all the shackles of the reading/writing block of the asset storage component are The registers are coupled together to form a block shift register so that the data block can be input or output by means of transfer. In particular, the group having r read/write modules is adapted such that its data lock Each in the set of registers - the data is moved into or out of the data bus in turn, > the same for the whole A portion of the shift register of the fetch/write block. Additional information regarding the structure and/or operation of various embodiments of the non-volatile storage device can be found in: 〇) 2〇〇7年3 The title of "Non-Volatile Memory And Method With Reduced Source Line Bias Errors" was published on the 27th of June, and was published on April 4, 2002. The title is N〇 U.S. Patent No. 7, 〇23, 736; (3) May 16, 2006 issued under the heading "improved Memory Sensing Circuit And Method For Low Voltage Operation" US Patent 7,046,568; (4) Published on August 5, 2006, titled "Compensating for Coupling During Read Operations of Non-Volatile Memory", US Patent Application Publication No. 2006/0221692; and (5) Title published on July 20, 2006 For 1'Reference Sense

U.S. Patent Application Publication No. 20060158947 to Amplifier For Non-Volatile Memory. All of the five patent documents listed above are hereby incorporated by reference in their entirety herein. 5 e ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ An example is described as a NAND flash EEpR 〇M divided into (10) blocks. It can be erased and stored in each block at the same time = 枓: In the embodiment, the block is the smallest memory element that is erased at the same time.

仵Single 7G ° In this example, there are 8 512 rows corresponding to the bit line in the block of the Xixia 纟·% £ :, BL1........BL8511. In the implementation of the all-in-one, qing L) architecture ((4) 151G), all the bit lines of the block can be selected simultaneously between reading and program money. Storage elements along a common sub-line and connected to any bit line can be programmed simultaneously. In the example provided, four storage elements are connected in series to form a NAND string. (d) Four storage elements are shown to be included in each -n survey but may utilize more than four or fewer than four storage elements (eg, 16, 32, 64 or another number) One of the series terminals is connected to the corresponding bit line ' via the gateless selection gate (connected to the selected (four) pole drain line SGD) and the other terminal is connected to the selected gate source line SGS via the source (selected gate source line SGS) And connected to a common source.

In another embodiment, referred to as an odd-even architecture (Architecture 15A), the bit lines are divided into even bit lines (BLe) and odd bit lines (BL〇). In an odd/even bit line architecture, storage elements along a common word line and connected to odd bit lines are programmed at one time, while storage elements along a common word line and connected to even bit lines are in another Stylized for a while. In this example, there are 8,512 rows divided into even rows and odd rows in each block. In this example, four storage elements are shown connected in series to form a NAND 131225.doc -43- 200903499 string. Although four storage elements are shown as being included in each I-string, more than four or fewer than four storage elements may be utilized. In the configuration of one of the read and program operations, 4,256 storage elements are simultaneously selected. The selected storage elements have the same word line and the same type of line (e.g., even or odd). Therefore, 532 data bytes of the logical page can be simultaneously read or programmed, and at least eight logical pages of one block of memory (four words, each of which has 14 pages) have odd pages and Even page). In the case of a multi-state storage element, when each storage element stores two data bits (where each of the two bits is stored in a different page), one block stores sixteen logical pages. Blocks and pages of other sizes can also be used. For an ABL or parity architecture, the storage element can be erased by raising the well to an erase voltage (e.g., 20 V) and grounding the word line of the selected block. The source line and the bit line are floating. Erasing can be performed on the entire memory array, the independent block, or another unit of the storage element that is part of the memory device. The floating gate of the electronic self-storage component is transferred to the p-well region such that the VTH of the storage component becomes negative. During read and verify operations, the select gates (SGD and SGS) are connected to voltages in the range of 2.5 to 4.5 V, and unselected word lines (eg, WLO, WL1, and WL3 when the selected word line is selected) Raising to the read pass voltage VrEAD (typically a voltage in the range of 4.5 to 6 V) to operate the transistor as a pass gate. The selected word line WL2 is coupled to a voltage that is specified for each read and verify operation to determine if the VTH of the associated memory element is above or below this level. For example, in the case of 131225.doc -44 - 200903499 = quasi-storage reading of the operating towel, the selected word line machine 2 can be grounded, / whether VTH is detected to be higher than 0 V. In the verification for the two quasi-storage elements, the selected word line WL2 is connected to, for example, G8 v, n verifying that ^ = at least 0.8V. Source and well, at 0V. Pre-charging the selected bit line (the foot line is an even bit line (BLe)) to, for example, the level of 〇7 V. If Vt„ is higher than the reading or verifying level on the word line, then The potential level of the bit line (BLe) associated with the storage element maintains the surface level due to the non-transmission (four) storage element. On the other hand, \r in: ΤΗ is lower than the face extraction or verification level, then the relevant bit line The potential level of (BLe) is reduced to a low level, for example, less than 0.5 V, because the conduction storage element discharges the bit line. This can be used by the Μ comparator sense amplifier connected to the bit line. State of the component 0 is performed in accordance with techniques known in the art to perform the erasing, decimation, and inspection operations described above. Thus, those skilled in the art can change the interpretation.

Many details in the details. Other erase, read, and verify techniques known in the art can also be utilized. Figure 16 depicts an example set of threshold voltage distribution & single process stylization. An instance VTH distribution of the array of storage elements is provided for the condition that two data bits are stored for each storage element. Providing a first threshold voltage knife E for the erased storage element and three threshold voltage distributions AB and C for the stylized storage element of the seven fields, in one embodiment, the threshold voltage in the £ distribution is negative, and The threshold voltage in the A, B, and C distributions is positive. Every phase. The threshold voltage range corresponds to a predetermined value of the data 4 epoch set. The specific relationship between the data stored in the storage component and the threshold voltage level of the storage component 131225.doc -45- 200903499 can be seen in the case of the storage component. U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2/4,255, filed on Dec. 16, 2004, the disclosure of which is incorporated herein by reference. The cases are hereby incorporated by reference in their entirety. In an embodiment, the data value is assigned to the threshold voltage range using a Gray code assignment such that if the floating: extreme threshold voltage is erroneously shifted to its neighboring entity state, then only ~a bits will be 70. An instance assigns "11, to the threshold voltage range E (state E), assigns "10" to the threshold voltage range A (state a), and assigns "〇〇" to the L-limit voltage range B (state B), and assign "〇1 " to the threshold voltage range C (state C). The wipes are not in the other embodiments. Although the four states are not exhibited, the present invention can also be utilized with other multi-state structures including those having more than four or six state structures of four. Three read reference voltages Vra, Vrb, and Vrc are also provided for self-storage - picking of the material. The state in which the storage element is located (e.g., stylized conditions) can be determined by testing whether the threshold voltage of a given storage element is above or below Vra'. In addition, three verification reference voltages Vva, Vvb & vve are provided. When staging storage elements to state A, the system will test if their storage elements have a power limit greater than or equal to Vva. # Program the storage component to state_, the system will test whether the storage component has a threshold voltage greater than or equal to Vvb. When the memory (4) is programmed to state (4), the system will determine if the component has its threshold voltage greater than or equal to Vve. I3l225.doc -46 - 200903499 In one embodiment referred to as full sequence stylization, the storage element can be directly programmed from the erase state E to any of the stylized states A, B*c. For example, the population of storage elements to be programmed may be erased first so that all storage elements in the population are erased. A series of stylized pulses as depicted by the control gate voltage sequence of Figure 20 will then be used to program the storage elements directly to state A, 3 or 〇. Some of the storage elements are programmed from state E to state set, and other storage elements are programmed from state to state B and/or from state E to state c. When the state is programmed from the state to the state c, the amount of parasitic fit to the bottom of the ww reaches the maximum, because the amount of charge on the floating pole of the milk is changed and the program is in the state E. The change in charge when the state A or the self-pattern w is programmed to the state B is the largest. When the state is flavored to state B, the amount of the approach to the adjacent floating idle is less. When staging from state E to state a, the amount of consumption is even reduced. Figure (7) shows an example of a two-process technique for stylized multi-state storage elements that store data for two different pages: the lower page and the upper page. Four states are depicted: state E(1)), state A(10), state B(〇〇), and state C(01). For the case tE, both pages store "1". For state A, the lower page is "〇" and the upper page is stored ", for state B, 'two pages are stored, 〇" . For status c, the page stores "1" and the upper page stores 丨丨〇丨丨. , 七立 ^ ^ Only 砵仔〇. Note that although a particular bit pattern has been assigned to each of the states', different bit patterns can also be assigned. In the first stylization process, the threshold voltage level of the six-storage component is based on the program to be converted to the lower logical page. If the bit is logic 131225.doc -47- 200903499 "ι" ’, the threshold voltage does not change because it is in the proper shape ‘% because it has been erased earlier. However, if the bit to be programmed is logical, 〇", then the threshold level of the storage element is increased to be in state A, as indicated by arrow 17〇〇. It ends the first stylization process. In the second stylization process, the threshold voltage level of the storage element is set according to the bits that are programmed into the upper logical page. ^The upper logical page bit will store the logic "1", then no stylization will occur, because the storage element is in state E or A - this depends on the stylization of the lower page bit, two u @ ± . If the upper f-bit will be a logical "〇", then the threshold voltage shifts. If the first process causes the storage element to remain in the erased state E, then in the second phase, the storage element is programmed to make the threshold The voltage is increased in the state as depicted by arrow 172. If the storage element has been programmed to state A due to the first stylization process, the storage element is further stylized in the first process, causing the threshold voltage to increase In state B, 'as depicted by arrow 1710. The result of the second process is to program the storage element to the state specified to store the logical "〇" for the upper page without changing the information of the lower page. In Figure 16 and Figure, the amount of coupling to the floating gates on adjacent word lines depends on the final state. In one implementation, if enough data is written to fill the entire page, the system can be set to execute the full Sequence write. If the full page is not written to the full: data 'the stylization process can (4) the received data to program the next page stylized. When receiving the follow-up capital (four) 'the system will then program the upper page In yet another In the example, the system can start writing in the mode of the programmed lower page and then receive enough data to fill the storage elements of the entire word line (or 131225.doc -48-200903499 most of the word line). Switch to full-serial stylized mode. The US Patent Application Publication No. 2〇〇6/, published on June 15, 2002, is titled "Pipelined pr〇gramming 〇f Non-Volatile Memories Using EaHy DaU" Further details of this embodiment are disclosed in pp. 126,390, which is hereby incorporated by reference in its entirety in its entirety. Reducing the floating gate to floating gate coupling effect: for any particular storage element, after writing to an adjacent storage element for a previous page, writing to a particular storage element relative to a particular page. In an example embodiment A non-volatile storage element utilizes four data states and stores two data bits per storage element. For example, assume that state e is erased and states A and BAC are stylized. Store data η. State a stores data 01. State B stores data 1 状态 state c stores data 00. This is an example of non-Gray coding because both bits change between adjacent centers A and B. Other codes of data can be used to the status of the physical data. Each storage element stores two data pages. For reference purposes, these data pages are referred to as upper and lower pages; however, they can be given other marks. The upper page stores the bit 〇 and the lower page stores the state B, the upper page stores the bit 】 and the lower page stores the bit. For the state C ' both pages store the bit 〇. The process is a two-step process . In the first step, stylize the lower part. The lower right page will keep the data ι, then store the component shape. 2: The poor material is to be programmed. , the power plant threshold of the storage component is increased, and the storage component is programmed to state B. Figure shows the storage unit 131225.doc •49· 200903499 Stylized from state E to shape·% B. State B, which is the temporary state b; therefore, the verification point is depicted as Vvb1, which is lower than \rvb. In one embodiment, after the storage element is programmed from state E to state B, its neighboring storage elements (WLn+1) in the NAND string will then be programmed relative to its lower page. For example, referring back to Figure 2, after the lower page of the storage element 106 is programmed, the lower page of the storage element ι4 will be programmed. After staging the storage element 104, if the storage element ι4 has a threshold voltage that rises from state E to state B', the floating gate-to-floating gate coupling effect will cause the storage element 1〇6 to look The voltage limit is increased. This will have the effect of widening the threshold voltage distribution of state B to the threshold voltage distribution of the threshold voltage distribution 185 of the graph (10). This apparent widening of the threshold voltage distribution will be corrected when the upper page is programmed. Figure... depicts the process of stylizing the upper page. If the storage element is in erased state E and the upper page will remain at! , the storage element will remain in state E. If the storage element is in state E and its upper page data is to be programmed to 〇, then the threshold voltage of the storage element will rise so that the storage element is in the middle of the energy distribution 185° and the upper page is ^: Hold at 1, the storage element will be programmed to final state B. If the health component is in the middle threshold voltage distribution 185〇 and the data 0 ’ is stored, the component is stored in the factory. The meal is in the form of C Γ The voltage will rise so that the storage component is located. The process-synthesis effect depicted by Figures 18a through 18c, since only the upper portion of the storage element will have an effect on the given instance of the code. An alternative state is exemplified by moving from distribution (10) to state c, I31225.doc •50·200903499 when the upper page data is 1, and moving to state B when the upper page data is zero. Figure 1 8a to Figure 1 8C provide examples of four data states and two data pages 'but the concepts taught can be applied to have more than four or less than four states and more than two or less Other embodiments of two pages. Figure 19 is a flow chart depicting one embodiment of a method for staging non-volatile memory. In one embodiment, the components are erased (in blocks or other units) prior to programming. In step 〇〇9〇〇, the controller issues a "data loading command and the input is received by the control circuit 121A. In the step, the address data of the specified page address is input to the decoder 1214 from the controller or the host. In step 1910, the program data page of the addressed page is entered into the negative buffer for stylization. The data is latched into the appropriate set of latches. In step 1 915, the controller sends the program " command to the state machine 1 2 1 2 . Triggered by the ''Program' command'' will use the stepped program pulse of pulse train 2000 applied to the appropriate selected word line of FIG. 20 to program the data latched in step 丨〇9丨〇 to state machine 1 2 In the selected storage element controlled by 12. In step 1920, the program voltage VpGM is initialized to a start pulse (e.g., 12 V or other value), and the program counter (PC) maintained by the state machine 121 2 is initialized to 0. In step 1925, source boosting is applied, as previously discussed. At step 1930, a first VpGM pulse is applied to the selected word line to begin programming the storage elements associated with the selected word line, and The pole side boost, as previously discussed. If the logic "〇" is stored in a particular data latch indicating that the corresponding storage element should be programmed, then the corresponding bit line is grounded. On the other hand, if the logic "1" is stored in In the specific latch, indicate the corresponding storage 131225.doc -51 - 200903499 The cow should maintain its pre-data status, then the corresponding bit v will be suppressed to stylize. In the 1935 order, verify the status of the selected storage element. Save If the target's target power limit has reached the appropriate level, the data in the memory: memory will be changed to logic T. If the detection of Pro:, 〇, to the appropriate level, then the data will not be stored in the corresponding data. The data in the latch 3|. With this t bucket ' „ ^ f beneficial logic, ρ bit 7 is stored in the corresponding data latch, 铒 1 bit line. When all data latches store a logical "Ρ" state machine (via the line or type mechanism described above), it is known that all selected memory items have been programmed. In step 1940, 'on all data locks' Whether the memory stores a check of logic "1". If all data is latched, the logic is "successful" and the program is successfully completed, because all the stored conditions have been programmed and verified. In step 1945, the report is passed. State. In some embodiments, even if all selected storage elements are not verified during stylization, the stylization process is considered to be complete and successful. In this case, it is known that subsequent operations are caused by insufficiently programmed storage elements. Errors during reading are read. However, such errors can be corrected by ECC. " Right In step 1940, it is determined that not all data latches store logic "1^" and the stylization process continues. In some embodiments, the program process stops even if not all of the data latches store logic. In step mo, the program counter PC is checked against the program limit value Pcmax. An example of a process limit value is twenty; however, other numbers may also be utilized. If the program count HPC is not less than PCmax, the program process has failed and the "failure" status is reported in step 1955. If the program counter PC is less than PCmax, 131225.doc -52· 200903499 increments VpGM in step I960 and The program counter pc is incremented. The process then loops back to step 1930 to apply the next VpGM pulse. Figure 20 depicts an example pulse train 2〇〇〇 applied to the control gate of the non-volatile storage element during stylization, and The boost mode switching occurs during the burst. The burst 2000 includes a series of program pulses 2005, 2010, 2015, 2020, 2025, 2〇30, 2035, 2040, 2045 applied to the word line selected for programming. 2050 . . . In one embodiment, the stylized pulse has a voltage VpGM that begins at 12 v and increments (eg, 0.5 volts) for each successive stylized pulse until it reaches For example, the maximum value of 20-25 V. Between the program pulses is an example of a verification pulse & the s pulse collection 2006 includes three verification pulses. In some embodiments, the data is programmed. Chemical There may be one verify pulse for each of the states (eg, states A, B, and C.) In other embodiments, there may be more or fewer verify pulses. For example, the verify pulse in each set may have Vva, The amplitude of Vvb and Vvc (Fig. 17) or Vvb, (Fig. 18a). As mentioned, when stylization occurs, for example, 'before or during the program pulse, a voltage applied to the word line to implement the boost mode is applied. On the other hand, during the verification process, for example, occurring between program pulses, no boost voltage is applied. In other words, a read voltage, typically less than the boost voltage, is applied to the unselected word line. The read voltage has an amplitude. The amplitude is sufficient to open the previously stylized storage element in the string when the threshold voltage of the current programmed storage element is compared to the verification level. Describing 0 For the purposes of illustration and description, the present invention is not intended In order to be exhaustive or to limit the invention to the precise description of the detailed description of the disclosure, the descriptions of the above-described teachings, many modifications and variations are possible in the preferred embodiments. The principles of the present invention and the use of the present invention will enable others skilled in the art to best utilize the present invention in the embodiments and in the particular application. The present invention is intended to define the scope of the present invention by the scope of the present invention. The application of the invention is hereby incorporated by reference. FIG. 1 is a top view of a NAND string. FIG. 2 is a NAND string of FIG. Equivalent Circuit Diagram Figure 3 is a block diagram of an array of NAND flash memory elements. Figure 4 depicts a cross-sectional view of the sinister string showing the program interference mechanism. Figures 5a through 5h depict different examples of self-elevation modes. Figure 6 depicts a timeline of word lines and other voltages based on the self-boost mode of Figure 5a. Figure 7 depicts a timeline of word lines and other voltages based on the self-boost mode of Figure 5b. Figure 8 depicts a timeline of word lines and other voltages based on the self-boost mode of Figure 5c. Figure 9 depicts a timeline of word lines and other voltages as an alternative to the timeline of Figure 8. Figure 10 depicts the stylized progression of the source side of the NAND string before the drain side of the NAND string. Figure 11 is a block diagram of an array of NAND flash memory elements. Figure 12 is a block diagram of a non-volatile 131225.doc-54-200903499 memory system utilizing a single column/row decoder and a read/write circuit. Non-volatile into the circuit Figure 13 is a block diagram of a dual column/row decoder and a read/write memory system. 14 is a block diagram depicting one embodiment of a sensing block. Memory Rack Figure 15 illustrates an example of the organization of a full bit line memory architecture or a block of suffix arrays to blocks of parity. Figure 16 depicts a set of examples of threshold voltage distribution and single-process stylization.

Figure 17 depicts an example set of threshold voltage distribution and two-process stylization. Figures 18a through 18c show various threshold voltage distributions and describe the process for non-volatile memory. Figure 19 is a diagram depicting a process for staging non-volatile memory. AA_' Figure 20 depicts an example pulse train that applies a gate during stylization. Control to non-volatile storage components [Main component symbol description] 100 transistor 100CG control gate 100FG floating gate 102 transistor 102CG control gate 102FG floating gate 104 transistor 104CG control gate 104FG floating gate 131225.doc 55- 200903499 106 Transistor 106CG Control Gate 106FG Floating Gate 120 Select Gate 120CG Control Gate 122 Select Gate 122CG Control Gate 126 Bit Line 128 Source Line 320 NAND String 321 Bit Line 322 Select Gate 323 '324, 325, 326 storage element 327 select gate 340 NAND string 341 bit line 342 select gate 343 ' 344 , .345, 346 storage element 347 select gate 360 NAND string 361 bit line 362 select gate 363 364 ' * 365 , 366 storage element 367 selection gate - 56 - 131225.doc 200903499 400 404 406 408 , 410 , 412 , 414 , 416 ' 418 , 420 , 422 424 426 800 810 815 820 825 830 835 840 845 1100 1104 1106 1126 1128 1150 1200 1210 NAND string source supply line selection gate storage Piece selection gate bit line waveform waveform waveform waveform waveform waveform waveform NAND storage element array source line bit line 汲 terminal source terminal NAND string sensing block control circuit 131225.doc -57- 200903499 1212 state machine 1214 on-chip address decoding 1215 boost control 1216 power control module 1218 line 1220 lean bus 1250 controller 1260 decoder 1260A row decoder 1260B row decoder 1265 read / write circuit 1265A read / write circuit 1265B read Fetch/write circuit 1270 sense circuit 1272 bus bar 1280 sense module 1282 bit line latch 1290 common part 1292 processor 1293 input line 1294 data latch 1296 memory device 1298 memory die 1500 parity structure 131225.doc -58 - 200903499

1700 1710 1720 1850 2000 2005 ' 2010 2020 ' 2025 2035 , 2040 2050 2006 tO, tl, t2, t5, t6, t7, ABB' BLe BLo BLO, BL1, BL3, BL4, BL8511 CE SGD SGS arrow arrow arrow threshold voltage Distributed pulse train, 2015, program pulse '2030, , 2045, verification pulse set t3, t4, time point t8 't9 state state state even bit line odd bit line BL2 'bit line BL5, state state selection Pole line selection gate source line 131225.doc -59- 200903499 V bl bit line voltage V CH-DRA1N channel potential V CH-SOURCE channel potential V COND voltage V ISO isolation voltage Vlow intermediate voltage VpASS through electric dust V PASS- HIGH high pass voltage V PASS-LOW low pass voltage V PASS-MEDIUM intermediate pass voltage VpGM program voltage VpGM 1 program electric dust VpGM2 program voltage Vra read reference voltage Vrb read reference voltage Vrc read reference voltage VsGD drain select gate Voltage VsGS Source Select Gate Voltage V SOURCE Source Bias V th Threshold Voltage Vva Verify Reference Voltage Vvb Verify Reference Voltage Vvb' Test point Vvc verification reference voltage 131225.doc -60- 200903499

Wli Word Lines WLO, WL1, WL2, Word Lines WL3, WL4, WL5, WL6, WL7, WL63 WLn Selected Word Line WLn-1 Word Line WLn-2 Word Line WLn-3 Word Line WLn-4 Word Line WLn-5 Word Line WLn-6 Word Line WLn-7 Word Line WLn-8 Word Line WLn+1 Word Line WLn+2 Word Line WLn+3 Word Line WLn+4 Word Line 131225.doc -61 -

Claims (1)

200903499 X. Patent Application: 1. A method for operating a non-volatile memory, comprising: one of a first word line before lifting at least one NAND string on one of the second word lines Performing the first-upward of the at least one nand string on the source side, the second word line is on the drain side of the first word line, and includes a plurality of words of the first word line and the second word line a line associated with the at least nand string, and the at least - NAND string having a plurality of non-volatile storage elements; during the first boost, applying a voltage to the first word line for providing the plurality of non- a first non-volatile storage element in a conductive state associated with the first word line in the volatile storage element, and applying a voltage to the second word line for providing the plurality of non-volatile Storing a non-volatile storage element in a conductive state associated with the second word line in a 7L piece; and performing the up to the drain side of the second word line after the first boost v The second boost of the NAND string, while applying _ A word line is provided for providing the first non-volatile storage element in a non-conducting state, 1 simultaneously applying a voltage of the 字 to the second word line. 2. The method of claim 1, wherein: during the second boosting period, a voltage at a first level is applied to a word line on a (four)-pole side of the first word line in the plurality of word lines The voltage applied to the first word line is applied to a second level less than the first level and (4) at a level greater than the second level is applied to the first word line At least the middle word line between the second word lines. 131225.doc 200903499 3. The method of claim 9, further comprising: during the promotion period: applying an electromigration to at least the word line between the sub-line and the second word line of the plurality of word lines For extracting a plurality of non-volatile storage elements in a conductive state between the first word line and the second sub-line in a conductive state, at least in the - Each of the non-volatile storage elements between the non-volatile storage elements and the non-volatile storage elements is provided in a conductive state. 4. The method of claim 1, further comprising: 5. = a first boost period 'applying a voltage to the second side of the plurality of word lines on the drain side adjacent to the second At least a sub-line of the word line for providing at least one non-volatile storage element adjacent to the second conductive state on the drain side of the second word line of the plurality of non-volatile storage elements . Conducted as in the method of claim 1, the step _ includes: = 弟 - boost period 'will - (d) apply to the plurality of word lines = the first word line set on the drain side of the : word line for avoiding The at least-nand string is raised on the (four) pole side of the sub-line. 6. The method of claim 1, wherein the method further comprises: applying a power house to the plurality of non-numbers of the plurality of word lines on the drain side of the second word line during the first-elevation The volatile storage line is provided to the at least one of the first plurality of word lines in the at least one of the first plurality of word lines. The upper-word line set is used to avoid X: the non-volatile storage element - and the pole side is raised by the second method. The method of claim 1 further includes: during the second lifting period, applying a voltage to the At least one of the first word line and the second word line of the plurality of word line lines for use in the first word after the first word. - Raising the at least one between the lines. For example, the method of claim 1, the step-by-step includes, during the second boosting period: the medium voltage is applied to the - extra word line for providing the -nonstate:: An additional non-volatile storage element, the additional word line being on the first = no-pole side, the second boosting line is an additional word line between the third word line and the additional word line for the at least one ND string On the one side, execute at least = two brothers two liters. 9. A non-volatile storage system comprising: a NAND string having a plurality of non-volatile storage elements; a plurality of word lines communicating with the at least NAND string; and 'one or more control circuits And communicating with the plurality of word lines 1 = a plurality of control circuits: (4) on the 1st side of the - second word line: :=;, - before the NAND string is on the -first side of the -th word line Performing a first boost of the upper string, the second word line is on the first: to the extreme side; (8) during the first boosting period, applying one (four) to the word line to provide the plurality of non-volatile stores The first non-volatile storage element in the - conduction state associated with the first word line of 131225.doc 200903499, and a voltage applied to the second word line to provide the plurality of non-volatile storage a second non-volatile storage element in a conductive state associated with the second word line; and (4) performing the at least one on the non-polar side of the second word line after the first boost The second increase in the string, while applying a voltage to the first word line to provide A non-conducting state of the second - non-volatile storage element, and simultaneously - the program voltage is applied to the second word line. 10. The non-volatile storage system of claim 9 wherein: ▲ during the second boost period, applying a voltage at a first level to/in the plurality of sub-lines at the second word line a word line on the side, the voltage applied to the first word line is applied to the second level a less than the first level, and the voltage at a level greater than the second level is applied to the Xth At least one intermediate word line between the line and the second word line of the β. 11. The non-volatile storage system of claim 9, wherein: during the first boosting period, the one or more control circuits apply a voltage to the plurality of word lines at the second word line A set of word lines on the pole side is used to avoid Φ as a packet r _ + NAND string is reduced on the drain side of the ~ first sub-line. , - Η non-burst storage ... -,,, the target is applied to the second word line to provide the electrical conductivity of the second non-volatile storage component in a conductive state at the - _ level; And the one or more control circuits are applied to the plurality of word lines by a voltage at a level greater than the first level, at the first word line, 13I225.doc 200903499 A set of word lines on the pole side to perform the first boost. 13. The non-volatile storage system of claim 9, wherein: the first word line is added to the first word line to provide the first volatilization in a conductive state The voltage of the storage element is at a first level; and the one or more control circuits are applied to the at least one NAND string by applying a voltage greater than a first level of the first level - Non-volatile: A collection of 70 non-volatile storage elements on the source side of the 70 pieces is stored to perform the first boost. 14. The non-volatile storage system of claim 13, wherein: the one or more control circuits are at a scale less than the first level: r >, live, A two-level voltage is applied to a set of non-volatile storage elements on the x-pole side of the second non-volatile storage element in the plurality of non-volatile euro storage 7L pieces. 1 5. The non-volatile storage system of claim 1, wherein: _ the first or more control circuits apply a voltage at the second level to the at least one _ when the first-up is performed A collection of the non-volatile storage elements on the non-polar side of the second non-volatile storage element in the string. 16· A non-volatile storage system, comprising: a component for performing a first boosting step, wherein the one of the second word line is boosted by at least one of the NAND strings before the -th word line-source Performing at least the first-up of the NAND string on the side, the second word line being on a drain side of the first word line, including the first word line and the second word, the plurality of word lines and The at least string is associated, and the at least 131225.doc 200903499 NAND string has a plurality of non-volatile fault elements; for providing a non-volatile member in the conductive state, the first boost period, applying a wish to the first word a member for providing the plurality of non-volatile storages 1 for extracting a -first non-volatile storage element in a conductive state capable of being associated with the first sub-line, and Adding a voltage yoke to the second word line to be associated with the second word line 胪 + + ^ storage ^ deep associated with a non-volatile storage element in a conductive state; And the younger one is used to perform the second boosting component, i 筮 _~ , after the ° Haidi - soaring Performing a second boost of the at least one of the dice strings on the dipole side of the line, and applying a voltage to the first to prewire for providing the first non-volatile in a non-conducting state The component is stored and a program voltage is applied to the second word line at the same time. 131225.doc