TWI220526B - An operation method of nonvolatile memory array - Google Patents

Abstract

An operation method of nonvolatile memory array is suitable for an NAND memory cell array, wherein each memory cell comprises a charge trapping layer. Using F-N tunneling effect erases the whole nonvolatile memory array, and using hot-hole injection effect programs one bit of one memory cell. Using the F-N tunneling effect to perform the erasing operation, electron injection is more effective, the current flow to the memory cell is lower and the operating speed is thereby increase. The cell current is small during operations, and the power consumption of the whole chip can be significantly reduced.

Description

1220526 _Ά 92106746_ Year of the month., Τ .____ 5. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for operating a non-volatile memory cell array (Non-Volatile Memory Array), and In particular, there is a kind of single-memory cell (1 C e 1 1 2 B its) stored electrically erasable and programmable read-only memory (Electrical ly Erasable

Programmable Read Only Memory (EEPR0M) array operation method. [Prior art] No, the electrically erasable and programmable read-only memory in the memory has ΐ ^ 进 彳 ^ multiple data storage, reading, erasing and other actions, and the stored data is in The advantage that it will not disappear even after power off, so it has become a kind of memory element widely used in personal computers and electronic devices. Electrically erasable and programmable read-only memory system based on Code ^ is made of doped polycrystalline silicon, and a gate (F1 〇at ing Gate) and a control gate (Control t 6) When the memory is stylized (Pr ogr am), the implanted floating gates ^ ^ t will be evenly distributed throughout the polycrystalline silicon floating gate layer. However, Erxi = tunneling under the Shixi floating gate layer When there is a defect in the oxide layer, the loss of electrons stored in the Gu Yi F element is affected, which affects the reliability of the element. In order to solve the electrical leakage of the programmable read-only memory element that can be erased electrically, a charge is used. The trapped layer replaces the polycrystalline silicon floating gate. The material of the trapped layer is, for example, silicon nitride. Here the charge trapped layer goes up and down! There is a layer of oxidized stone and a kind of silicon oxide / silicon nitride / 4 Stacked gate structure including fossil evening (N0) composite layer. ^ Erasable and programmable read-only memory, because silicon nitride has

Page 6 1220526 _Case No. 92106746_ Year Month Date__ V. Description of the invention (2) Capturing the characteristics of electrons and holes, and it will not conduct electricity itself, it is less sensitive to defects in the tunneling oxide layer, and the component is stored The loss of electrons and holes is less likely to occur. In addition, when this type of electrically erasable and programmable read-only memory is programmed, the source / drain region on the first side of the stacked gate can have a higher voltage, The electrons are stored in the charge trapping layer of the source / drain region; and the source / drain region on the second side of the stacked gate can also have a higher voltage, while the source / drain region near the second side can have a higher voltage. Electrons are trapped in the charge trapping layer. Therefore, by changing the voltage applied to the gate and the source / drain regions on either side, two groups of electrons, a single group of electrons, or no electrons can exist in a single charge trapping layer. Therefore, this electrically erasable and programmable read-only memory can write four states in a single memory cell, which is a non-volatile memory with a single memory cell of two bits (2 bits / ce 1 1). body. Generally speaking, this type of electrically erasable and programmable read-only memory system uses the Channel Hot-Electron (CHE) mode to trap electrons into the charge for programming. And after stylization, since the charge trapping layer on the drain side (or source side) has a net negative charge, it will cause the starting voltage (VT) of the memory cell to rise. These electrons will stay in the charge trapping layer for a long time (for example, at 85 ° C for more than ten years) unless they are intentionally erased. During the erasing operation, the hole-to-band hot hole injection (B and-t 〇- B and Η 〇 t ο 1 e I njecti ο n) mode is used to make the hole injection fall into the layer near the nonpolar side (or Source side) and the combination with the electrons stored on this side or the charge offset to achieve erasure

10631twf1.ptc Page 7 1220526

V. Description of the invention (3) After erasing, the electricity that originally existed on the drain side (or source side), which was trapped on the layer, and how the negative electricity was combined or offset, will cause the initial voltage of the memory cell ( VT) is lowered to become an erased state. However, the above-mentioned electrically erasable and program-readable memory is programmed using channel hot electrons, so its electron injection efficiency is very low. Therefore, a higher voltage needs to be applied in the process of formulating to provide a larger current 'and thereby increase the programming rate. However, when the used voltage rises to Case No. 92106746, the reliability and reliability of electronic components (Reliabi 1 ity) will be reduced due to high leakage current and low programming efficiency caused by punch-through. Especially when the size of the memory element is smaller, the situation of high leakage current and low programming efficiency caused by punch-through will be more serious, and the element size will be limited. [Inventive Content] U 1 Therefore, one object of the present invention is to provide a == which can reduce the memory cell current, and another purpose of this month is to provide a, .. + this is enough to early MBit), bytes (B t ), That is, the sector is programmed in units. In order to achieve the above object, the present invention provides a method for operating a column. This non-volatile memory cell array includes a plurality of rows; each row of memory cells in each row is connected in series:; No .:? Electricity; between bodies; each memory cell contains at least a base recognition: &, drain region, charge trapping layer, and gate; complex digital element lines are flat in the row direction

10631twfl.ptc 1220526 _Case No. 92106746_ YYYY__ V. Description of the invention (4) Gates arranged in rows and connected to memory cells in the same row; multiple upper-bit lines are connected to the source of each first selection transistor, respectively ; The plurality of lower bit lines are respectively connected to the drains of the second selection transistors; the first selection gate line is connected to the gate of the first selection transistor in the same row, and the second selection gate line is connected to the second selection transistor in the same row; The gate of the crystal; this method involves applying a first voltage on the character line and a second voltage on the substrate of the memory cell during the erasing operation, where a voltage difference between the first voltage and the second voltage is sufficient for the electrons The charge trapping layer injected into the memory cell is used to erase the entire memory cell array. When performing a stylized operation, a third voltage is applied to the character line to which the selected memory cell is coupled, a fourth voltage is applied to the non-selected character line to open the channel of the memory cell, and a fifth voltage is applied to the selected upper bit line. A sixth voltage is applied to the unselected upper bit line and the lower bit line to program the source-side bits of the memory cell using the thermal hole injection effect. When performing a read operation, a seventh voltage is applied to the character line coupled to the selected memory cell, and an eighth voltage is applied to the non-selected character line to open the channel of the memory cell, and a ninth voltage is applied to the selected bit line. The tenth voltage is applied to the unselected upper bit line and lower bit line to read the source-side bit of the memory cell. The operation method of the non-volatile memory further includes applying a third voltage to the character line to which the selected memory cell is coupled, and applying a fourth voltage to the non-selected character line to open the channel of the memory cell and lower the selected cell. A fifth voltage is applied to the element line, and a sixth voltage is applied to the unselected lower bit line and the upper bit line to program a drain-side bit of one of the memory cells by using a thermal hole injection effect. When performing a read operation, a seventh voltage is applied to the character line to which the selected memory cell is coupled, and an eighth voltage is applied to the unselected character line to open the memory cell.

10631twfl.ptc Page 9 1220526 _Case No. 92106746_ Year and month amendment_ V. Description of the invention (5) Channel, apply the ninth voltage to the selected upper bit line, and apply the tenth to the unselected lower bit line and upper bit line. Voltage to read the drain-side bit of the memory cell. The present invention also provides a method for operating a non-volatile memory cell array, which is suitable for operating a NAND-type memory cell array. The method is to apply a first voltage to a character line and apply a voltage to the substrate of the memory cell during an erase operation The second voltage, wherein a voltage difference between the first voltage and the second voltage is sufficient to cause the charge injected into the memory cell by the electrons to be trapped in the layer to erase the entire memory cell array. In the operation mode of the non-volatile memory cell array of the present invention, it uses the F-N tunneling effect (F-N Tu n n e 1 i n g) to erase the entire memory cells of the array. Then, the thermal hole injection effect is used to program in a single bit of a single memory cell without affecting the programming of other memory cells. Similarly, a single bit can be read from a single memory cell. Of course, the programming and reading operations of the non-volatile memory cell array of the present invention can also be controlled by each word line, select gate line, upper bit line, and lower bit line. Area, or block for programming and reading. In addition, in the operation of the non-volatile memory cell array, the present invention uses the F-N penetrating effect (F-NT u η ne 1 ing) to perform the erasing operation of the memory cells, and uses the thermal hole injection effect to Program the memory cells. Due to the F N -tunneling effect, its electron injection efficiency is high, so it can reduce the memory cell current during erasure, and at the same time, it can increase the operating speed. Therefore, the current consumption is small, which can effectively reduce the power loss of the entire chip.

10631twfl.ptc Page 10 1220526 Amendment _ Case No. 92106746 V. Description of the invention (6) The fart ^ makes the above and other objects, features, and advantages of the present invention clearer-'A preferred embodiment is given below, In conjunction with the attached drawings, the detailed description is as follows: [Embodiment] The first figure of the bean is a schematic circuit diagram of a non-volatile memory cell array. ， 'This non-volatile memory cell array is a N A N D (Reverse Gate) type array. The operation method of the non-volatile memory cell array of the present invention is applicable to a nand (reverse gate) type array. In this embodiment, four rows of NAND memory cells are used as an example for description. Please refer to FIG. 1 'The non-volatile memory cell array includes a plurality of selection transistors STal ~ STdl and STa2 ~ STd2, a plurality of memory cells Qal ~ Qdn, a plurality of word lines WL1 ~ WLn, and a selection gate line SG1 and SG2 . The upper bit lines BLU1 to BLU4 and the lower bit lines BLD1 to BLD4. The memory cells Q a 1 to Q a η form a memory cell array in the direction of the column and are connected in series between the selection transistor STal and the selection transistor STa2. The memory cells Qbl to Qbn form a memory cell array in the direction of the column and are connected in series between the selection transistor STbl and the selection transistor STb2. The memory cells Qcl ~ Qcn form a memory cell array in the direction of the column, and are connected in series between the selection transistor STcl and the selection transistor STc2. The memory cells Q d 1 to Q d η form a memory cell array in the direction of the column and are connected in series between the selection transistor STd1 and the selection transistor STd2. The complex digital element lines are arranged in parallel in the row direction and connected to the gates of the memory cells in the same row. That is, the gates of the memory cells Qal ~ Qdl in the first row are coupled to the corresponding word line WL1. Gates of the second column of memory cells Qa2 ~ Qd2

10631twf1.ptc Page 11 1220526 __Case No. 92106746_ Year, Month, Day, Amendment _ V. Description of the invention (7) is coupled to the corresponding word line WL2. The gates of the third column of memory cells Qa3 ~ Qd3 are connected to the corresponding sub-element line W L 3. The gates of the fourth column of memory cells Q a 4 to Qd4 are coupled to the corresponding word line WL4. By analogy, the gates of the memory cells Qaη ~ Qdn in the ηth column are coupled to the corresponding word line WLn 〇 The gates of the selection transistors STal ~ STdl are coupled to the selected gate line S G 1. The sources of the selection transistors S T a 1 to S T d 1 are respectively coupled to the upper bit lines BLU1 to BLU4. The gates of the selection transistors STa2 to STd2 are coupled to the selection gate line SG2. The drains of the selection transistors STa2 to STd2 are respectively coupled to the lower bit lines BLD1 to BLD4.

Next, please refer to Table 1 and FIGS. 2A to 2D, FIGS. 3A to 3D, and FIGS. 4A to 4D to understand the operation mode of the non-volatile memory cell array of the present invention. Operation modes include (Erase, Figures 2A to 2D), Program (Program, Figures 3A to 3D), and data reading (Read 'Figures 4A to 4D). In the following description, memory cell 2 not shown in Figure 1 is used as an example, and Figures 2B and 2D, Figures 3B and 3D, and Figures 4B and 4D are shown as a single unit. Operating mode of non-volatile memory cells. As shown in Table 1, the erasing method of the present invention is described by taking the erasing of the entire memory cell array 2 as an example. Of course, the non-volatile memory cell array erasing operation of the present invention can also be erased with the nodal area or area as an early bit under the control of each word line. The erasing method of the flute 9 β Ϊ invention can be divided into two types. Please refer to FIG. 2A and the method ′ at the same time. This is to explain the first erasing method of the present invention. Be right

Page 1212526 Amendment_Case No. 92106746 V. Description of the Invention (8) When the memory cell is erased, a bias voltage + Vge is applied to all the word lines WL 1 to w L n (gate 丨 〇8), for example, It is about 0 volts to about 20 volts, and a bias voltage -V b ′ is applied to the substrate 1 () 0, which is, for example, 0 volts to -2 volts. A bias voltage + Vst is applied to the selection gate line SG1, which is, for example, about 5 volts, and a bias voltage + Vdt is applied to the selection gate line SG2, which is, for example, about 5 volts. The upper bit line BLU2 (source 1 1 0) and the lower bit line B L D 2 (drain electrode 丨 2) are respectively biased by 0 volts. Therefore, the voltage difference (0 volts to 40 volts) applied between the gate 108 and the substrate is sufficient to establish a large electric field between the gate 108 and the substrate 100, and the FN penetration effect can be used. (F —N TunneHng) The electrons are injected through the channel through the oxide layer 102 and injected into the charge trapping layer 104 as shown in FIG. 2B. After erasing, there is a net negative charge on the charge trapping layer, so the initial voltage () of the memory cell will rise. Please refer to FIG. 2C and FIG. 2D at the same time, which are used to explain the second erasing method of the present invention. When the entire memory cell is erased, a bias voltage _Vge is applied to all the lines WL1 to WLn (gate 108), which is, for example, about 0 volts to -20 volts. A bias voltage + Vb is applied to the substrate 1 () (), which is, for example, volts to 20 volts. Select gate line SG1, select gate line, upper BLU2 (source 11) and lower bit line BLD2 (drain 112). Voltage difference between gate 108 and substrate 100 (0 volts to -4) The voltage f ^ is used to establish a large electric field between the intermediate electrode 108 and the substrate 100, so that electrons can be injected from the gate 108 through the dielectric layer 106 through the FN tunneling effect (F_N Tunneling) and trapped. In layer 104, as shown in FIG. 2D, since the charge trapping layer 104 has a net negative charge, the initial voltage (ντ) of the ensemble and the memory cell rises.

1220526 ---- Case No. 92106746_Amended Month and Day ___ V. Description of the Invention (9) Please refer to Figure 3A and Figure 3B at the same time. When performing the programmed operation on the memory cell Qb2 drain side bit, A bias voltage -Vgp is applied to the selected word line WL2 (gate 108), which is, for example, about 0 volts to about -15 volts. A bias voltage Vg is applied to the other unselected word lines WL1, WL3 to WLn, which is, for example, about 10 volts to open the channel region of the memory cells. A bias voltage + Vst 'is applied to the selection gate line SG 1, which is, for example, about 5 volts to open the channel of the selection transistor STa and STdl, and the upper bit lines BLU 1 to BLU 4 and the memory cells Q a 1 to Q are respectively The source of d 1 is electrically connected. A bias voltage + Vdt is applied to the selection gate line SG2, which is, for example, about 5 volts to open the channels of the selection transistors STa2 to STd2, and the lower bit lines BLD1 to BLD4 are electrically connected to the drains of the memory cells Qan to Qdn connection. The bias voltage Vdp is applied to the selected lower bit line BLD2 (drain 1 1 2), which is, for example, about 5 volts, and the voltage of the unselected lower bit lines BLD1, BLD3, and BLD4 is 0 volts. The upper bit lines B L U 1 to B L U 4 (source 1 1 0) have a voltage of 0 volts. Under this kind of bias condition, the overlapping area of the gate 108 and the drain 1 12 produces a phenomenon of deep depletion, and due to the high electric field perpendicular to the penetration and the formation layer, it is close to the drain The hole on the pole side can enter the charge trapping layer 104 through the energy barrier that follows the oxide layer (Hot Hole Injection), as shown in FIG. 3B. After stylization, since the negative charge originally existing on the drain-side charge trapping layer 104 is injected into the holes and neutralized, the initial voltage () of the memory cell will drop. When programming the drain side bits of memory cell Q b 2, the drain side bits of memory cells Qa2, Qc2, and Qd2 that share the same word line WL2, because the lower bit lines BLD1, BLD3, and BLD4 Both are 0 volts, so they will not be blocked

1220526 _ Case No. 92106746_ 年月 日 __ V. Description of the invention (10) Similarly, please refer to Figure 3 C and Figure 3 D at the same time. When programming the source side bit of memory cell Q b 2 At this time, a bias voltage -Vgp is applied to the word line WL 2 (gate 108), which is, for example, about 0 volts to about -15 volts. A bias voltage Vg is applied to the other unselected word lines WL1, WL3 to WLn, which is, for example, about 10 volts to open the channel region of the memory cells. A bias voltage + Vst is applied to the selection gate line SG1, which is, for example, about 5 volts to open the channels of the selection transistors STal ~ STdl, so that the upper bit lines BLU1 ~ BLU4 and the source electrodes of the memory cells Qa and Qdl are respectively Sexual connection. A bias voltage + Vdt is applied to the selection gate line SG2, which is, for example, about 5 volts, to open the channels of the selection transistors STa2 to STd2, so that the lower bit lines BLD1 to BLD4 are electrically connected to the drains of the memory cells Qan to Qdn. connection. Apply bias to upper bit line B L U 2 (source 1 1 0)

Vdp 'is, for example, about 5 volts, and the voltage of the unselected upper bit lines BLU1, BLU3, and BLU4 is 0 volts. The lower bit lines BLD1 to BLD4 (drain 112) have a voltage of 0 volts. Under such a bias condition, the overlapping region between the gate 10 and the source 1 10 produces a phenomenon of deep depletion, and it is close to the source side due to the high electric field perpendicular to the penetrating oxide layer. The hole can pass through the energy barrier of the tunneling oxide layer and enter the charge trapping layer 104 (Hot Hole Injection), as shown in FIG. 3D. After stylization, because the negative charge originally existing on the source side is trapped on the layer, how is the negative hole charged by the host to neutralize it, so the initial voltage (V ') of the memory cell will drop. τ When the source side bits of memory cell Qb2 are programmed, the source side bits of memory cells Qa2, Qc2, and Qd2 of the same word line WL2 are shared. Because the upper bit lines BLU1, BLU3, and BLU4 are all 0 volts, so it will not be

1220526 _ Case No. 92106746_ Year Month Day _ Zheng V. Description of the invention (11) Stylized. Moreover, in the above description, although the programming is performed by using a single bit of a single memory cell in the memory element array, the programming of the non-volatile memory cell array of the present invention can also be performed by each word line and a selection gate. The control of the epipolar line, the upper bit line, and the lower bit line is programmed in units of bytes, nodes, or blocks. Please refer to FIG. 4A and FIG. 4B at the same time. When reading the data of the source side bit of the memory cell qb 2, apply a bias voltage + vst to the selection gate line SG 1, which is, for example, about 5 volts. The channels of the selection transistors STal to STdl are opened, and the upper bit lines BLU 1 to BLU 4 are electrically connected to the sources of the memory cells Q a 1 to Q d 1, respectively. A bias voltage + V dt is applied to the selection gate line SG 2, which is, for example, about 5 volts' to open the channels of the selection transistors STa2 to STd2, so that the lower bit lines BLD1 to BLD4 and the memory cells Q a η to Q d, respectively. η is not electrically connected. A bias voltage ν d r of about 1.5 volts is applied to the lower bit line B L D 2 (Waiji 1 1 2). The voltage of the unselected lower bit lines BLD1, BLD3, and BLD4 is 0 volts. The word line WL2 (gate 10) applies a bias voltage Vcc of about 3 volts, and other unselected word lines WL1, WL3 to WLn apply a bias voltage Vg, which is, for example, about 5 volts to open the channel of the memory cell. Area. A bias voltage of 0 volts is applied to the upper bit lines BLU1 to BLU4 (source 1 110). At this time, the channel of the memory cell with a negative total charge amount on the charge trapping layer 〇04 is closed and the current is small, and the channel of the memory cell with the total charge amount which is slightly positive on the charge trapping layer 104 is open and the current is large, so You can judge whether the digital information stored in the memory cell is "1" or Γ 〇 by the channel switch / channel current of the memory cell. ~ Please refer to Figure 4C and Figure 4D at the same time, when reading the memory cell q b 2 drain

Page 16 1220526 _Case No. 92106746_ Revised Year of the Month _ V. Description of the invention (12) When the data of the side bit is selected, a bias voltage + V st is applied to the selection of the gate line SG 1, which is, for example, about 5 volts, and The channels of the selection transistors STal ~ STdl are opened, and the upper bit lines BLU1 ~ BLU4 are electrically connected to the sources of the memory cells Qa and Qdl, respectively. A bias voltage + Vdt is applied to the selection gate line SG2, which is, for example, about 5 volts to open the channels of the selection transistors STa2 to STd2, so that the lower bit lines BLD1 to BLD4 are electrically connected to the drains of the memory cells Qan to Qdn, respectively. connection. A bias voltage Vsr of about 1.5 volts is applied to the upper bit line BLU2 (source 110). The voltage of the unselected upper bit lines BLU1, BLU3, and BLU4 is 0 volts. The word line WL2 (gate 108) applies a bias voltage Vcc, which is, for example, about 3 volts. A bias voltage Vg is applied to the other unselected word lines WL1, WL3 to WLn, which is, for example, about 5 volts to open the channel region of the memory cells. A bias voltage of 0 volts is applied to the lower bit lines B L D 1 to B L D 4 (drain 1 1 0). At this time, the channels of the memory cells with a negative total charge amount on the charge trapping layer 104 are closed and the current is small, while the channels of the memory cells with a slightly positive total charge amount on the charge trapping layer 104 are open and the current is large, so You can judge whether the digital information stored in the memory cell is "1" or "0" by the channel switch / channel current of the memory cell. Moreover, in the above description, although the reading operation is performed by using a single bit of a single memory cell in the memory element array, the reading operation of the non-volatile memory cell array of the present invention can also be performed by each word line, Select the gate line, upper bit line and lower bit line control, and read the data in bytes, nodes, or blocks. In the operation mode of the non-volatile memory cell array of the present invention, it uses the F-N penetrating effect (F-N Tu n n e 1 i n g) to erase the entire memory cells of the array. Then, using the hot hole injection effect

10631twfl.ptc Page 17 1220526 _Case No. 92106746_ Year Month Amendment _ V. Description of the Invention (13) Stylized as a unit without affecting the stylization of other memory cells. Similarly, a single bit can be read from a single memory cell. Of course, the programming and reading operations of the non-volatile memory cell array of the present invention can also be controlled by byte lines, node areas by controlling the word lines, selection gate lines, upper bit lines, and lower bit lines. , Or program and read in units of blocks. In addition, in the operation of the non-volatile memory cell array, the present invention uses the F-N penetrating effect (F-NT u η ne 1 ing) to perform the erasing operation of the memory cells, and uses the thermal hole injection effect to Program the memory cells. Due to the F N -tunneling effect, its electron injection efficiency is high, so it can reduce the memory cell current during erasure, and at the same time, it can increase the operating speed. Therefore, the current consumption is small, which can effectively reduce the power loss of the entire chip. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10631twfl.ptc Page 18 1220526 Case No. 92106746 Means a simple explanation of the modified table. Table 1 is the applied voltage table for the operation modes of erasing, programming and data reading of the non-volatile memory cell array of the present invention; Figure 1 is A schematic circuit diagram of a non-volatile memory cell array is shown; Figures 2A to 2D are schematic diagrams showing the erasing operation of the non-volatile memory cell array of the present invention; Figures 3A to 3D FIG. 4 is a schematic diagram illustrating the stylized operation of the non-volatile memory cell array of the present invention; and FIGS. 4A to 4D are schematic diagrams illustrating the read operation of the non-volatile memory cell array of the present invention. Brief description of drawing numbers: 100 102 104 106 108 110 1 12 BLD1 BLU1 Qal, SG1 STal WL1, substrate penetration and oxide layer charge trapped in the dielectric layer gate source region > and the pole region ~ BLD4 ~ BLU4 Qdn · SG2 :: Lower bit line: Upper bit line memory cell selection gate line STdl > STa2 ~ STd2 WLn: Word line selection transistor

10631twf1.ptc Page 19

Claims (1)

1220526 _ Case No. 92106746_ Year Month__ VI. Application for Patent Scope 1. A method for operating a non-volatile memory cell array, the non-volatile memory cell array includes a plurality of memory cell arrays, each of which The memory cells are connected in series between a first selection transistor and a second selection transistor. Each of the memory cells includes at least a substrate, a source region, a drain region, a charge trapping layer, and a gate electrode. ; The plural digital element lines are arranged in parallel in the row direction and connected to the gates of the memory cells in the same row; the plural upper bit lines are respectively connected to the sources of the first selection transistors; the plural lower bit lines are connected to each Drains of the second selection transistors; a first selection gate line is connected to the gates of the first selection transistors in the same row, and a second selection gate line is connected to the second selection transistors in the same row A gate of a crystal; the method includes applying a first voltage to the character lines and a second voltage to the substrate of the memory cells during the erasing operation, the first voltage and the first voltage Voltage of two voltages The difference is sufficient to cause electrons to be injected into the charge trapping layers of the memory cells to erase the entire memory cell array. When performing a program operation, a third voltage is applied to the word line to which the selected memory cell is coupled. A fourth voltage is applied to the unselected word lines to open the channels of the memory cells, a fifth voltage is applied to the selected upper bit lines, and an unselected upper bit line and the lower bit lines are applied A sixth voltage to program a source-side bit of the memory cell using a thermal hole injection effect; and a seventh voltage is applied to the word line to which the selected memory cell is coupled during a read operation , An eighth voltage is applied to the selected character lines to open the channels of the memory cells, and the selected lower bit line is applied 10631twfl.ptc Page 20 1220526 _Case No. 92106746_ Month and Day__ Sixth, the scope of the patent application is a ninth voltage, and the tenth voltage is applied to the upper bit lines and the lower bit lines without selection to read the The source side of the memory cell. 2. The method for operating a non-volatile memory cell array as described in item 1 of the scope of patent application, further comprising: applying the third voltage to the word line to which the selected memory cell is coupled, and unselecting the Applying the fourth voltage on the word line to open the channels of the memory cells, applying the fifth voltage to the selected lower bit line, and applying the sixth voltage to the unselected lower bit lines and the upper bit lines, One of the memory cells is programmed using the hot hole injection effect to program a drain side bit. 3. The method for operating a non-volatile memory cell array as described in item 2 of the scope of the patent application, further comprising: applying a seventh on the character line to which the selected memory cell is coupled during the reading operation. Voltage, the eighth voltage is applied to the unselected word lines to open the channels of the memory cells, the ninth voltage is applied to the selected upper bit lines, and the lower bit lines and the upper bit lines are not selected The tenth voltage is applied to read the drain-side bit of the memory cell. 4. The method of operating a non-volatile memory cell array as described in item 1 of the patent application range, wherein the voltage difference is from 0 volts to -40 volts. 5. The method for operating a non-volatile memory cell array as described in item 1 of the scope of the patent application, wherein the first voltage is from 0 volts to -20 volts. 6. The method for operating a non-volatile memory cell array as described in item 1 of the scope of the patent application, wherein the second voltage is from 0 volts to 20 volts. 7. The method of operating a non-volatile memory cell array as described in item 1 of the scope of the patent application, wherein the third voltage is from 0 volts to -15 volts. 10631twfl.ptc Page 21 1220526 _ Case No. 92106746 _ Month and Day __ VI. Patent Application Range 8. The method of operating a non-volatile memory cell array as described in item 1 of the patent application range, wherein the fourth voltage is 0 volts to 10 volts. 9. The method for operating a non-volatile memory cell array according to item 1 of the scope of the patent application, wherein the fifth voltage is from 0 volts to 10 volts. I 0 · The method of operating a non-volatile memory cell array as described in item 1 of the patent application range, wherein the sixth voltage is from 0 volts to 10 volts. II. The method of operating a non-volatile memory cell array as described in item 1 of the patent application range, wherein the seventh voltage is from 0 volts to 10 volts. 1 2. The method for operating a non-volatile memory cell array according to item 1 of the scope of the patent application, wherein the eighth voltage is 0 volts to 10 volts. 1 3. The method of operating a non-volatile memory cell array as described in item 1 of the scope of the patent application, wherein the ninth voltage is 0 volts to 5 volts. 1 4. The method of operating a non-volatile memory cell array as described in item 1 of the scope of the patent application, wherein the tenth voltage is from 0 volts to 5 volts. 1 5. A method of operating a non-volatile memory cell array, suitable for operating a NAND-type memory cell array, the memory cell array includes a plurality of memory cell arrays, and the memory cells in each of the memory cell arrays are connected in series to one Between a first selection transistor and a second selection transistor; each of the memory cells includes at least a substrate, a source region, an electrodeless region, a charge trapping layer, and a gate; the complex digital element lines are in line The gates are arranged in parallel and connected to the gates of the memory cells in the same row; a plurality of upper bit lines are respectively connected to the sources of the first selection transistors; a plurality of lower bit lines are respectively connected to the second selection transistors A drain; a first selection gate line connects the gates of the first selection transistors in the same row, and a second selection gate line connects the second selections of the same row 10631twfl.ptc Page 22 1220526 _Case No. 92106746_ YYYY__ VI. Patent application: Selecting the gate of a transistor, the method includes: applying a first to the character lines during the erasing operation. Voltage, a second voltage is applied to the substrate of the memory cells, and a voltage difference between the first voltage and the second voltage is sufficient to allow electrons to be injected into the charge trapping layers of the memory cells to perform the entire memory cell array Erasure. 16. The method for operating a non-volatile memory cell array as described in item 15 of the scope of patent application, further comprising: when performing a programmed operation, applying a character line on the character line to which the selected memory cell is coupled A third voltage, a fourth voltage is applied to the selected word lines to open the channels of the memory cells, a fifth voltage is applied to the selected upper bit lines, and the upper bit lines and the lower bits are not selected. A sixth voltage is applied to the element wire to program a source-side bit of one of the memory cells using a thermal hole injection effect. 1 7. The method for operating a non-volatile memory cell array as described in item 15 of the scope of patent application, further comprising: when performing a programmed operation, applying the word line on the character line to which the selected memory cell is coupled The third voltage, the fourth voltage is unselected on the word lines to open the channels of the memory cells, the fifth voltage is applied to the selected lower bit lines, and the lower bit lines and the upper bits are unselected. The element line applies the sixth voltage to program a non-polar side bit of one of the memory cells using a thermal hole injection effect. 1 8. The method of operating a non-volatile memory cell array as described in item 15 of the scope of the patent application, further including: when performing a read operation, the character coupled to the selected memory cell 10631twfl.ptc Page 23 1220526 _Case No. 92106746_ Year and Month Amendment_ 6. Apply a seventh voltage on the patent application line, and apply an eighth voltage on the unselected character lines to open the channels of the memory cells A ninth voltage is applied to the selected lower bit line, and a tenth voltage is applied to the unselected upper bit line and the lower bit line to read the source-side bit of the memory cell. 19. The method for operating a non-volatile memory cell array as described in item 15 of the scope of patent application, further comprising: applying a word operation on the character line to which the selected memory cell is coupled during a reading operation. Seventh voltage, the eighth voltage is applied to the selected word lines to open the channels of the memory cells, the ninth voltage is applied to the selected upper bit lines, and the lower bit lines and the upper bits are not selected The element line applies the tenth voltage to read the drain-side bit of the memory cell. 20. The method of operating a non-volatile memory cell array as described in item 15 of the scope of the patent application, wherein the voltage difference is from 0 volts to -40 volts. 2 1 · The method for operating a non-volatile memory cell array according to item 15 of the scope of the patent application, wherein the first voltage is 0 volts to 20 volts. 2 2 · The method for operating a non-volatile memory cell array as described in item 15 of the scope of patent application, wherein the second voltage is from 0 volts to -20 volts. 2 3 · The method for operating a non-volatile memory cell array as described in item 16 of the scope of patent application, wherein the third voltage is from 0 volts to -15 volts. 2 4. The method for operating a non-volatile memory cell array according to item 16 of the scope of the patent application, wherein the fourth voltage is from 0 volts to 10 volts. 25. The method for operating a non-volatile memory cell array according to item 16 of the scope of the patent application, wherein the fifth voltage is 0 volts to 10 volts. 2 6. The non-volatile memory cell array described in item 16 of the scope of patent application 10631twf1.ptc Page 24 1220526 _Case No. 92106746_ Year Month Amendment _ 6. The method of operation in the scope of patent application, where the sixth voltage is 0 volts to 10 volts. 2 7. The method for operating a non-volatile memory cell array according to item 18 of the scope of the patent application, wherein the seventh voltage is 0 volts to 10 volts. 2 8. The method for operating a non-volatile memory cell array according to item 18 of the scope of the patent application, wherein the eighth voltage is from 0 volts to 10 volts. 2 9. The method of operating a non-volatile memory cell array according to item 18 of the scope of the patent application, wherein the ninth voltage is from 0 volts to 5 volts. 30. The method for operating a non-volatile memory cell array according to item 18 of the scope of the patent application, wherein the tenth voltage is 0 volts to 5 volts. 31. —A method of operating a non-volatile memory cell array, the non-volatile memory cell array includes a plurality of memory cell arrays, and the memory cells in each of the memory cell arrays are connected in series to a first selection transistor and a A second selection transistor; each of the memory cells includes at least a substrate, a source region, an electrodeless region, a charge trapping layer, and a gate; the complex digital element lines are arranged in parallel in a row direction and connected to the same The gates of the memory cells; a plurality of upper bit lines are respectively connected to the sources of the first selection transistors; a plurality of lower bit lines are respectively connected to the drains of the second selection transistors; the method includes : During the erasing operation, the charge trapping layer is injected into the memory cells with electrons to erase the entire memory cell array; and when programming is performed, one side of the memory cell is programmed using the hole injection effect Bit. 10631twfl.ptc Page 25