TW200419577A - An operation method of nonvolatile memory array - Google Patents

Abstract

An operation method of nonvolatile memory array is suitable for a NAND memory cell array, wherein each memory cell comprises a charge trapping layer. Using F-N tunneling effect erases the whole nonvolatile memory array, and using hot-hole injection effect to program one bit of one memory cell. Using the F-N tunneling effect to perform the erasing operation, electron injection is more effective, the current flow to the memory cell is lower and the operating speed is thereby increase. The cell current is small during operations, and the power consumption of the whole chip can be significantly reduced.

Description

200419577 »« V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method of operating a non-volatile memory cell array (Non-Volatile Memory Array), and in particular, J relates to a single Operation method of an electrically erasable and programmable read only memory (EEPR0M) array stored in a memory cell two-bit (1 C e 1 1 2 B its). [Prior technology] The electrically erasable and programmable read-only memory in non-volatile memory can perform multiple operations of storing, reading, and erasing data, and the stored data can The advantage of not disappearing has become a memory element widely used in personal computers and electronic devices. A typical electrically erasable and programmable read-only memory system is made of doped polycrystalline silicon to make a floating gate (F 〇 a t i n g G a t e) and a control gate (C ο n t r ο 1 G a t e). When the memory is programmed (p r 0 g r a m), the injected floating gate $ electrons will be evenly distributed throughout the polycrystalline silicon floating gate layer. However, when there is a defect in the tunneling oxide layer under the polycrystalline stone floating gate layer, it is easy to cause the loss of electrons stored in the device and affect the reliability of the device. Therefore, in order to solve the problem of electrically erasable programmable read only memory device leakage current, a charge trapping layer is used instead of the polysilicon floating gate. The material of the charge trapping layer is, for example, silicon nitride. A silicon oxide layer is usually formed on each of the charge trapping layers to form a stacked gate structure including a silicon oxide / silicon nitride / silicon oxide (0N0) composite layer. t For this type of electrically erasable and programmable ROM, since silicon nitride has f

200419577 Qu 5. Description of the invention (2) The characteristics of capturing electrons and holes, and not conducting itself, is less sensitive to defects in the tunneling oxide layer, and the phenomenon of missing electrons and holes stored in the component is less likely to occur. In addition, when this type of electrically erasable and programmable read-only memory is programmed, the source / drain region on the first side of the stacked gate can have a higher voltage, The electrons are stored in the charge trapping layer of the source / dead region; and the source / drain region on the second side of the stacked gate can also have a higher voltage, while the source / drain region near the second side can be made higher. Electrons are trapped in the charge trapping layer. Therefore, by changing the voltage applied to the gate and the source / drain regions on either side, two groups of electrons, a single group of electrons, or no electrons can exist in a single charge trapping layer. Therefore, this electrically erasable and programmable read-only memory can write four states in a single memory cell, which is a non-volatile memory with a single memory cell of two bits (2 bits / ce 1 1). body. Generally speaking, this type of electrically erasable and programmable read-only memory system uses the Channel Hot-Electron (CHE) mode to trap electrons into the charge for programming. And after stylization, since the charge trapping layer on the non-electrode side (or source side) has a net negative charge, it will cause the starting voltage (VT) of the memory cell to rise. These electrons will stay in the charge trapping layer for a long time (for example, at 85 ° C for more than ten years) unless they are intentionally erased. When performing the erase operation, the band-to-band hot hole injection (B and-t 〇-B and Η 〇 t ο 1 e I njecti ο η) mode is used to make the hole injection sink into the layer near the drain side (or Source side) and the combination with the electrons stored on this side or the charge offset to achieve erasure

10631twf. Ptd Page 6 200419577 V. Description of the invention (3) " ------ ί Two in addition to ί In the original voltage (Vt) that originally existed on the non-polar side (or source side) Dropping it becomes the erase < H pin, so it will erase the memory cell, the first one is the above-mentioned electric erase and programmable read-only memory is programmed using channel hot electrons, so the efficiency of its electron injection is very low. Therefore, a higher voltage needs to be applied in the privatization of overpricing to provide a larger current, thereby increasing the programming rate. However, when the used voltage is increased, the reliability of the electronic components is reduced by 10% due to the high leakage lightning current and low programming efficiency caused by the punch-through effect. Especially when the size of the memory element is smaller, the situation of high leakage current and low programming efficiency caused by punch-through will become more serious, which will limit the shrinking of the element size [Inventive Content] & Therefore, one object of the present invention is to provide an operation method of a memory cell array, which can reduce the current of the memory cell, and the operation speed of the memory element. It is mentioned that another object of the present invention is to provide a Λ Jcb + Sector as a unit for programming. In order to achieve the above-mentioned object, the present invention provides a row of operating methods. The non-volatile memory cell array K memory cell array, the memory cells in each of the memory cells are connected in series to a memory cell. And the second selection transistor; each memory cell J ^ select transistor region, non-polar region, charge trapping layer and interrogator J = J, and the source-attracting Gemini 7G line is flat in the row direction

10631 twf. Ptd

Page 7 200419577 V. Description of the invention (4) Gates arranged in rows and connected to memory cells in the same row; the upper bit line is connected to the source of each first selection transistor; the lower bit line is connected to each of the two The first selection gate line is connected to the gate of the first selection transistor in the same row, and the second selection gate line is connected to the gate of the second selection transistor in the same row; this method is based on During the erasing operation, a first voltage is applied to the character line and a second voltage is applied to the substrate of the memory cell, where a voltage difference between the first voltage and the second voltage is sufficient to cause electrons to be injected into the charge trapping layer of the memory cell to Erase the entire memory cell array. When performing a stylized operation, a third voltage is applied to the character line to which the selected memory cell is coupled, a fourth voltage is applied to the non-selected character line to open the channel of the memory cell, and a fifth voltage is applied to the selected upper bit line. A sixth voltage is applied to the unselected upper bit line and the lower bit line to program the source-side bits of the memory cell using the thermal hole injection effect. When performing a read operation, a seventh voltage is applied to the character line coupled to the selected memory cell, and an eighth voltage is applied to the non-selected character line to open the channel of the memory cell, and a ninth voltage is applied to the selected bit line. The tenth voltage is applied to the unselected upper bit line and lower bit line to read the source-side bit of the memory cell. The operation method of the non-volatile memory further includes applying a third voltage to the character line to which the selected memory cell is coupled, and applying a fourth voltage to the non-selected character line to open the channel of the memory cell and lower the selected cell. A fifth voltage is applied to the element line, and a sixth voltage is applied to the unselected lower bit line and the upper bit line to program a drain-side bit of one of the memory cells by using a thermal hole injection effect. When performing a read operation, a seventh voltage is applied to the character line to which the selected memory cell is coupled, and an eighth voltage is applied to the unselected character line to open the memory cell.

10631twf. Ptd Page 8 200419577 V. Description of the invention (5) For the channel, a ninth voltage is applied to the selected upper bit line, and a tenth voltage is applied to the unselected lower bit line and upper bit line to read the drain of the memory cell. Side bit. The present invention also provides a method for operating a non-volatile memory cell array, which is suitable for operating a NAND-type memory cell array. The method is to apply a first voltage to a character line and apply a voltage to the substrate of the memory cell during an erase operation The second voltage, wherein a voltage difference between the first voltage and the second voltage is sufficient to cause the charge injected into the memory cell by the electrons to be trapped in the layer to erase the entire memory cell array. In the operation mode of the non-volatile memory cell array of the present invention, it uses the F-N penetrating effect (F-N Tu n n e 1 i n g) to erase the entire memory cells of the array. Then, the thermal hole injection effect is used to program in a single bit of a single memory cell without affecting the programming of other memory cells. Similarly, a single bit can be read from a single memory cell. Of course, the programming and reading operations of the non-volatile memory cell array of the present invention can also be controlled by each word line, select gate line, upper bit line, and lower bit line. Area, or block for programming and reading. In addition, in the operation of the non-volatile memory cell array, the present invention utilizes FN tunneling to perform the erase operation of the memory cell, and uses the thermal hole injection effect to perform the programmed operation of the memory cell. . Due to the F N -tunneling effect, its electron injection efficiency is high, so it can reduce the memory cell current during erasure, and at the same time, it can increase the operating speed. Therefore, the current consumption is small, which can effectively reduce the power loss of the entire chip.

10631 twf. Ptd Page 9 200419577 V. Description of the invention (6) and other objects, features, and advantages can be better embodiments, and in conjunction with the accompanying drawings, to make the above description of the present invention clearly understandable, the following A special description is as follows: [Embodiment] Doudou 1 is a schematic circuit diagram of a non-volatile memory cell array.

/ 、 中 ’This non-volatile memory cell array is a N A N D (Reverse Gate) type array. The operation method of the non-volatile memory cell array of the present invention is applicable to a N A N D (reverse gate) type array. In this embodiment, four rows of NAND memory cells are used as an example for description. Please refer to FIG. 1. The non-volatile memory cell array includes a plurality of selective electric solar cells STal ~ STdl and STa2 ~ STd2, a plurality of memory cells Qal ~ Qdn, a plurality of word lines WL1 ~ WLn, and a selection gate line SG1. With SG2. The upper bit lines BLU1 to BLU4 and the lower bit lines BLD1 to BLD4. The memory cells Q a 1 to Q a η form a memory cell array in the direction of the column and are connected in series between the selection transistor STal and the selection transistor STa2. The memory cells Qbl to Qb η form a memory cell array in the direction of the column, and are connected in series between the selection transistor STbl and the selection transistor STb2. The memory cells Qcl ~ Qcn form a memory cell array in the direction of the column, and are connected in series between the selection transistor STc 1 and the selection transistor S T c 2. The memory cells Q d 1 to Q d η form a memory cell array in the direction of the column and are connected in series between the selection transistor STd1 and the selection transistor STd2. The complex digital element lines are arranged in parallel in the row direction and connected to the gates of the memory cells in the same row. That is, the gates of the memory cells Q a 1 to Q d 1 in the first row are connected to the corresponding word line WL1. Gates of the second column of memory cells Qa2 ~ Qd2

10631twf. Ptd Page 10 200419577 V. Description of the invention (7) The car is connected to the corresponding character line WL2. The gates of the third column of memory cells Qa3 ~ Qd3 are coupled to the corresponding word line WL3. The gates of the fourth column of memory cells Qa4 to Qd4 are coupled to the corresponding word line WL4. By analogy, the gates of the memory cells Qan ~ Qdn in the nth column are coupled to the corresponding word line WLn °, and the gates of the selection transistors STal ~ STdl are coupled to the selection gate line SG1. The sources of the selection transistors STal ~ STdl are respectively coupled to the upper bit lines BLU1 ~ BLU4. The gates of the selection transistors STa2 to STd2 are connected to the selection gate line SG2. The drains of the selected transistors STa2 ~ STd2 are respectively connected to the bit lines BLD 1 ~ BLD4 ° Figures to the 3D sexual memory cell array to the 2D material reading instructions are based on the map and the 2D single non-volatile memory Cell array memory Cell array area or block according to Figure 2A and method. When registering, please refer to Table 1 and Figure 2A to Figure 2D, Figure 3A, Figure 4A to Figure 4D to clarify the operation mode of the non-volatile column of the present invention, which includes erasing (E (rase, Fig. 2a), programming (Program (Fig. 3A to 3Dgj)), and data (Read (Fig. 4A to 4D)). The memory cell Qb2 shown in Fig. 1 below is taken as an example for illustration, and the operation modes of the memory cells are shown in Figs. 3B and 3D, 4β and sexual memory cells. Mouth ~ 1 is not shown in Table 1. The description of the invention is as follows. Of course, according to the present invention, Γ can be divided into two types by the control of each character line, and the erasing method of section 2 B f 图 can be divided into two types. Please refer to the figure at the same time, which is used to illustrate the first erasing of the present invention. Division

10631twf. Ptd Page 11 200419577 V. Description of the invention (8) When the memory cell is erased, a bias voltage + Vge is applied to all the word lines WL1 to WLn (gate 1 08), which is, for example, 0 volts to 20 volts. Left and right, a bias voltage -Vb is applied to the substrate 100, which is, for example, 0 volts to -20 volts. A bias voltage + V st is applied to the selection gate line S G1, which is, for example, about 5 volts, and a bias voltage + Vdt is applied to the selection gate line SG2, which is, for example, about 5 volts. The upper bit line BLU2 (source 1 1 0) and the lower bit line B L D 2 (drain 1 1 2) are respectively biased by 0 volts. The voltage difference (0 to 40 volts) applied between the gate 108 and the substrate 100 is then sufficient to establish a large electric field between the gate 108 and the substrate 100 to utilize the FN The tunneling effect (FN Tunneling) causes electrons to be injected into the charge trapping layer 104 from the channel through the tunneling oxide layer 102, as shown in FIG. 2B. After erasing, there is a net negative charge on the charge trapping layer 104, which will cause the starting voltage (VT) of the memory cell to rise. Please refer to FIG. 2C and FIG. 2D at the same time, which are used to explain the second erasing method of the present invention. When erasing the entire memory cell, a bias voltage -Vge is applied to all of the word lines WL1 to WLn (gate 108), which is, for example, about 0 volts to -20 volts. A bias voltage + Vb is applied to the substrate 100, which is, for example, 0 volts to 20 volts. Select gate line S G 1, select gate line S G 2, upper bit line BLU2 (source 1 1 0) and lower bit line BLD2 (drain 1 1 2) are floating. The voltage difference (0 volts to -40 volts) applied between the gate 108 and the substrate 100 is sufficient to establish a large electric field between the gate 108 and the substrate 100, and the FN punch-through effect can be used ( FN Tunneling) causes electrons to be injected into the charge trapping layer 104 from the gate 108 through the dielectric layer 106, as shown in FIG. 2D. After erasing, there is a net negative charge on the charge trapping layer 104, which will cause the starting voltage (Vτ) of the memory cell to rise.

10631twf. Ptd Page 12 200419577 V. Description of the invention (9) Please refer to Figure 3 A and Figure 3 B at the same time. When the drain cell of the memory cell Q b 2 is programmed, select the character line. A bias voltage -Vgp is applied to WL 2 (gate 10 8), which is, for example, about 0 volts to about -15 volts. A bias voltage Vg is applied to the other unselected word lines WL1, WL3 to WLn, which is, for example, about 10 volts to open the channel region of the memory cell. A bias voltage + Vst is applied to the selection gate line SG1, which is, for example, about 5 volts to open the channels of the selection transistors STa and STdl, so that the upper bit lines BLU1 ~ BLU4 and the source electrodes of the memory cells Qal ~ Qdl are respectively Sexual connection. A bias voltage + Vdt is applied to the selection gate line SG2, which is, for example, about 5 volts to open the channels of the selection transistors STa2 to STd2, and the lower bit lines BLD1 to BLD4 are electrically connected to the drains of the memory cells Qan to Qdn connection. The bias voltage Vdp is applied to the selected lower bit line BLD2 (drain 1 12), which is, for example, about 5 volts, and the voltage of the unselected lower bit lines BLD1, BLD3, and BLD4 is 0 volt. The upper bit lines B L U 1 to B L U 4 (source 1 1 0) have a voltage of 0 volts. Under such a bias condition, the overlapping region of the gate 108 and the drain 1 12 creates a phenomenon of deep depletion, and is close to the non-polar side due to the south electric field perpendicular to the penetrating oxide layer. The hole can pass through the energy barrier of the tunneling oxide layer and enter the charge trapping layer 104 (Hot Hole Injection), as shown in FIG. 3B. After the stylization, the negative charge originally existing on the drain side trapped on the layer 104 is neutralized by the injected holes, so the starting voltage (VT) of the memory cell will decrease. When the drain side bit of memory cell Q b 2 is programmed, the drain side bits of memory cells Qa2, Qc2, and Qd2 that share the same word line WL2, because the lower bit lines BLD1, BLD3, and BLD4 are all It is 0 volts and therefore will not be stylized. Say

10631twf. Ptd Page 13 200419577 V. Description of invention (ίο) Similarly, please refer to Figure 3C and Figure 3D at the same time. When programming the source side bit of memory cell Qb2, the character line A bias voltage -V gp is applied to WL2 (gate 10 8), which is, for example, about 0 volts to about -15 volts. A bias voltage Vg is applied to the other unselected word lines WL1, WL3 to WLn, which is, for example, about 10 volts to open the channel region of the memory cells. A bias voltage + V st is applied to the selection gate line 3G 1, which is, for example, about 5 volts to open the channels of the selection transistors STa 1 to STd 1, so that the upper bit lines BLU 1 to BLU4 and the memory cells Qa and Qdl are respectively The source is electrically connected. A bias voltage + Vdt is applied to the selection gate line SG2, which is, for example, about 5 volts to open the channels of the selection transistors STa2 to STd2, so that the lower bit lines BLD1 to BLD4 and the memory cells Qan to Qdn are electrically non-polar. connection. A bias voltage Vdp 'is applied to the upper bit line BLU2 (source 丨 10), which is, for example, about 5 volts, and the voltage of the unselected upper bit lines BLU1, bLU3, and BLU4 is 0 volt. The lower bit lines BLD1 to BLD4 (drain 12) are electrically 0 volts. Under such a bias condition, a deep depletion phenomenon occurs in the heavy region between the gate 丨 〇8 and the source 丨 丨 〇, and due to the high electric field perpendicular to the tunneling oxide layer, it is close to the source The hole on the side can enter the charge trapping layer (Hot Hole Injection) through the energy barrier of the tunneling oxide layer, as shown in FIG. 3D. After stylization, the initial voltage of the memory cell will be lowered due to how the negative charge originally existing on the source side is trapped on the layer and injected into the hole. r When performing a stylized operation on the source-side bit of the Q2 memory cell, a total of == one word line WL2 memory cell "2, Qc2, source-side bit of Qd2, due to the upper το Lines BLU1, BLU3, and BLU4 are all 0 volts, so they will not be

200419577 V. Description of Invention (ll) Stylized. Moreover, in the above description, although the programming is performed by using a single bit of a single memory cell in the memory element array, the programming of the non-volatile memory cell array of the present invention can also be performed by each word line and a selection gate. The control of the epipolar line, the upper bit line, and the lower bit line is programmed in units of bytes, nodes, or blocks. Please refer to FIG. 4A and FIG. 4B at the same time. When reading the data of the source side bit of the memory cell Qb2, apply a bias voltage + Vs t to the selection gate line SG1, which is, for example, about 5 volts to turn on the selection circuit. The channels of the crystals STal ~ STdl, so that the upper bit lines BLU1 ~ BLU4 are electrically connected to the sources of the memory cells Qa and Qdl, respectively. A bias voltage + Vdt is applied to the selection gate line SG2, which is, for example, about 5 volts' to open the channels of the selection transistors STa2 to STd2, so that the lower bit lines β LD 1 to β l D 4 and the memory cell Q a η are respectively ~ Q d η is not electrically connected. A bias voltage Vdr of about 1.5 volts is applied to the lower bit line BLD2 (drain 112), and the voltage of the unselected lower bit lines BLD1, BLD3, and BLD4 is 0 volts. The word line WL2 (gate 108) is biased by about 3 volts Vcc, and other unselected word lines WL1, WL3 ~ WLn are biased by Vg, which is, for example, about 5 volts to open the channel region of the memory cell. A bias voltage of 0 volts is applied to the upper bit lines BLU1 to BLU4 (source 1 1 0). At this time, the channel of the memory cell with a negative total charge amount on the charge trapping layer 04 is closed and the current is small, and the channel of the memory cell with a slightly positive total charge amount on the charge trapping layer 104 is open and the current is large, so You can judge whether the digital information stored in this memory cell is "1" or "0" by the channel switch / channel current of the memory cell. Please refer to Figure 4C and Figure 4D at the same time. When reading the memory cell Qb2 drain

Page 15 l0631twf.ptd 200419577 V. Description of the invention (12) When the information of the side bit is applied, a bias voltage + Vst is applied to the selection gate line SG1, which is, for example, about 5 volts, to open the selection transistor STal ~ STdl And the upper bit lines BLU1 to BLU4 are electrically connected to the sources of the memory cells Qa and Qdl, respectively. A bias voltage + V dt is applied to the selection gate line SG 2, which is, for example, about 5 volts to open the channels of the selection transistors STa2 to STd2, and the lower bit lines BLD 1 to BLD 4 and the memory cells Q a η to The drain of Q d η is electrically connected. A bias voltage V s r of about 1.5 volts is applied to the upper bit line B L U 2 (source 1 110). The voltage of the unselected upper bit lines BLU1, BLU3, and BLU4 is 0 volts. The word line W L 2 (gate 10 8) applies a bias voltage V c c, which is, for example, about 3 volts. A bias voltage Vg is applied to the other unselected word lines WL1, WL3 ~ WLn, which is, for example, about 5 volts to open the channel region of the memory cell. A bias voltage of 0 volts is applied to the lower bit lines BLD1 to BLD4 (drain 1 110). At this time, the channels of the memory cells with a negative total charge ϊ on the charge trapping layer 104 are closed and the current is small, and the channels of the memory cells with a slightly positive total charge on the charge trapping layer 104 are open and the current is large, so You can judge whether the digital information stored in the memory cell is "1" or "0" by the channel switch / channel current of the memory cell. Moreover, in the above description, although the reading operation is performed by using a single bit of a single memory cell in the memory element array, the reading operation of the non-volatile memory cell array of the present invention can also be performed by each word line, Select the gate line, upper bit line and lower bit line control, and read the data in bytes, nodes, or blocks. In the operation mode of the non-volatile memory cell array of the present invention, it uses the F-N tunneling effect (F-N Tu n n e 1 i n g) to erase the entire memory cells of the array. Then, using the hot hole injection effect

10631twf. Ptd Page 16 200419577 V. Description of the Invention (13) The unit is programmed without affecting the programming of other memory cells. Similarly, a single bit can be read from a single memory cell. Of course, the programming and reading operations of the non-volatile memory cell array of the present invention can also be controlled by byte lines, node areas by controlling the word lines, selection gate lines, upper bit lines, and lower bit lines. , Or program and read in units of blocks. In addition, in the present invention, in the operation of the non-volatile memory cell array, the F-N tunneling effect (F-NT u η ne 1 ing) is used to perform the erasing operation of the memory cells, and the thermal hole injection effect is used to Program the memory cells. Due to the F N -tunneling effect, its electron injection efficiency is high, so it can reduce the memory cell current during erasure, and at the same time, it can increase the operating speed. Therefore, the current consumption is small, which can effectively reduce the power loss of the entire chip. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10631twf.ptd Page 17 200419577 Brief description of the table Table 1 is an applied voltage meter for the operation modes of erasing, programming and data reading of the non-volatile memory cell array of the present invention; FIG. 1 shows a non-volatile memory Simplified circuit diagram of a memory cell array; Figures 2A to 2D are schematic diagrams showing the erasing operation of the non-volatile memory cell array of the present invention; Figures 3A to 3D are the present invention. Figures 4A to 4D are schematic diagrams of the nonvolatile memory cell array stylized operation; and Figures 4A to 4D are schematic diagrams illustrating the read operation of the nonvolatile memory cell array of the present invention. Brief description of the drawing numbers: 100 substrate 102 tunneling oxide layer 104 charge trapping layer 106 dielectric layer 108 gate 110 source region 112 drain region BLD1 to BLD4: lower bit line BLU1 to BLU4: upper bit line Qa 1 to Qdn: Memory cells SGI, SG2: Select gate lines STal ~ STdl, STa2 ~ STd2: Select transistors WL1 ~ WLn: Word lines

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Claims (1)

200419577 VI. Application Patent Scope 1. A method for operating a non-volatile memory cell array, the non-volatile memory cell array includes a plurality of memory cell arrays, and the memory cells in each of the memory cell arrays are connected in series to a first selection Between the transistor and a second selection transistor; each of the memory cells includes at least a substrate, a source region, a drain region, a charge trapping layer, and a gate; the plurality of digital element lines are arranged in parallel in the row direction And connect the gates of the memory cells in the same row; the plural upper bit lines are respectively connected to the sources of the first selection transistors; the plural lower bit lines are respectively connected to the drains of the second selection transistors A first selection gate line connects the gates of the first selection transistors in the same row, and a second selection gate line connects the gates of the second selection transistors in the same row; the method includes: During the erasing operation, a first voltage is applied to the word lines, and a second voltage is applied to the substrate of the memory cells. The voltage difference between the first voltage and the second voltage is sufficient for electron injection. The charge trapping layers of the memory cells are used to erase the entire memory cell array. When performing a programming operation, a third voltage is applied to the word line to which the selected memory cell is coupled, and the words are not selected. A fourth voltage is applied to the element lines to open the channels of the memory cells, a fifth voltage is applied to the selected upper bit lines, and a sixth voltage is applied to the unselected upper bit lines and the lower bit lines to A source hole bit of the memory cell is programmed using a thermal hole injection effect; and a seventh voltage is applied to the word line to which the selected memory cell is coupled during a read operation, and the words are not selected An eighth voltage is applied to the element line to open the channels of the memory cells and select the lower bit. 10631twf. Ptd Page 19 200419577 6. Apply a ninth voltage to the patent application line, apply a tenth voltage to the unselected upper bit lines and the lower bit lines to read the source side of the memory cell yuan. 2. The method of operating non-volatile memory as described in item 1 of the scope of patent application, further comprising: applying the third voltage to the character line to which the selected memory cell is coupled, and unselecting the words The fourth voltage is applied to the element lines to open the channels of the memory cells, the fifth voltage is applied to the selected lower bit lines, and the sixth voltage is applied to the unselected lower bit lines and the upper bit lines to One of the drain side bits of the memory cell is programmed using the hot hole injection effect. 3. The method for operating a non-volatile memory as described in item 2 of the scope of patent application, further comprising: applying a seventh voltage to the character line to which the selected memory cell is coupled when performing a read operation , The eighth voltage is applied to the unselected word lines to open the channels of the memory cells, the ninth voltage is applied to the selected upper bit lines, and the unselected lower bit lines and the upper bit lines are applied The tenth voltage is used to read the drain-side bit of the memory cell. 4. The operation method of the non-volatile memory according to item 1 of the scope of the patent application, wherein the voltage difference is about 0 volts to about -40 volts. 5. The operation method of the non-volatile memory according to item 1 of the scope of patent application, wherein the first voltage is about 0 volts to about -20 volts. 6. The operation method of the non-volatile memory according to item 1 of the scope of patent application, wherein the second voltage is about 0 volts to about 20 volts. 7. Operation of non-volatile memory as described in item 1 of the scope of patent application 10631twf. Ptd Page 20 200419577 VI. Application for Patent Application Method, where the third voltage is about 0 volts to -15 volts. 8. The method for operating a non-volatile memory according to item 1 of the scope of the patent application, wherein the fourth voltage is about 0 volts to about 10 volts. 9. The method for operating a non-volatile memory according to item 1 of the scope of the patent application, wherein the fifth voltage is about 0 volts to about 10 volts. 10. The method for operating a non-volatile memory according to item 1 of the scope of patent application, wherein the sixth voltage is about 0 volts to 10 volts. 1 1. The method for operating a non-volatile memory according to item 1 of the scope of patent application, wherein the seventh voltage is about 0 volts to about 10 volts. 1 2. The method for operating a non-volatile memory according to item 1 of the scope of the patent application, wherein the eighth voltage is about 0 volts to about 10 volts. 1 3. The method for operating a non-volatile memory according to item 1 of the scope of patent application, wherein the ninth voltage is about 0 volts to 5 volts. 1 4. The method for operating a non-volatile memory according to item 1 of the scope of patent application, wherein the tenth voltage is about 0 volts to about 5 volts. 1 5. A method of operating a non-volatile memory cell array, suitable for operating a NAND-type memory cell array, the memory cell array includes a plurality of memory cell arrays, and the memory cells in each of the memory cell arrays are connected in series to one Between a first selection transistor and a second selection transistor; each of the memory cells includes at least a substrate, a source region, an electrodeless region, a charge trapping layer, and a gate; the complex digital element lines are in line The gates are arranged in parallel and connected to the gates of the memory cells in the same row; a plurality of upper bit lines are respectively connected to the sources of the first selection transistors; a plurality of lower bit lines are respectively connected to the second selection transistors Drain; a first select gate line connected to the same row 10631twf. Ptd Page 21 200419577 6. Scope of patent application The gates of the first selection transistors and a second selection gate line are connected to the gates of the second selection transistors in the same row. The method includes: During the erasing operation, a first voltage is applied to the word lines, and a second voltage is applied to the substrate of the memory cells. A voltage difference between the first voltage and the second voltage is sufficient for electron injection. The charge trapping layers of the memory cells are used to erase the entire memory cell array. 16. The method of operating non-volatile memory as described in item 15 of the scope of patent application, further comprising: when performing a programmatic operation, applying a first on the character line to which the selected memory cell is coupled Three voltages, a fourth voltage is applied to the selected word lines to open the channels of the memory cells, a fifth voltage is applied to the selected upper bit lines, and the upper bit lines and the lower bits are not selected Apply a voltage of one to six, to program a source-side bit of the memory cell using the hot hole injection effect. 1 7. The method for operating non-volatile memory as described in item 15 of the scope of patent application, further comprising: when performing a programmed operation, applying the first on the character line to which the selected memory cell is coupled Three voltages, the fourth voltage is unselected on the word lines to open the channels of the memory cells, the fifth voltage is applied to the selected lower bit lines, and the lower bit lines and the upper bits are not selected The sixth voltage is applied to the wire to program a drain-side bit of one of the memory cells using a hot hole injection effect. 1 8. The method of operating non-volatile memory as described in item 15 of the scope of patent application, which further includes: 10631twf. Ptd Page 22 200419577 VI. When reading the patent application range, a seventh voltage is applied to the character lines to which the selected memory cell is coupled, and an eighth voltage is applied to the unselected character lines. To open the channels of the memory cells, apply a ninth voltage to the selected lower bit lines, and apply a tenth voltage to the unselected upper bit lines and the lower bit lines to read the memory cells. Source side bit. 19. The method for operating a non-volatile memory as described in item 15 of the scope of patent application, further comprising: when performing a read operation, applying the first on the character line to which the selected memory cell is coupled Seven voltages, the eighth voltage is applied to the unselected word lines to open the channels of the memory cells, the ninth voltage is applied to the selected upper bit lines, and the lower bit lines and the upper bits are unselected The tenth voltage is applied to the line to read the drain-side bit of the memory cell. 20. The method for operating a non-volatile memory according to item 15 of the scope of patent application, wherein the voltage difference is about 0 volts to about _40 volts. 2 1. The method for operating a non-volatile memory according to item 15 of the scope of patent application, wherein the first voltage is about 0 volts to about 20 volts. 2 2. The method for operating a non-volatile memory according to item 15 of the scope of patent application, wherein the second voltage is about 0 volts to about -20 volts. 2 3. The method for operating a non-volatile memory as described in item 16 of the scope of patent application, wherein the third voltage is about 0 volts to about -15 volts. 2 4. The method for operating a non-volatile memory according to item 16 of the scope of patent application, wherein the fourth voltage is about 0 volts to about 10 volts. 25. The non-volatile memory as described in item 16 of the scope of patent application 10631 twf. Ptd page 23 200419577 6. Application scope of patent Operation method, wherein the fifth voltage is about 0 volts to about 10 volts. 26. The method for operating a non-volatile memory according to item 16 of the scope of patent application, wherein the sixth voltage is about 0 volts to about 10 volts. 2 7. The method for operating a non-volatile memory according to item 18 of the scope of patent application, wherein the seventh voltage is about 0 volts to about 10 volts. 2 8. The method for operating a non-volatile memory according to item 18 of the scope of patent application, wherein the eighth voltage is about 0 volts to 10 volts. 29. The method for operating a non-volatile memory as described in item 18 of the scope of patent application, wherein the ninth voltage is about 0 volts to 5 volts. 30. The method of operating a non-volatile memory as described in item 18 of the scope of patent application, wherein the tenth voltage is about 0 volts to 5 volts. 31. —A method of operating a non-volatile memory cell array, the non-volatile memory cell array includes a plurality of memory cell arrays, and the memory cells in each of the memory cell arrays are connected in series to a first selection transistor and a A second selection transistor; each of the memory cells includes at least a substrate, a source region, a drain region, a charge trapping layer, and a gate; the complex digital element lines are arranged in parallel in a row direction and connected to the same The gates of the memory cells; a plurality of upper bit lines are respectively connected to the sources of the first selection transistors; a plurality of lower bit lines are respectively connected to the drains of the second selection transistors; the method includes : During the erasing operation, the charge trapping layer is injected into the memory cells with electrons to erase the entire memory cell array; and when programming is performed, one side of the memory cell is programmed using the hole injection effect Bit. 10631twf.ptd Page 24 200419577 Table 1 Erase stylized read (1) (2) Drain-side bit Source-side bit Drain-side bit Source-side bit Select word line WL2 + Vge -Vge- Vgp -Vgp + Vcc + Vcc Unselected word line WL1, WL3, WL4 ... WLn + Vge -Vge + Vg + Vg + Vg + Vg Selected upper line BLU2 0 Floating 0 + Vsp + Vsr 0 Unselected upper bit line BLU1, BLU3, BLU4 0 floating 0 0 0 0 selected lower bit line BLD2 0 floating + Vdp 0 0 + Vdr unselected lower bit line BLD1, BLD3, BLD4 0 floating 0 0 0 0 select gate line SG1 Vst floating Set Vst Vst Vst Vst Select gate line SG2 Vdt Float Vdt Vdt Vdt Vdt Base-Vb + Vb 0 0 0 0