JP2010515199A - NAND flash memory cell array and method with adaptive memory state partition - Google Patents

Abstract

  The NAND flash memory is configured in the form of a NAND string, and each NAND string is a series of serial memory cells, and is connected to a bit line or a source line through selection transistors at both ends of the string. Memory cells near both ends of the NAND string are particularly susceptible to errors due to program disturb. In order to overcome the error, the memory cells except for the memory cells near both ends are divided so as to store a large number of bit data, and the memory cells near both ends store a relatively small number of bits. use. Thus, by storing relatively few bits in memory cells near both ends of the NAND string, a sufficient margin is provided to overcome the error. For example, a memory designed to store 2-bit data is configured to store 1 bit of 2-bit data in cells near both ends of the NAND string.

Description

  The present invention relates generally to flash EEPROM (electrically erasable and programmable read-only memory) type non-volatile semiconductor memory, and more specifically to operating a NAND type memory cell array and It relates to a structure and method for dealing with program disturb near the end.

  Currently, a number of commercially successful non-volatile memory products are in use, especially in the form of small form factor cards that use flash EEPROM cell arrays.

  In an example of a flash memory system using a NAND structure, a plurality of charge storage transistors functioning as memory cells are arranged in series with two selection gates interposed therebetween. The NAND array has several memory cells, for example, 8, 16, 32 memory cells connected as a series of memory cells (NAND strings) between a bit line and a reference potential through selection transistors at both ends. The word lines are connected to the control gates of cells in different series strings.

  To program a flash memory cell, a program voltage is applied to the control gate, and the bit line is grounded to raise the threshold voltage of the cell. Since the program voltage is applied to all cells connected to the word line, unselected cells on the word line (cells that should not be programmed) may be programmed unintentionally. The unintentional programming of a non-selected cell on a selected word line is referred to as “program disturb”.

  In order to accumulate more information efficiently and prevent program disturb, continuous efforts are being made to improve the programming technique of NAND memory cells.

  Therefore, there is a general demand for high performance and high capacity nonvolatile memory. In particular, there is a need for a compact non-volatile memory with improved read and programming performance, compact and efficient, but with an improved processor that can handle a wide range of data processing in read / write circuits.

US Pat. No. 5,570,315 US Pat. No. 5,774,397 US Pat. No. 6,046,935 US Pat. No. 6,456,528 US Pat. No. 6,522,580 US Published Patent Application No. 2006-0198195 US patent application Ser. No. 11 / 407,816 US Pat. No. 6,657,891

  The NAND flash memory is configured in the form of a NAND string, and each NAND string is a series of serial memory cells, and is connected to a bit line or a source line through selection transistors at both ends of the string. Memory cells near both ends of the NAND string are particularly susceptible to errors due to program disturb. In order to overcome the error, the memory cells except for the memory cells near both ends are partitioned to store a large number of bit data, and the memory cells near both ends use an adaptive memory state partitioning method that stores relatively few bits. To do. Thus, by storing relatively few bits in memory cells near both ends of the NAND string, a sufficient margin is provided to overcome the error.

  In one embodiment of designing a memory to store 2 bits per cell, one bit of such 2 bits per unit can be stored in a memory cell adjacent to one end of the NAND string and the other bit is It can be stored in another memory cell adjacent to the other end.

  In another embodiment in which the memory is designed to store 3 bits per cell, 2 bits of such 3 bits per unit can be stored in one memory cell and one bit is in the other memory cell. Can accumulate.

  The present invention has the advantage that existing memory systems can be easily modified to accommodate this adaptive scheme. To maintain the same memory capacity in the case of 2-bit or 3-bit memory systems, at most one additional memory cell may be added to the existing NAND chain.

  Further features and advantages of the present invention will be understood by interpreting the following description of preferred embodiments thereof in conjunction with the accompanying drawings.

It is a top view of a NAND string. FIG. 6 is an equivalent circuit diagram of a NAND string. 1B is a cross-sectional view of the NAND string of FIG. 1A. FIG. FIG. 6 is a circuit diagram depicting three NAND strings. 8 illustrates programming of an 8-cell NAND string. The effect of the self-boosting technique is demonstrated with an 8-cell NAND string. An 8-cell NAND string shows the GIDL effect. Fig. 5 illustrates application of an intermediate voltage when a memory cell is programmed. The GIDL effect when programming the word line WL0 is shown. 1 is a block diagram of one embodiment of a non-volatile memory system that implements various aspects of the invention. FIG. An example of a memory array organization is shown. The threshold voltage distribution in a four-state memory array when 2-bit data is stored in each memory cell using a conventional Gray code is shown. FIG. 6 illustrates lower page programming in an existing two-stroke programming scheme that uses Gray code. Fig. 5 illustrates upper page programming in an existing two-stroke programming scheme using Gray code. Fig. 4 shows a read operation for identifying the lower bits of a 4-state memory encoded with a Gray code. Fig. 4 illustrates a read operation for identifying the upper bits of a 4-state memory encoded with a Gray code. The threshold voltage distribution of a four-state memory array when 2 bits of data are stored in each memory cell using the LM code is shown. FIG. 6 illustrates lower page programming in an existing two-round programming scheme using LM codes. FIG. 6 shows upper page programming in an existing two-round programming scheme using LM codes. Fig. 4 shows a read operation for identifying the lower bits of a 4-state memory encoded with an LM code. Fig. 4 shows a read operation for identifying the upper bits of a 4-state memory encoded with an LM code. The effect of GIDL induced errors is shown in various memory cells of a conventional NAND string. FIG. 6B illustrates a memory state partition of memory cells in an exemplary NAND string corresponding to FIG. 6A. A prior solution is shown for introducing additional dummy memory cells at the end of the memory cell chain in a NAND string. FIG. 7B illustrates memory state partitioning of memory cells in a typical NAND string with dummy cells similar to FIG. 7A. FIG. 7B shows the memory state partition of a memory cell in a typical NAND string with two dummy cells similar to FIG. 7A. FIG. 5 illustrates a scheme for overcoming GIDL errors in a NAND string end memory cell in accordance with a general embodiment of the present invention. FIG. 8B illustrates memory state partitioning of memory cells in an exemplary NAND string according to the adaptive memory state partitioning scheme of FIG. 8A. 6 illustrates a preferred alternative scheme using the 2-bit LM encoding described in FIGS. 5A-5E. It is a flowchart which shows an adaptive memory division system.

  To facilitate an understanding of the preferred embodiment, the general configuration and operation of a NAND string will be described. Thereafter, the specific configuration and operation of the preferred embodiment will be described with reference to the general configuration.

Overview of NAND Structure FIG. 1A shows a top view of a NAND structure with a number of series transistors sandwiched between two select gates. The transistor in series and the select gate are called a NAND string. (Transistors and gates are sometimes referred to as non-volatile storage elements.) FIG. 1A shows a four memory cell NAND string. FIG. 1B shows a circuit equivalent to FIG. 1A.

  The NAND string depicted in FIGS. 1A and 1B includes four series transistors 100, 102, 104, and 106 sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG of the selection gate 120. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG of the selection gate 122. Transistors 100, 102, 104, and 106 each have a control gate and a floating gate. For example, transistor 100 includes a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. Transistor 104 includes a control gate 104CG and a floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.

  FIG. 1C is a cross-sectional view of the NAND string 142 described above. As depicted in FIG. 1C, a NAND string transistor (also referred to as a cell or memory cell) is formed in the p-well region 140. Each transistor includes a stacked gate structure including a control gate (100CG, 102CG, 104CG, and 106CG) and a floating gate (100FG, 102FG, 104FG, and 106FG). The floating gate is formed on the oxide film on the surface of p well region 140. The control gate is above the floating gate, and the control gate and the floating gate are separated by an oxide film.

  FIG. 1C appears to depict the control gate and floating gate of select transistors 120 and 122. However, in the case of the transistors 120 and 122, both the control gate and the floating gate are connected. The control gates of the memory cells (100, 102, 104, and 106) form a word line. By sharing N + diffusion layers 130, 132, 134, 136, and 138 between adjacent cells, the cells are connected in series with each other to form a NAND string. These N + diffusion layers form the source and drain of each cell. For example, N + diffusion layer 130 functions as a drain for transistor 122 and functions as a source for transistor 106, N + diffusion layer 132 functions as a drain for transistor 106 and functions as a source for transistor 104, and N + diffusion Layer 134 functions as a drain for transistor 104 and as a source for transistor 102, N + diffusion layer 136 functions as a drain for transistor 102 and as a source for transistor 100, and N + diffusion layer 138 is a transistor. It functions as a drain for 100 and as a source for transistor 120. The N + diffusion layer 126 is connected to the bit line of the NAND string, and the N + diffusion layer 128 is connected to a common source line of a number of NAND strings.

  Although FIGS. 1A-1C show four memory cells in a NAND string, the use of four transistors is only an example. A NAND string may have no more than 3 memory cells and may have no less than 5 memory cells. For example, some NAND strings may include 8 memory cells (shown and described later in relation to FIGS. 2B-2F), 16 memory cells, and 32 memory cells. The discussion here is not limited to a specific number of memory cells in a NAND string.

  FIG. 2A shows a memory array of three NAND strings 202, 204, and 206, with more NAND strings. Each of the NAND strings of FIG. 2A includes two select transistors and four memory cells. For example, NAND string 202 includes select transistors 220 and 230 and memory cells 222, 224, 226, and 228. NAND string 204 includes select transistors 240 and 250 and memory cells 242, 244, 246, and 248. Each string is connected to the source line by a respective select transistor (eg, select transistor 230 and select transistor 250). The selection line SGS is used to control the source side selection gate. The various NAND strings are connected to their respective bit lines by select transistors 220, 240, etc. controlled by select line SGD.

  The selection lines need not be common in other embodiments. Word line WL 3 is connected to the control gates of memory cell 222 and memory cell 242. Word line WL 2 is connected to the control gates of memory cell 224 and memory cell 244. Word line WL 1 is connected to the control gates of memory cell 226, memory cell 246, and memory cell 250. Word line WL 0 is connected to the control gates of memory cell 228 and memory cell 248. As can be seen, each bit line and NAND string constitute a column of the memory cell array. The word lines (WL3, WL2, WL1, and WL0) constitute a row of the array, and as described above, the word line connects the control gates of the memory cells in the row.

  FIG. 2B shows an example of an 8-memory cell NAND string. Additional word lines are seen as WL4 to WL7 (for memory cells 222A to 228A), which function similarly to word lines WL0 to WL3.

  Each memory cell can store data (analog or digital). When 1-bit digital data is stored, the threshold voltage range of the memory cell is divided into two ranges, and logical data “1” and “0” are assigned. In an example of the NAND flash memory, the threshold voltage after the memory cell is erased is negative and is defined as logic “1”. The threshold voltage after the program operation is positive and is defined as logic “0”. If a read is attempted when the threshold voltage is negative, the memory cell is turned on to instruct the accumulation of logic one. If a read operation is attempted when the threshold voltage is positive, the memory cell is not turned on, and an instruction to store logic 0 is given.

  A memory cell may store multiple levels of information (or “data”), eg, multiple bits of digital data. When storing data of a plurality of levels, the threshold voltage range is divided into the number of data levels. For example, if four levels of information are stored, four threshold voltage ranges are assigned to data values “11”, “10”, “01”, and “00”. In an example of the NAND type memory, the threshold voltage after the erase operation is negative and is defined as “11”. Positive threshold voltages are used for states “10”, “01”, and “00”.

  U.S. Pat. Nos. 5,570,315 (Patent Document 1), 5,774,397 (Patent Document 2), 6,046,935 (Patent Document 3), which are incorporated herein by reference. ), No. 6,456,528 (Patent Document 4) and No. 6,522,580 (Patent Document 5) present an example of a NAND flash memory and its operation.

When programming the program disturb flash memory cell, a program voltage is applied to the control gate and the bit line is grounded. Electrons are injected from the p-well into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the cell threshold voltage increases. In order to apply a program voltage to the control gate of a cell to be programmed, the program voltage is applied along the corresponding word line. As described above, the word line is also connected to one cell of another NAND string that uses the same word line. For example, when the cell 224 of FIG. 2A is programmed, the program voltage is also applied to the control gate of the cell 244 sharing the same word line.

  Problems arise when one cell on a word line is programmed and another cell connected to the same word line is not programmed, for example, when cell 224 is programmed and cell 244 is not programmed. Since the program voltage is applied to all cells connected to the word line, unselected cells on the word line (cells that should not be programmed) may be programmed unintentionally. For example, when programming cell 224, there is a concern that cell 244 may be programmed unintentionally. The unintentional programming of a non-selected cell on a selected word line is referred to as “program disturb”.

  There are several ways to prevent program disturb. One method known as “self-boosting” electrically isolates unselected bit lines and applies a pass voltage (eg, 10 volts) to unselected word lines during programming. An unselected word line is coupled to an unselected bit line, and a voltage (for example, 8 volts) is generated in the channel of the unselected bit line, thereby suppressing program disturb. The voltage boost that occurs in the channel due to self-boosting tends to lower the tunnel oxide voltage and suppresses program disturb. FIG. 2C shows an example of a self-boosting technique that includes a boosted channel 252.

  The NAND string is usually programmed from the source side to the drain side, for example, from memory cell 228 to memory cell 228A (but not necessarily). If all or most of the programmed cells on the forbidden string (eg string 204) were programmed when attempting to program the last (or near the end) memory cell of the NAND string, the programmed cell's There is a negative charge in the floating gate. The boost potential due to the negative charge on the floating gate is not sufficiently high, and program disturb may occur in the last few word lines. For example, if cells 248, 246, and 244 were programmed when programming cell 222, the floating gates of those transistors (244, 246, and 248) have a negative charge, which boosts the self-boosting process. Limiting levels may cause program disturb in cell 242.

Local self-boosting (“LSB”) and erased area self-boosting (“EASB”)
The self-boosting problem described above has been addressed in two ways: local self-boosting (“LSB”) and erased area self-boosting (“EASB”). Both LSB and EASB attempt to isolate the programmed cell channel from the prohibited cell channel. For example, when programming cell 224 of FIG. 2A (or FIG. 2B) with LSB and EASB, an attempt is made to inhibit programming in cell 244 by isolating the channel of cell 244 from the programmed cells (246 and 248).

  In the case of the LSB method, the bit line of the cell to be programmed is grounded, and the bit line of the string including the prohibited cell is Vdd. A program voltage Vpgm (for example, 20 volts) is applied to the selected word line. The word line adjacent to the selected word line is 0 volts, and the remaining unselected word lines are Vpass. For example, in FIG. 2A, bit line 202 is 0 volts and bit line 204 is Vdd. The drain selection SGD is Vdd and the source selection SGS is 0 volts. The selected word line WL2 (to program cell 224) is Vpgm. Adjacent word lines WL1 and WL3 are at 0 volts, and the other word lines (eg WL0) are at Vpass. The same can be seen for the 8-memory cell NAND string of FIG. 2B.

  EASB is similar to LSB except that only the adjacent word line on the source side is at 0 volts. FIG. 2D shows an example of EASB. When programming WL5, WL4 is set to 0 volts to isolate the channel and WL3 is set to Vpass. Vpass is 7 to 10 volts in one embodiment. If Vpass is too low, channel boost will be insufficient to prevent program disturb. If Vpass is too high, unselected word lines are programmed.

Gate induced drain leakage (GIDL)
Although LSB and EASB improve self-boosting, problems may arise depending on whether programming or erasing is performed on adjacent cells on the source side (cell 246 is an adjacent cell on the source side of cell 244). If an adjacent cell on the source side is programmed, the floating gate of the adjacent cell on the source side has a negative charge. 0 volts is applied to the control gate. An extreme reverse bias junction occurs under the negatively charged gate and gate induced drain leakage (GIDL) occurs. With GIDL, electrons leak into the boost channel between bands (BB tunneling). Whenever adjacent source-side cells are programmed to boost the drain junction, a large bias and a low or negative gate voltage are generated at the junction along with GIDL. With GIDL, the boost voltage leaks prematurely, leading to programming errors. GIDL becomes even more severe with extreme doped junctions required to scale cell dimensions. If the leakage current is sufficiently high, the boost potential in the channel region is lowered and program disturb occurs. The closer the word line to be programmed is to the drain, the less charge on the boosted junction. As a result, the boosted junction voltage rapidly drops and program disturb occurs. Even if the leakage current is not high enough, the electrons induced by GIDL are easily injected into the floating gate with a high electric field between the gate and the channel. This also causes program disturb.

  FIG. 2D shows an example of GIDL when Vpgm is applied to WL5, WL4 is set to 0 volts, and Vpass is applied to other word lines. It can be seen that positive charges leak into the p-well and the remaining electrons are injected into the floating gate.

  When the interval between word lines is reduced in order to reduce the die size, further problems appear at certain stages of lithography such as noise due to WL-SG (coupling between word lines and selection gates) and program disturb due to GIDL. For example, the WL-SG coupling capacitance increases as the word line is reduced. As a result, the waiting time until the combined noise is reduced is increased.

  Since the electric field density increases as the word line shrinks, the GIDL error becomes more prominent when programming the memory cells located at both ends of the NAND string.

  In the previous approaches, in order to reduce the electric field density and reduce the WL-SG coupling noise, the gap between the select gate transistor (eg, select transistor 230 in FIG. 2A) and the adjacent memory transistor (eg, memory cell 228) is widened. To do. However, doing so makes the NAND string longer and not suitable for die size reduction. Also, a more serious lithography problem arises due to the abrupt line / space change of SG-WL relative to WL-WL. US Published Patent Application No. 2006-0198195 discloses an improved self-boosting method that reduces GIDL. In that technique, another voltage VGP is applied to the memory cell next to the cell to be programmed. In FIG. 2E, which illustrates this, WL5 is programmed, VGP is applied to WL4, and 0 volts is applied to WL3. Thus, the WL voltage gradually decreases around the selected WL (VPGM). For example, VPGM (24 V) -VPASS (10 V) -VGP (4 V) -VISO (0 V). Thereby, GIDL decreases by programming from WL1 to WLN where N is the last word line. However, when WL0 is programmed, this technique fails because there is no adjacent word line on the select transistor side. FIG. 2F shows that the GIDL problem still occurs at the end of the string. For example, when Vpgm is applied to WL0, GIDL occurs due to band-to-band (BB) tunneling.

  US Patent Application No. 11 / 407,816 entitled “Method and System for Flash Memory Devices”, filed on April 20, 2006, includes a memory cell located at the end of a string and a select gate. The GIDL problem at the end of the string is addressed by inserting a dummy memory cell in between. The control gate of this dummy memory cell is coupled to a dummy word line (WL). By controlling the bias of the dummy WL, GIDL can be suppressed as in US Patent Application Publication No. 2006-0198195 (Patent Document 6). The dummy WL also prevents noise between SG and WL. In order to suppress the source side GIDL in addition to the drain side GIDL, it is necessary to add two dummy memory cells and two WLs at each end of the NAND string. Dummy memory cells do not store data and have the disadvantage of further increasing the size of the NAND string.

Adaptive memory state partitioning in NAND strings NAND flash memory is configured in the form of NAND strings, each NAND string being a series of serial memory cells, connected to a bit line or source line through select transistors at both ends of the string . Memory cells near both ends of the NAND string are particularly susceptible to errors due to program disturb.

  According to a general aspect of the invention, an adaptive memory state partitioning scheme is used to overcome errors at both ends of the NAND string. In the NAND string, the memory cells excluding the memory cells near both ends are divided so as to store data of 2 bits or more, and the memory cells near both ends store fewer bits than other cells. Thus, by storing relatively few bits in memory cells near both ends of the NAND string, a sufficient margin is provided to overcome the error. For example, in a memory designed to store 2 bits per cell, two bits are stored in two memory cells near both ends as individual bits.

Flash Memory System FIG. 3A is a block diagram of one embodiment of a flash memory system used to implement the present invention. The memory cell array 302 is controlled by a column control circuit 304, a row control circuit 306, a c source control circuit 310, and a p well control circuit 308. In order to read data stored in the memory cell, to determine the state of the memory cell during a program operation, and to control the potential level of the bit line to promote or inhibit programming, the column control circuit 304 Is connected to the bit line of the memory cell array 302. To select any one of the word lines, to apply a read voltage, to apply a program voltage combined with a bit line potential level controlled by the column control circuit 304, and to apply an erase voltage, a row The control circuit 306 is connected to the word line. The c source control circuit 310 controls the common source line (labeled “C source” in FIG. 3B) connected to the memory cell. The p well control circuit 308 controls the p well voltage.

  Data stored in the memory cell is read by the column control circuit 304 and output to the external I / O line through the data input / output buffer 312. Program data stored in the memory cell is input to the data input / output buffer 312 through the external I / O line and transferred to the column control circuit 304. The external I / O line is connected to the controller 318.

  Command data for controlling the flash memory device is input to the controller 318. The command data informs the flash memory of the requested operation. Input commands are forwarded to state machine 316, which controls column control circuit 304, row control circuit 306, c source control 310, p well control circuit 308, and data input / output buffer 312. The state machine 316 can also output status data of the flash memory such as READY / BUSY, PASS / FAIL, and the like.

  The controller 318 is connected to or connectable to a host system such as a personal computer, a digital camera, or a personal digital assistant (PDA). The controller communicates with the host, which in turn initiates commands to store and read data in the memory array 302 and provides or receives such data. The controller 318 converts the command into a command signal that can be interpreted and executed by a command circuit 314 that communicates with the state machine 316. The controller 318 normally includes a buffer memory for user data that is read and written by the memory array. A typical memory system includes an integrated circuit including a controller 318 and one or more integrated circuit chips, each integrated with a memory array and associated control, input / output, and state machine circuits. . Both memory arrays and system controller circuits tend to be integrated into one or more integrated circuit chips. The memory system may be embedded as part of the host system or may be included in a memory card (or other package) that is removably inserted into the host system. Such cards may include the entire memory system (eg, including a controller) or only peripheral circuitry associated with the memory array (the controller is embedded in the host). Thus, the controller is embedded in the host or included in the removable memory system.

  A structural example of the memory cell array 302 will be described with reference to FIG. 3B. As an example, a NAND flash EEPROM divided into 1,024 blocks will be described. Data stored in each block is erased simultaneously. In one embodiment, a block is the smallest unit of cells that are simultaneously erased. Each block in this example has 8,512 columns divided into even columns and odd columns. The bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo). FIG. 3B shows by way of example four memory cells connected in series to form a NAND string. Each NAND string has four cells, but may use fewer than four cells or more than four. For example, one NAND string may accommodate 32 or more memory cells. One end of the NAND string is connected to the corresponding bit line through the first selection transistor SGD, and the other end is connected to the c source through the second selection transistor SGS.

  In a read operation and a programming operation, one page (for example, 4,256) memory cells are simultaneously selected. The selected memory cell has the same word line (for example, WL2-i) and the same kind of bit line (for example, even bit line). Accordingly, reading or programming of 532 bytes of data can be performed simultaneously. A logical page is formed by 532 bytes of data that are read and programmed simultaneously. Therefore, at least eight pages can be stored in one block. If 2-bit data is stored in each memory cell (for example, multi-level cell), 16 pages are stored in one block.

  To erase the memory cell, the p-well is raised to an erase voltage (for example, 20 volts), and the word line of the selected block is grounded. The source line and bit line are floating. Erasing is performed for the entire memory array, for each block, or for each other cell unit. Electrons are transferred from the floating gate to the p-well region, and the threshold voltage becomes negative.

  In read and verify operations, the select gates (SGD and SGS) and unselected word lines (eg, WL0, WL1, and WL3) are applied to the read pass voltage (eg, 4.5 volts) to operate the transistors as pass gates. ) The level of the voltage connected to the word line (for example, WL2) selected by the read operation and the verify operation is determined, and it is determined whether or not the threshold voltage of the corresponding memory cell has reached that level. For example, in the read operation, the selected word line WL2 is grounded, and it is detected whether or not the threshold voltage is higher than 0V. In the verify operation, the selected word line WL2 is connected to 2.4V, for example, and it is verified whether the threshold voltage has reached 2.4V or another threshold level. The source and p-well are 0 volts. The selected even bit line (BLe) is precharged to a level of 0.7V, for example. If the threshold voltage is higher than the read level or the verify level, the potential level of the corresponding even bit line (BLe) for the non-conductive memory cell remains high. On the other hand, if the threshold voltage is lower than the read level or the verify level, the potential level of the corresponding even bit line (BLe) for the conductive memory cell is lowered to a low level, for example, less than 0.5V. The state of the memory cell is detected by a sense amplifier connected to the bit line. The difference between whether the memory cell is erased or programmed depends on whether negative charge is stored in the floating gate. For example, if negative charges are accumulated in the floating gate, the threshold voltage becomes high and the transistor can enter the enhancement mode.

  The erase, read and verify operations described above are performed according to techniques known in the art. Accordingly, many of the details described may vary from one person skilled in the art.

Examples of Multi-State Memory Reading and Programming FIGS. 4A-4E and 5A-5E show two multi-bit encoding examples in a 4-state memory, respectively. In a four-state memory cell, four states can be expressed by two bits. One existing technique programs such memory using two-stroke programming. The first bit (lower page bit) is programmed in the first pass. After that, the desired second bit (upper page bit) is expressed by programming the same cell in the second step. In order not to change the value of the first bit in the second step, the memory state representation of the second bit depends on the value of the first bit.

4A-4E illustrate programming and glueing of a four-state memory encoded with a conventional 2-bit Gray code. The programmable threshold voltage range (threshold window) of the memory cell is four, corresponding to the unprogrammed state “U” and the three programmed states “A”, “B”, and “C”. Divide into areas. The four regions are delimited by boundary threshold voltages D _A , D _B and D _C.

  FIG. 4A shows the threshold voltage distribution in a four-state memory array when conventional bits are used to store 2-bit data in each memory cell. The four distributions correspond to four memory state groups “U”, “A”, “B”, and “C”. Before a memory cell is programmed, it is erased to a “U” or “unprogrammed” state. As memory cells are progressively programmed, memory states “A”, “B”, and “C” are gradually reached. Gray code uses (upper bit, lower bit) and sets “U” to (1,1), “A” to (1,0), “B” to (0,0), “C” Specify (0, 1).

  FIG. 4B illustrates lower page programming in an existing two-stroke programming scheme that uses Gray code. When programming one page of cells in parallel, two logical pages are formed by the upper bits and the lower bits, the logical lower page consists of lower bits, and the logical upper page consists of upper bits. In the first programming step, only the logical lower page bits are programmed. With proper encoding, the logical upper page bits are programmed in a subsequent second programming step for the same page of cells and the logical lower page bits are not reset. Gray code is a commonly used code, and only one bit changes when transitioning to a nearby state. This code has the advantage of lightening the burden of error correction involving only one bit.

  In a general method using the gray code, “1” represents a “non-programmed” state. Therefore, the erased memory state “U” is expressed by (upper page bit, lower page bit) = (1, 1). To program the logic lower page in the first pass, the logic state of the cell storing bit “0” transitions from (x, 1) to (x, 0), where “x” is the upper bit ignored. (Don't care) value. However, since the upper bits are not yet programmed, “x” can be labeled with “1” for consistency. The logic state (1, 0) is represented by programming the cell to memory state “A”. That is, the lower bit value of “0” is represented by the memory state “A” prior to the second programming step.

  FIG. 4C illustrates upper page programming in an existing two-stroke programming scheme that uses Gray code. The second stage programming is performed to store the bits of the logical upper page. Only those cells that require an upper page bit value of “0” are programmed. Cells in the page are in the logic state (1, 1) or logic state (1, 0) after the first pass. In order to maintain the value of the lower page in the second stroke, it is necessary to distinguish the lower bit value of “0” or “1”. In the transition from (1, 0) to (0, 0), the memory cell is programmed to the memory state “B”. In the transition from (1, 1) to (0, 1), the memory cell is programmed to the memory state “C”. Thus, by determining the memory state programmed into the cell during reading, both the lower page bits and the upper page bits can be decoded.

To achieve programming, programming pulses are alternately applied in parallel to a page of memory cells, and then each cell is sensed or program verified to determine whether the cell has been programmed to a target state. To do. A program-verified cell is locked out of further programming, i.e., in a program inhibit state, even if a programming pulse is subsequently applied to complete programming of other cells in the group. In FIG. 4B and FIG. 4C, it can be seen that it is necessary to execute the program verify (“verifyA”) of the state “A” with the boundary threshold voltage D _A during the lower page programming. However, in the case of upper page programming, it is necessary to execute program verify for the states “B” and “C”. Therefore, it is necessary to "verifyC" 2-stroke verify "verifyB" and relative to the demarcation threshold voltages D _B and D _C is when verifying the upper page.

FIG. 4D shows a read operation to identify the lower bits of the 4-state memory that are encoded with the Gray code. Since the low-order bits of the memory state “A” encoded with (1, 0) and “B” encoded with (0, 0) are both “0”, the state up to the state “A” or “B” When the memory cell is programmed, the lower bit “0” is detected. Conversely, when the memory cell is unprogrammed in state “U” or programmed to state “C”, the lower bit “1” is detected. Therefore, when reading the lower page, read-out readA and readC in two steps with reference to the boundary threshold voltages D _A and D _C are required.

FIG. 4E shows a read operation to identify the upper bits of a 4-state memory encoded with a Gray code. It is required once read stroke readB for the demarcation threshold voltage D _B. The cells programmed threshold voltage is less than D _B will be detected as a memory state "1", and vice versa.

  The Gray code two-stroke programming scheme is problematic when there is an error in the second stroke programming. For example, if the upper page bit is programmed to “0” when the lower bit is “1”, a transition from (1, 1) to (0, 1) occurs. This requires progressive programming of memory cells from “U” through “A” and “B” to “C”. If there is a power failure before this programming is complete, the memory cell ends in one of the transient memory states, eg, “A”. When the memory cell is read, “A” is decoded to the logic state (1, 0). Since this is supposed to be (0, 1), both the upper and lower bits are wrong. Similarly, if programming is interrupted when it reaches “B”, it becomes (0, 0). The upper bits in this case are correct, but the lower bits are still incorrect. In addition, since there is a transition from the unprogrammed state “U” to the most programmed state “C”, this code system increases the difference in charge level between adjacent cells programmed at different times. The field effect coupling (“Yupin effect”) between adjacent floating gates also becomes serious.

  FIGS. 5A-5E illustrate programming and reading of a four-state memory that is encoded with another logical code (“LM code”). This code has excellent fault tolerance and relaxes adjacent cell coupling due to the Yupin effect.

  FIG. 5A shows the threshold voltage distribution of a 4-state memory array when 2 bits of data are stored in each memory cell using the LM code. LM encoding differs from the conventional Gray code seen in FIG. 7A in that the upper and lower bits are reversed in states “A” and “C”. The “LM” code disclosed in US Pat. No. 6,657,891 suppresses field effect coupling between adjacent floating gates by avoiding program operations that require significant charge changes. There is an advantage. As seen in FIGS. 5B and 5C, the programming operation changes the charge of the charge storage unit gently, which is evident from the gentle change in the threshold voltage VT.

  In that encoding, the lower and upper 2 bits are programmed and read separately. The threshold level of the cell when programming the lower bits stays in the unprogrammed area or proceeds to the “lower middle” area of the threshold window. When programming the upper bits, the threshold level in either of the two regions is further advanced to a slightly higher level that is less than a quarter of the threshold window.

FIG. 5B shows lower page programming in an existing two round programming scheme using LM codes. The fault tolerant LM code basically avoids the passage of intermediate states in upper page programming. The lower page programming of the first round is represented by the "unprogrammed" memory state "U" by the program threshold voltages below D _C greater than D _A in the wide distribution (x, 0) "intermediate" By programming to the state, the logic state (1, 1) transitions to the intermediate state (x, 0). During programming, the intermediate state is verified with reference to the boundary DV _A.

  FIG. 5C shows upper page programming in an existing two round programming scheme using LM codes. If the lower page bit is "1" in the second round of programming the upper page bit to "0", the logic state (1, 1) is (1) by programming the "unprogrammed" memory state "U" to "A" ( Transition to 0,1). If the lower page bit is “0”, the logic state (0, 0) is obtained by programming from the “intermediate” state to “B”. Similarly, if the upper page is kept at "1" when the lower page is programmed to "0", the "intermediate" state transitions to (1, 0) by programming the "middle" state to "C" There is a need to. In the programming of the upper page, only the next memory state is programmed, so that a large amount of charge does not change from round to round. Lower page programming from “U” to the approximate “intermediate” state saves time.

FIG. 5D shows a read operation to identify the lower bits of the 4-state memory encoded with the LM code. Decoding depends on whether the upper page has been programmed. If the upper page programmed, it will require one read step readB relative to the demarcation threshold voltage D _B when reading the lower page. On the other hand, if the upper page has not yet been programmed, the lower page is programmed to the “intermediate” state (FIG. 5B) and an error occurs in readB. To read the lower page will require one read step readA relative to the demarcation threshold voltage D _A. In order to distinguish between the two cases, a flag (“LM” flag) is written in the upper page when the upper page is programmed. At the time of reading, first, it is assumed that the upper page has been programmed and the readB operation is executed. If the LM flag is read, this assumption is correct and the read operation is complete. On the other hand, if the flag is not obtained by the first reading, it means that the upper page is not programmed, and the lower page must be read by the readA operation.

FIG. 5E shows a read operation to identify the upper bits of the 4-state memory encoded with the LM code. As is apparent from this figure, when reading the upper page, read-out readA and readC in two steps based on the boundary threshold voltages D _A and D _C are required. Similarly, decoding of the upper page is confused by the “intermediate” state if the upper page is not programmed. Again, the LM flag indicates whether the upper page has been programmed. If the upper page is not programmed, the read data is reset to “1” which means that the upper page data is not programmed.

  FIG. 6A illustrates the effect of GIDL induced errors on various memory cells of a conventional NAND string. The NAND string shown in this example has 32 serial memory cells corresponding to the word lines WL0 to WL31. Each memory cell is partitioned to store any one of four memory states (2-bit representation). FIG. 6A shows threshold voltage distributions in four memory states in three groups of memory cells and three memory cells of a NAND string. Two of the three locations are adjacent to the select transistor (or gate). Specifically, the control gate of the memory cell adjacent to the source end of the string is connected to the word line WL0, and the control gate of the memory cell adjacent to the drain end of the string is connected to the word line WL31. The remaining memory cells are located in the core region of the NAND string and correspond to the word lines WL1 to WL30.

  As can be seen from FIG. 6A, the normal distribution (intermediate graph) of the four memory states is that of the memory cells (WL1 to WL30) located in the core region. However, due to the GIDL effect that becomes prominent at the end of the NAND string, the distribution (bottom graph) of the memory cells (WL0) adjacent to the source selection transistor is shifted to a high threshold voltage. This may cause an error. For example, a shifted “01” state may be erroneously read as a “00” state. Similarly, the memory cell (WL31) adjacent to the drain select transistor suffers the same error. (See the graph above.)

  FIG. 6B shows the memory state partition of the memory cells in the exemplary NAND string corresponding to FIG. 6A. This example is a 32-cell NAND string in the column direction of the memory array. One page of NAND strings is formed by one bank of NAND strings in the row direction. A word line is coupled to all control gates of each memory cell along the row. Each NAND string has word lines WL0 to WL31, and further has select lines SGS and SGD corresponding to two rows of select transistors located at the end of the NAND string bank. Programming and reading are performed in parallel on one page of memory cells. In one embodiment, even (one) pages are formed by even-numbered memory cell rows, and one (odd) pages are formed by odd-numbered memory cell rows. In another embodiment, a page is formed by successive memory cells along a row or by a portion thereof.

  In the conventional scheme seen in FIG. 6B, each memory cell is partitioned to store any one of four memory states. As described in the examples of FIGS. 4A to 4E and FIGS. 5A to 5E, four memory states are encoded with two bits. The two logical bits can be represented as a lower bit (“L”) and an upper bit (“U”). That is, the memory cell of the NAND string is configured to store 2-bit data, specifically, “L / U”.

  FIG. 7A shows a prior solution that introduces additional dummy memory cells at the end of the memory cell chain in a NAND string. In this case, the dummy memory cell adjacent to the selection transistor and the end of the NAND string suffers the maximum GIDL effect (see the upper and lower graphs). However, since the dummy cell is not used for data storage, it has an effect on the dummy cell. Is not a problem. Further, in order to reduce the GIDL effect, an intermediate voltage can be applied to the word line of the dummy cell in the same manner as the method proposed in US Published Patent Application No. 2006-0198195 (Patent Document 6). Thus, the memory cells connected to WL0-WL31 are not affected (see the middle graph).

  FIG. 7B shows the memory state partition of the memory cell in a typical NAND string with the same dummy cells as in FIG. 7A. In this NAND string, normal memory cells (WL0 to WL31) are configured to store 2-bit data of lower and upper bits. Additional dummy cells are not programmed.

  FIG. 7C shows the memory state partition of the memory cell in a typical NAND string with the addition of two dummy cells similar to FIG. 7A. In this NAND string, normal memory cells (WL0 to WL31) are configured to store 2-bit data of lower and upper bits. Additional dummy cells located at the end of the memory cell chain are not programmed.

Adaptive Memory State Partitioning FIG. 8A illustrates a scheme for overcoming GIDL errors in the end memory cells of a NAND string according to a general embodiment of the present invention. Basically, minimal changes are required from the conventional case shown in FIG. 6A. The main difference is that the memory cell located at the end of the NAND string is configured to store binary data instead of multi-state data. By dividing the threshold window of the end memory cells (eg, WL0 and WL32) into two states that are more spaced than in the four state, this extraneous error can be detected even if there is a GIDL induced error at the end of the NAND string. The two states can be distinguished by the margin. When 2-bit data is stored in each of 32 cells in a conventional NAND string (32 × 2 = 64 bits per string), this method allows the same 64-bit capacity (1 string) by adding only one memory cell to the chain. (31 × 2 + 2 × 1 bit) is provided.

  FIG. 8B illustrates memory state partitioning of memory cells in a typical NAND string according to the adaptive memory state partitioning scheme of FIG. 8A. With this NAND string, the core memory cells (WL1 to WL31) are configured to store 2-bit data of lower and upper bits as usual. The two end cells (WL0 and WL32) are configured to store binary data, and the margin between states is larger than usual.

  FIG. 8C shows a preferred alternative scheme that uses the 2-bit LM encoding described in FIGS. 5A-5E. In the LM encoding described with reference to FIGS. 5A to 5E, two bits can be programmed in two separate steps. In the first step, the lower logical bit is programmed, and in the second step, the upper logical bit is programmed in the same memory cell. As a characteristic of LM coding, the lower bit section has a wider margin than that of the upper bits or the joint two bits. For this reason, the programming of the lower bits is more robust than the upper bits in terms of failure. In order to minimize changes from existing memory systems, the low-order bit (or page) programming of the LM code is preferably used for binary bit programming for the two end cells in the NAND chain. However, it will be appreciated that one of the binary bits is used to represent the lower bits of the 2-bit LM code and the other binary bits are used to represent the upper bits of the 2-bit LM code.

FIG. 9 is a flow diagram illustrating an adaptive memory partitioning scheme.
Step 300: Providing a non-volatile memory having a memory cell array configured in the form of a NAND string, each memory cell being a charge storage transistor having a source and drain, a charge storage element, and a control gate, each NAND string Has a source end and a drain end and is formed by a series of charge storage transistors that are daisy chained to the source of an adjacent charge storage transistor by the drain of one cell and sourced by a source select transistor. It can be switched to the end, and can be switched to the drain end by the drain selection transistor.
Step 310: Distinguish memory cells of each NAND string into a first group and a second group, wherein the second group of memory cells is adjacent to the source selection transistor or the drain selection transistor, and the first group of memory cells Is the complement of the second group.
Step 320: Store data of a first predetermined number of bits in each memory cell of the first group.
Step 330: Accumulating data of a second predetermined number of bits less than the first predetermined number in each memory cell of the second group.

  In one embodiment of designing a memory to store 2 bits per cell, one bit of such 2 bits per unit can be stored in a memory cell adjacent to one end of the NAND string and the other bit is It can be stored in another memory cell adjacent to the other end.

  In another embodiment in which the memory is designed to store 3 bits per cell, 2 bits of such 3 bits per unit can be stored in one memory cell and one bit is in the other memory cell. Can accumulate.

  All patents, patent applications, articles, books, specifications, other publications, documents and things referred to herein are hereby incorporated by reference in their entirety for all purposes. If there is a conflict or discrepancy in the definition or use of a term between any of the incorporated publications, documents, or things and the body of this specification, the definition or use of the term in this specification shall prevail. And

  While the invention has been described with reference to various embodiments, it is understood that changes and modifications can be made without departing from the scope of the invention as defined by the appended claims and their equivalents. I understand. Any reference material referred to herein is hereby incorporated by reference.

Claims (44)

Each memory cell is a charge storage transistor having a source and a drain, a charge storage element, and a control gate, and each NAND string has a source end and a drain end. And formed by a series of charge storage transistors, the series of charge storage transistors being daisy chained to the source of an adjacent charge storage transistor by the drain of one cell, switchable to the source end by a source selection transistor, and A method of storing data in a non-volatile memory that can be switched to a drain end by a drain selection transistor,
Distinguishing the memory cells of each NAND string into a second group of memory cells adjacent to the source selection transistor or the drain selection transistor and a first group of memory cells that are complementary to the second group; ,
Storing data of a first predetermined number of bits in each memory cell of the first group, and storing data of a second predetermined number of bits less than the first predetermined number in each memory cell of the second group And steps to
Including methods. The method of claim 1, wherein
The storing step is a method in which one page of memory cells having a common word line among the corresponding pages of the NAND string is programmed in parallel. The method of claim 2, wherein
A method in which a memory cell page is erased by first removing charge from each charge storage element. The method of claim 1, wherein
The first predetermined number of bits of data is 2-bit data. The method of claim 4, wherein
The second memory cell group includes two memory cells each storing one bit of two bits of data. The method of claim 4, wherein
2-bit data consists of a logical first bit and a logical second bit,
The second group includes two memory cells, one memory cell storing a logic first bit and the other memory cell storing a logic second bit. The method of claim 6 wherein:
The second group includes two memory cells each storing one logical bit of logical bits of 2-bit data. The method of claim 1, wherein
A method in which the first predetermined number of bits of data is 3-bit data. The method of claim 8, wherein
The method wherein the second group of memory cells includes two memory cells each storing one or two bits of 3-bit data. The method of claim 8, wherein
The 3-bit data consists of a logic first bit, a logic second bit, and a logic third bit, the second group includes two memory cells, one memory cell stores the logic first bit, The memory cell stores a logic second bit and a third bit. The method of claim 10, wherein:
The second group includes two memory cells each storing one or two logic bits of the logic bits of the 3-bit data. Each memory cell is a charge storage transistor having a source and a drain, a charge storage element, and a control gate, and each NAND string has a source end and a drain end. And formed by a series of charge storage transistors, the series of charge storage transistors being daisy chained to the source of an adjacent charge storage transistor by the drain of one cell, switchable to the source end by a source selection transistor, and A method of storing data in a non-volatile memory that can be switched to a drain end by a drain selection transistor,
Distinguishing the memory cells of each NAND string into a second group of memory cells adjacent to the source selection transistor or the drain selection transistor and a first group of memory cells that are complementary to the second group; ,
Configuring each memory cell of the first group to store data of a first predetermined number of bits;
Configuring each memory cell of the second group to store data of a second predetermined number of bits less than the first predetermined number;
Including methods. The method of claim 12, wherein
The storing step is a method in which one page of memory cells having a common word line among the corresponding pages of the NAND string is programmed in parallel. 14. The method of claim 13, wherein
A method in which a memory cell page is erased by first removing charge from each charge storage element. The method of claim 12, wherein
The first predetermined number of bits of data is 2-bit data. The method of claim 15, wherein
The second memory cell group includes two memory cells each storing one bit of two bits of data. The method of claim 15, wherein
2-bit data consists of a logical first bit and a logical second bit,
The second group includes two memory cells, one memory cell storing a logic first bit and the other memory cell storing a logic second bit. The method of claim 17, wherein
The second group includes two memory cells each storing one logical bit of logical bits of 2-bit data. The method of claim 12, wherein
A method in which the first predetermined number of bits of data is 3-bit data. The method of claim 19, wherein
The method wherein the second group of memory cells includes two memory cells each storing one or two bits of 3-bit data. The method of claim 19, wherein
The 3-bit data consists of a logic first bit, a logic second bit, and a logic third bit, the second group includes two memory cells, one memory cell stores the logic first bit, The memory cell stores a logic second bit and a third bit. The method of claim 21, wherein
The second group includes two memory cells each storing one or two logic bits of the logic bits of the 3-bit data. Non-volatile memory,
Comprising a memory cell array configured in the form of a NAND string;
Each memory cell is a charge storage transistor having a source and drain, a charge storage element, and a control gate,
Each NAND string has a source end and a drain end and is formed by a series of charge storage transistors that are daisy chained to the source of an adjacent charge storage transistor by the drain of one cell, and source select The transistor can be switched to the source end, and the drain selection transistor can be switched to the drain end.
Each NAND string includes a first group and a second group of memory cells, the second group of memory cells being adjacent to the source selection transistor or the drain selection transistor, and the first group of memory cells being the first in the NAND string. Is the complement of two groups,
Means for storing data of a first predetermined number of bits in each memory cell of the first group;
Means for storing data of a second predetermined number of bits less than the first predetermined number in each memory cell of the second group;
Non-volatile memory also provided. 24. The non-volatile memory of claim 23.
The means for storing is a non-volatile memory by programming one page of memory cells having a common word line in the corresponding page of the NAND string in parallel. The non-volatile memory of claim 24.
A memory cell page is a non-volatile memory that is erased by first removing charge from each charge storage element. 24. The non-volatile memory of claim 23.
The non-volatile memory in which the first predetermined number of bits of data is 2-bit data. The non-volatile memory of claim 26.
The second memory cell group is a nonvolatile memory including two memory cells each storing one bit of bits of 2-bit data. The non-volatile memory of claim 26.
2-bit data consists of a logical first bit and a logical second bit,
A second group includes two memory cells, one memory cell storing a logical first bit and the other memory cell storing a logical second bit. The non-volatile memory of claim 28.
The second group is a nonvolatile memory including two memory cells each storing one logical bit of logical bits of 2-bit data. 24. The non-volatile memory of claim 23.
The data of the first predetermined number of bits is a non-volatile memory that is 3-bit data. The non-volatile memory according to claim 30,
The second memory cell group is a non-volatile memory including two memory cells each storing 1 or 2 bits of 3-bit data. The non-volatile memory according to claim 30,
The 3-bit data consists of a logic first bit, a logic second bit, and a logic third bit, the second group includes two memory cells, one memory cell stores the logic first bit, These memory cells are non-volatile memories that store logic second and third bits. The non-volatile memory according to claim 32.
The second group is a nonvolatile memory including two memory cells each storing one or two logic bits of the logic bits of the 3-bit data. Non-volatile memory,
Comprising a memory cell array configured in the form of a NAND string;
Each memory cell is a charge storage transistor having a source and drain, a charge storage element, and a control gate,
Each NAND string has a source end and a drain end and is formed by a series of charge storage transistors that are daisy chained to the source of an adjacent charge storage transistor by the drain of one cell, and source select The transistor can be switched to the source end, and the drain selection transistor can be switched to the drain end.
Each NAND string includes a first group and a second group of memory cells, the second group of memory cells being adjacent to the source selection transistor or the drain selection transistor, and the first group of memory cells being the first in the NAND string. Is the complement of two groups,
The first group of memory cells is configured to be programmable to any one of the first predetermined number of memory states;
The second group of memory cells is configured to be programmable to any one of a second predetermined number of memory states, the second predetermined number being a non-volatile memory that is less than the first predetermined number. The non-volatile memory of claim 34.
A non-volatile memory in which one page of memory cells having a common word line in the corresponding page of the NAND string is programmed and read as a unit. 36. The nonvolatile memory of claim 35.
A memory cell page is a non-volatile memory that is first erased by removing charge from each charge storage element. The non-volatile memory of claim 34.
The non-volatile memory in which the first predetermined number of bits of data is 2-bit data. 38. The non-volatile memory according to claim 37.
The second memory cell group is a nonvolatile memory including two memory cells each storing one bit of bits of 2-bit data. 38. The non-volatile memory according to claim 37.
2-bit data consists of a logical first bit and a logical second bit,
A second group includes two memory cells, one memory cell storing a logical first bit and the other memory cell storing a logical second bit. 40. The non-volatile memory of claim 39.
The second group is a nonvolatile memory including two memory cells each storing one logical bit of logical bits of 2-bit data. The non-volatile memory of claim 34.
The data of the first predetermined number of bits is a non-volatile memory that is 3-bit data. The nonvolatile memory of claim 41,
The second memory cell group is a non-volatile memory including two memory cells each storing 1 or 2 bits of 3-bit data. The nonvolatile memory of claim 41,
The 3-bit data consists of a logic first bit, a logic second bit, and a logic third bit, the second group includes two memory cells, one memory cell stores the logic first bit, The non-volatile memory stores the logic second bit and the third bit. 44. The memory of claim 43.
The second group is a nonvolatile memory including two memory cells each storing one or two logic bits of the logic bits of the 3-bit data.

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