JP2010503212A5 - - Google Patents

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Publication number
JP2010503212A5
JP2010503212A5 JP2009526696A JP2009526696A JP2010503212A5 JP 2010503212 A5 JP2010503212 A5 JP 2010503212A5 JP 2009526696 A JP2009526696 A JP 2009526696A JP 2009526696 A JP2009526696 A JP 2009526696A JP 2010503212 A5 JP2010503212 A5 JP 2010503212A5
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JP
Japan
Prior art keywords
mask layer
hard mask
semiconductor substrate
forming
layer
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Granted
Application number
JP2009526696A
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English (en)
Japanese (ja)
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JP2010503212A (ja
JP5281008B2 (ja
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Publication date
Priority claimed from US11/840,299 external-priority patent/US20080057612A1/en
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Publication of JP2010503212A publication Critical patent/JP2010503212A/ja
Publication of JP2010503212A5 publication Critical patent/JP2010503212A5/ja
Application granted granted Critical
Publication of JP5281008B2 publication Critical patent/JP5281008B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009526696A 2006-09-01 2007-08-29 半導体基板に形成された素子を分離する方法 Active JP5281008B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US84207506P 2006-09-01 2006-09-01
US60/842,075 2006-09-01
US11/840,299 US20080057612A1 (en) 2006-09-01 2007-08-17 Method for adding an implant at the shallow trench isolation corner in a semiconductor substrate
US11/840,299 2007-08-17
PCT/US2007/018997 WO2008030371A2 (en) 2006-09-01 2007-08-29 Implant at shallow trench isolation corner

Publications (3)

Publication Number Publication Date
JP2010503212A JP2010503212A (ja) 2010-01-28
JP2010503212A5 true JP2010503212A5 (https=) 2010-10-14
JP5281008B2 JP5281008B2 (ja) 2013-09-04

Family

ID=39031210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009526696A Active JP5281008B2 (ja) 2006-09-01 2007-08-29 半導体基板に形成された素子を分離する方法

Country Status (7)

Country Link
US (1) US20080057612A1 (https=)
EP (1) EP2057675B1 (https=)
JP (1) JP5281008B2 (https=)
KR (1) KR101329462B1 (https=)
DE (1) DE602007009548D1 (https=)
TW (1) TWI413167B (https=)
WO (1) WO2008030371A2 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100148230A1 (en) * 2008-12-11 2010-06-17 Stevens Eric G Trench isolation regions in image sensors
US7968424B2 (en) * 2009-01-16 2011-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of implantation
US7838325B2 (en) * 2009-02-13 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method to optimize substrate thickness for image sensor device
US9196547B2 (en) * 2009-04-03 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Dual shallow trench isolation and related applications
US9000500B2 (en) 2009-12-30 2015-04-07 Omnivision Technologies, Inc. Image sensor with doped transfer gate
US8048711B2 (en) * 2009-12-30 2011-11-01 Omnivision Technologies, Inc. Method for forming deep isolation in imagers
US8367512B2 (en) 2010-08-30 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned implants to reduce cross-talk of imaging sensors
FR2981502A1 (fr) * 2011-10-18 2013-04-19 St Microelectronics Crolles 2 Procede de realisation d'au moins une tranchee d'isolation profonde
US9040891B2 (en) * 2012-06-08 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Image device and methods of forming the same
US9355888B2 (en) 2012-10-01 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Implant isolated devices and method for forming the same
US9673245B2 (en) * 2012-10-01 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Implant isolated devices and method for forming the same
US8969997B2 (en) * 2012-11-14 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structures and methods of forming the same
WO2014209421A1 (en) * 2013-06-29 2014-12-31 Sionyx, Inc. Shallow trench textured regions and associated methods
JP6362449B2 (ja) 2014-07-01 2018-07-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
KR102399338B1 (ko) * 2014-09-12 2022-05-19 삼성전자주식회사 이미지 센서의 제조 방법
US9647022B2 (en) * 2015-02-12 2017-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-layer structure for high aspect ratio etch
US10580789B2 (en) * 2017-07-10 2020-03-03 Macronix International Co., Ltd. Semiconductor device having etching control layer in substrate and method of fabricating the same
CN109256389B (zh) * 2017-07-13 2021-06-11 旺宏电子股份有限公司 半导体元件及其制造方法
CN110021559B (zh) * 2018-01-09 2021-08-24 联华电子股份有限公司 半导体元件及其制作方法
US11923205B2 (en) * 2021-12-17 2024-03-05 United Microelectronics Corporation Method for manufacturing semiconductor device
CN119153486B (zh) * 2023-06-08 2025-10-10 长鑫存储技术有限公司 半导体结构及其制备方法

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JPS6052580B2 (ja) * 1978-10-20 1985-11-20 三洋電機株式会社 半導体装置に於ける表面保護膜の製法
JPH01125935A (ja) * 1987-11-11 1989-05-18 Seiko Instr & Electron Ltd 半導体装置の製造方法
JPH0621047A (ja) * 1992-05-08 1994-01-28 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US5780353A (en) * 1996-03-28 1998-07-14 Advanced Micro Devices, Inc. Method of doping trench sidewalls before trench etching
US5874346A (en) * 1996-05-23 1999-02-23 Advanced Micro Devices, Inc. Subtrench conductor formation with large tilt angle implant
US5891787A (en) * 1997-09-04 1999-04-06 Advanced Micro Devices, Inc. Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure
US6030898A (en) * 1997-12-19 2000-02-29 Advanced Micro Devices, Inc. Advanced etching method for VLSI fabrication
US6096612A (en) * 1998-04-30 2000-08-01 Texas Instruments Incorporated Increased effective transistor width using double sidewall spacers
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TW391051B (en) * 1998-11-06 2000-05-21 United Microelectronics Corp Method for manufacturing shallow trench isolation structure
TW406350B (en) * 1998-12-07 2000-09-21 United Microelectronics Corp Method for manufacturing the shallow trench isolation area
TW486774B (en) * 1998-12-19 2002-05-11 United Microelectronics Corp Shallow trench isolation technique joining field oxide layer
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US6150235A (en) * 2000-01-24 2000-11-21 Worldwide Semiconductor Manufacturing Corp. Method of forming shallow trench isolation structures
US6437417B1 (en) * 2000-08-16 2002-08-20 Micron Technology, Inc. Method for making shallow trenches for isolation
US6624016B2 (en) * 2001-02-22 2003-09-23 Silicon-Based Technology Corporation Method of fabricating trench isolation structures with extended buffer spacers
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JP4087108B2 (ja) * 2001-12-10 2008-05-21 シャープ株式会社 不揮発性半導体記憶装置及びその製造方法
KR100480897B1 (ko) * 2002-12-09 2005-04-07 매그나칩 반도체 유한회사 반도체소자의 소자분리막 형성방법
US7102184B2 (en) * 2003-06-16 2006-09-05 Micron Technology, Inc. Image device and photodiode structure
US7067387B2 (en) * 2003-08-28 2006-06-27 Taiwan Semiconductor Manufacturing Company Method of manufacturing dielectric isolated silicon structure
US6951780B1 (en) * 2003-12-18 2005-10-04 Matrix Semiconductor, Inc. Selective oxidation of silicon in diode, TFT, and monolithic three dimensional memory arrays
US7154136B2 (en) * 2004-02-20 2006-12-26 Micron Technology, Inc. Isolation structures for preventing photons and carriers from reaching active areas and methods of formation
US7279397B2 (en) * 2004-07-27 2007-10-09 Texas Instruments Incorporated Shallow trench isolation method
US7045410B2 (en) * 2004-07-27 2006-05-16 Texas Instruments Incorporated Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI)
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