JP2010267368A - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP2010267368A
JP2010267368A JP2010091039A JP2010091039A JP2010267368A JP 2010267368 A JP2010267368 A JP 2010267368A JP 2010091039 A JP2010091039 A JP 2010091039A JP 2010091039 A JP2010091039 A JP 2010091039A JP 2010267368 A JP2010267368 A JP 2010267368A
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JP
Japan
Prior art keywords
circuit
layer
electrode
memory element
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2010091039A
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English (en)
Japanese (ja)
Other versions
JP2010267368A5 (enExample
Inventor
Toshihiko Saito
利彦 齋藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2010091039A priority Critical patent/JP2010267368A/ja
Publication of JP2010267368A publication Critical patent/JP2010267368A/ja
Publication of JP2010267368A5 publication Critical patent/JP2010267368A5/ja
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
JP2010091039A 2009-04-17 2010-04-12 半導体記憶装置 Withdrawn JP2010267368A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010091039A JP2010267368A (ja) 2009-04-17 2010-04-12 半導体記憶装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009100811 2009-04-17
JP2010091039A JP2010267368A (ja) 2009-04-17 2010-04-12 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2010267368A true JP2010267368A (ja) 2010-11-25
JP2010267368A5 JP2010267368A5 (enExample) 2013-05-16

Family

ID=42980871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010091039A Withdrawn JP2010267368A (ja) 2009-04-17 2010-04-12 半導体記憶装置

Country Status (2)

Country Link
US (1) US8964489B2 (enExample)
JP (1) JP2010267368A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019003014A1 (ja) * 2017-06-26 2019-01-03 株式会社半導体エネルギー研究所 半導体装置、電子機器
JP2020155193A (ja) * 2019-03-22 2020-09-24 タワー パートナーズ セミコンダクター株式会社 半導体装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011125455A1 (en) 2010-04-09 2011-10-13 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor memory device
US8659015B2 (en) * 2011-03-04 2014-02-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN113793628B (zh) 2012-12-27 2024-06-07 英特尔公司 电平移位器
US11183258B1 (en) * 2020-12-07 2021-11-23 Semiconductor Components Industries, Llc Circuit and method for programming a one-time programmable memory
JP7781010B2 (ja) * 2022-03-30 2025-12-05 キヤノン株式会社 記憶装置、液体吐出ヘッドおよび液体吐出装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223653A (ja) * 1988-07-12 1990-01-25 Seiko Epson Corp 集積回路
JPH0346198A (ja) * 1989-07-14 1991-02-27 Seiko Instr Inc 半導体集積回路装置
JPH07297293A (ja) * 1994-04-28 1995-11-10 Tadahiro Omi シリサイド反応を利用した半導体装置
US5684741A (en) * 1995-12-26 1997-11-04 Intel Corporation Auto-verification of programming flash memory cells
JP2001344981A (ja) * 2000-06-05 2001-12-14 Hitachi Ltd 不揮発性半導体記憶装置
JP2003123496A (ja) * 2001-07-31 2003-04-25 Hewlett Packard Co <Hp> Ｗｏｒｍ記憶装置のための書き込みパルス制限
JP2006196079A (ja) * 2005-01-13 2006-07-27 Toshiba Corp 不揮発性半導体記憶装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818082A (en) 1988-05-27 1989-04-04 Eastman Kodak Company Compact wide-angle close-focus SLR zoom lens
US5422842A (en) * 1993-07-08 1995-06-06 Sundisk Corporation Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells
US5418751A (en) * 1993-09-29 1995-05-23 Texas Instruments Incorporated Variable frequency oscillator controlled EEPROM charge pump
DE69721252D1 (de) * 1997-09-29 2003-05-28 St Microelectronics Srl Verfahren und Vorrichtung zum analogen Programmieren einer Flash-EEPROM-Speicherzelle mit Selbstprüfung
KR100327421B1 (ko) * 1997-12-31 2002-07-27 주식회사 하이닉스반도체 비휘발성 메모리 소자의 프로그램 시스템 및 그의 프로그램 방법
JP4231572B2 (ja) * 1998-07-07 2009-03-04 沖電気工業株式会社 電圧監視回路及びそれを内蔵したメモリカード
JP2003088103A (ja) 2001-09-17 2003-03-20 Nec Microsystems Ltd チャージポンプ方式電源回路
JP4222768B2 (ja) * 2002-03-27 2009-02-12 三洋電機株式会社 昇圧装置及びこれを用いた撮像装置
JP2004146082A (ja) * 2002-10-21 2004-05-20 Semiconductor Energy Lab Co Ltd 表示装置
US6940744B2 (en) * 2002-10-31 2005-09-06 Unity Semiconductor Corporation Adaptive programming technique for a re-writable conductive memory device
JP2008004038A (ja) * 2006-06-26 2008-01-10 Ricoh Co Ltd ボルテージレギュレータ
WO2008044559A1 (en) * 2006-10-02 2008-04-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102646681B (zh) 2006-10-04 2015-08-05 株式会社半导体能源研究所 半导体器件
JP5361176B2 (ja) * 2006-12-13 2013-12-04 株式会社半導体エネルギー研究所 半導体装置
JP5137545B2 (ja) * 2006-12-25 2013-02-06 株式会社半導体エネルギー研究所 半導体装置及びその駆動方法
US7477092B2 (en) * 2006-12-29 2009-01-13 Sandisk Corporation Unified voltage generation apparatus with improved power efficiency
JP5324161B2 (ja) * 2007-08-30 2013-10-23 株式会社半導体エネルギー研究所 半導体装置
US8238158B2 (en) * 2010-08-04 2012-08-07 Texas Instruments Incorporated Programming of memory cells in a nonvolatile memory using an active transition control

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223653A (ja) * 1988-07-12 1990-01-25 Seiko Epson Corp 集積回路
JPH0346198A (ja) * 1989-07-14 1991-02-27 Seiko Instr Inc 半導体集積回路装置
JPH07297293A (ja) * 1994-04-28 1995-11-10 Tadahiro Omi シリサイド反応を利用した半導体装置
US5684741A (en) * 1995-12-26 1997-11-04 Intel Corporation Auto-verification of programming flash memory cells
JP2001344981A (ja) * 2000-06-05 2001-12-14 Hitachi Ltd 不揮発性半導体記憶装置
JP2003123496A (ja) * 2001-07-31 2003-04-25 Hewlett Packard Co <Hp> Ｗｏｒｍ記憶装置のための書き込みパルス制限
JP2006196079A (ja) * 2005-01-13 2006-07-27 Toshiba Corp 不揮発性半導体記憶装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019003014A1 (ja) * 2017-06-26 2019-01-03 株式会社半導体エネルギー研究所 半導体装置、電子機器
JPWO2019003014A1 (ja) * 2017-06-26 2020-07-09 株式会社半導体エネルギー研究所 半導体装置、電子機器
US10784885B2 (en) 2017-06-26 2020-09-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
JP7265986B2 (ja) 2017-06-26 2023-04-27 株式会社半導体エネルギー研究所 半導体装置、電子機器
JP2020155193A (ja) * 2019-03-22 2020-09-24 タワー パートナーズ セミコンダクター株式会社 半導体装置

Also Published As

Publication number Publication date
US8964489B2 (en) 2015-02-24
US20100265754A1 (en) 2010-10-21

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