JP2010124102A5 - - Google Patents

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Publication number
JP2010124102A5
JP2010124102A5 JP2008294349A JP2008294349A JP2010124102A5 JP 2010124102 A5 JP2010124102 A5 JP 2010124102A5 JP 2008294349 A JP2008294349 A JP 2008294349A JP 2008294349 A JP2008294349 A JP 2008294349A JP 2010124102 A5 JP2010124102 A5 JP 2010124102A5
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JP
Japan
Prior art keywords
frequency
divided clock
outputs
controlled oscillator
voltage controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008294349A
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English (en)
Japanese (ja)
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JP2010124102A (ja
JP5139958B2 (ja
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Application filed filed Critical
Priority to JP2008294349A priority Critical patent/JP5139958B2/ja
Priority claimed from JP2008294349A external-priority patent/JP5139958B2/ja
Publication of JP2010124102A publication Critical patent/JP2010124102A/ja
Publication of JP2010124102A5 publication Critical patent/JP2010124102A5/ja
Application granted granted Critical
Publication of JP5139958B2 publication Critical patent/JP5139958B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2008294349A 2008-11-18 2008-11-18 デッドロック検出回路およびデッドロック復帰回路 Expired - Fee Related JP5139958B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008294349A JP5139958B2 (ja) 2008-11-18 2008-11-18 デッドロック検出回路およびデッドロック復帰回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008294349A JP5139958B2 (ja) 2008-11-18 2008-11-18 デッドロック検出回路およびデッドロック復帰回路

Publications (3)

Publication Number Publication Date
JP2010124102A JP2010124102A (ja) 2010-06-03
JP2010124102A5 true JP2010124102A5 (enExample) 2011-12-22
JP5139958B2 JP5139958B2 (ja) 2013-02-06

Family

ID=42325060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008294349A Expired - Fee Related JP5139958B2 (ja) 2008-11-18 2008-11-18 デッドロック検出回路およびデッドロック復帰回路

Country Status (1)

Country Link
JP (1) JP5139958B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9209960B1 (en) * 2014-11-21 2015-12-08 Xilinx, Inc. Fast locking CDR for burst mode
CN112305413B (zh) * 2019-12-17 2023-05-30 成都华微电子科技股份有限公司 一种参考时钟丢失检测电路与检测方法
CN113452348B (zh) * 2020-03-25 2025-02-21 络明芯微电子(厦门)有限公司 展频时脉产生系统
TWI739556B (zh) * 2020-08-19 2021-09-11 瑞昱半導體股份有限公司 時脈死結檢測系統、方法以及非暫態電腦可讀取媒體
CN114578153B (zh) * 2022-01-26 2023-05-16 奉加科技(上海)股份有限公司 一种晶振振荡检测电路
KR20240109707A (ko) * 2023-01-05 2024-07-12 매그나칩믹스드시그널 유한회사 데드락 리커버리 회로 및 데드락 리커버리 방법, 이를 포함하는 pll 회로
JP2024122688A (ja) * 2023-02-28 2024-09-09 ラピステクノロジー株式会社 Ｐｌｌ回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306557A (ja) * 2007-06-08 2008-12-18 Panasonic Corp 位相ロック回路

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