JP2010109353A - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP2010109353A
JP2010109353A JP2009228249A JP2009228249A JP2010109353A JP 2010109353 A JP2010109353 A JP 2010109353A JP 2009228249 A JP2009228249 A JP 2009228249A JP 2009228249 A JP2009228249 A JP 2009228249A JP 2010109353 A JP2010109353 A JP 2010109353A
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Prior art keywords
film
substrate
insulating film
semiconductor film
manufacturing
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JP2009228249A
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English (en)
Japanese (ja)
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JP2010109353A5 (enExample
Inventor
Akihisa Shimomura
明久 下村
Hajime Tokunaga
肇 徳永
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2009228249A priority Critical patent/JP2010109353A/ja
Publication of JP2010109353A publication Critical patent/JP2010109353A/ja
Publication of JP2010109353A5 publication Critical patent/JP2010109353A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2009228249A 2008-10-02 2009-09-30 Ｓｏｉ基板の作製方法 Withdrawn JP2010109353A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009228249A JP2010109353A (ja) 2008-10-02 2009-09-30 Ｓｏｉ基板の作製方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008257032 2008-10-02
JP2009228249A JP2010109353A (ja) 2008-10-02 2009-09-30 Ｓｏｉ基板の作製方法

Publications (2)

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JP2010109353A true JP2010109353A (ja) 2010-05-13
JP2010109353A5 JP2010109353A5 (enExample) 2012-10-11

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JP2009228249A Withdrawn JP2010109353A (ja) 2008-10-02 2009-09-30 Ｓｏｉ基板の作製方法

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US (1) US8741740B2 (enExample)
JP (1) JP2010109353A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180100496A (ko) * 2017-03-01 2018-09-11 가부시기가이샤 디스코 반도체 잉곳의 검사 방법, 검사 장치 및 레이저 가공 장치

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US8703521B2 (en) 2009-06-09 2014-04-22 International Business Machines Corporation Multijunction photovoltaic cell fabrication
US8802477B2 (en) * 2009-06-09 2014-08-12 International Business Machines Corporation Heterojunction III-V photovoltaic cell fabrication
KR101824537B1 (ko) * 2010-10-01 2018-03-15 삼성디스플레이 주식회사 박막 트랜지스터 및 이를 포함하는 유기 발광 디스플레이
US8766361B2 (en) * 2010-12-16 2014-07-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
US8318575B2 (en) * 2011-02-07 2012-11-27 Infineon Technologies Ag Compressive polycrystalline silicon film and method of manufacture thereof
FR2978604B1 (fr) * 2011-07-28 2018-09-14 Soitec Procede de guerison de defauts dans une couche semi-conductrice
WO2014163188A1 (ja) * 2013-04-04 2014-10-09 富士電機株式会社 半導体デバイスの製造方法
KR20150012530A (ko) * 2013-07-25 2015-02-04 삼성디스플레이 주식회사 전사용 도너 기판 및 유기 발광 표시 장치의 제조 방법
CN107195689B (zh) * 2017-07-21 2021-01-22 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、oled显示面板
US20230117013A1 (en) * 2021-10-14 2023-04-20 Applied Materials, Inc. SUBSTRATE PROCESSING FOR GaN GROWTH

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JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2000294754A (ja) * 1999-04-07 2000-10-20 Denso Corp 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置
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JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2000294754A (ja) * 1999-04-07 2000-10-20 Denso Corp 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置
JP2002305292A (ja) * 2001-04-06 2002-10-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハおよびその製造方法
JP2004063730A (ja) * 2002-07-29 2004-02-26 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180100496A (ko) * 2017-03-01 2018-09-11 가부시기가이샤 디스코 반도체 잉곳의 검사 방법, 검사 장치 및 레이저 가공 장치
KR102298614B1 (ko) 2017-03-01 2021-09-03 가부시기가이샤 디스코 반도체 잉곳의 검사 방법, 검사 장치 및 레이저 가공 장치

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US8741740B2 (en) 2014-06-03
US20100087045A1 (en) 2010-04-08

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