JP2010103519A - 半導体素子搭載用パッケージ基板とその製造方法 - Google Patents
半導体素子搭載用パッケージ基板とその製造方法 Download PDFInfo
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- JP2010103519A JP2010103519A JP2009222738A JP2009222738A JP2010103519A JP 2010103519 A JP2010103519 A JP 2010103519A JP 2009222738 A JP2009222738 A JP 2009222738A JP 2009222738 A JP2009222738 A JP 2009222738A JP 2010103519 A JP2010103519 A JP 2010103519A
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Abstract
大きく、パターン設計上の制約も小さく、トップパッケージとボトムパッケージ間の接続
を高密度で行うことが可能な半導体素子搭載用パッケージ基板とその製造方法を提供する
ことを目的とする。
【解決手段】キャビティ材と接着剤とを備え、これらを貫通するキャビティ層と、前記接着剤によって前記キャビティ層に積層されたベース層と、前記開口によって形成されたキャビティ部と、前記貫通孔によって形成された有底ビアと、を有する半導体素子搭載用パッケージ基板において、前記キャビティ層に内層回路が設けられ、この内層回路と接合するように、前記有底ビアの内壁に金属被覆がめっきにより形成され、前記有底ビアに導電樹脂が充填される半導体素子搭載用パッケージ基板とその製造方法である。
【選択図】図1
Description
(1) キャビティ材と接着剤とを備え、これらを貫通する開口及び貫通孔を有するキャビティ層と、前記接着剤によって前記キャビティ層に積層されたベース層と、前記開口によって形成されたキャビティ部と、前記貫通孔によって形成された有底ビアと、を有する半導体素子搭載用パッケージ基板において、前記キャビティ層に内層回路が設けられ、この内層回路と接合するように、前記有底ビアの内壁に金属被覆がめっきにより形成され、前記有底ビアに導電樹脂が充填される半導体素子搭載用パッケージ基板。
(2) 上記(1)において、有底ビアが、キャビティ材と接着剤とを貫通して、ベース層上のキャビティ層側に設けられる接続パッドに到るように設けられ、前記接続パッドと、前記キャビティ層上のベース層と反対側に設けられる接続端子Aとを接続する層間接続が形成される半導体素子搭載用パッケージ基板。
(3) 上記(1)または(2)において、キャビティ層に設けられる内層回路が貫通孔の周囲に設けられるアニュラリングであり、このアニュラリングと有底ビアの内壁に形成される金属被覆とが内層接続を形成する半導体素子搭載用パッケージ基板。
(4) 上記(1)から(3)の何れかにおいて、キャビティ層に設けられる内層回路が、前記キャビティ材上の接着剤側に設けられる半導体素子搭載用パッケージ基板。
(5) 上記(1)から(4)の何れかにおいて、キャビティ層に設けられる接着剤の厚みが、内層回路に対応する部分で、内層回路に対応しない部分に比べて薄い半導体素子搭載用パッケージ基板。
(6) 上記(1)から(5)の何れかにおいて、キャビティ層とベース層とを積層するための接着剤がエラストマー材である半導体素子搭載用パッケージ基板。
(7) 開口と貫通孔と内層回路を有するキャビティ材を形成する工程と、このキャビティ材に接着剤を介してベース層を積層し、前記開口によってキャビティ部を、前記貫通孔によって有底ビアを形成する工程と、前記有底ビアの内壁に金属被覆を形成し、この金属被覆と前記内層回路との内層接続を形成する工程と、前記金属被覆を下地として前記有底ビアに導電樹脂を充填する工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
[キャビティ層の作製]
図3に示すように、キャビティ材7として、両面に厚さ9μm、12μm、18μmの銅箔を張合わせた厚さ0.2mmのエポキシ樹脂ガラス布銅張積層板であるMCL−E679F(日立化成工業株式会社製、商品名)を準備した。NCドリルマシンであるMARK−100(日立精工株式会社製、商品名)によって、ガイド孔(図示しない。)と貫通孔A24を孔明けした。
図4に示すように、ベース材a28として、両面に厚さ12μmの銅箔を張合わせた厚さ0.06mmのエポキシ樹脂ガラス布銅張積層板であるMCL−E679F(日立化成工業株式会社製、商品名)にNCドリルマシンであるMARK−100(日立精工株式会社製、商品名)によって、貫通孔B39を明けた。
次に、この貫通孔B39のデスミア処理を過マンガン酸ナトリウム水溶液に温度85℃で6分間の条件で行い、無電解銅めっきであるCUST201(日立化成工業株式会社製、商品名)、硫酸銅10g/L、EDTA40g/L、ホルマリン10ml/L、pH12.2)に温度24℃、時間30分の条件で、貫通孔B39内を含むベース材a28の全面に0.5μmの下地銅めっきを行った。次に、硫酸銅めっきで温度30℃、電流密度1.5A/dm2、時間60分の条件で、貫通孔B39内を含むベース材a28の全面に、めっき厚20μmの電気銅めっき41を形成した。
次に、図5に示すように、キャビティ層5の接着剤8を仮付けした面と、ベース層6の感光性樹脂層10(ソルダーレジスト23)を形成した面が向き合うように重ね合わせ、真空プレスを用いて、圧力3MPa、温度175℃、保持時間1.5時間の条件で加圧加熱して積層一体化し、半導体素子搭載用パッケージ基板1とした。このとき、キャビティ層5に設けられた貫通孔A24が、ベース層6に設けられた接続パッド11によって塞がれるように積層され、接続パッド11を底面とした有底ビア13が、キャビティ層5に形成される。このとき、接着剤8が流動するが、キャビティ材7上の貫通孔A24の周囲に設けたアニュラリングが、貫通孔A24の周囲を完全に取り囲んだダムとして作用するので、接着剤8が貫通孔A24内側に流動するのを抑制することができた。貫通孔A24内側への接着剤の流動は、貫通孔A24の内壁から接続パッド11上へのしみ出し量(しみ出した距離)として観察することができ、本実施例では、片側で30μm以下のレベルであった。また、内層回路19が厚み(9μm、12μm、18μm)を有するため、内層回路19に対応する部分の接着剤8は、それ以外の部分に比べて、厚みが薄く形成される。この実施例1では、キャビティ材7上の内層回路19とベース層6の感光性樹脂10との間に挟まれる部分の接着剤の厚みは、1〜5μmであり、これらに挟まれていない部分に比べて薄くなった。
次に、図5に示すように、半導体素子2を、半導体素子搭載用パッケージ基板1のキャビティ部9内に、ダイボンディングフィルム(図示しない。)を用いて固定した後、この半導体素子2の上に、もう一つの半導体素子2をダイボンドフィルムを用いて固定した。その後、上段及び下段の半導体素子2と半導体素子搭載用パッケージ基板1のワイヤボンド端子12とをボンディングワイヤ4で接続した。このとき、ボンディングワイヤ4を含む上段の半導体素子2の最上部は、半導体素子搭載用パッケージ基板1の接続端子A14と同等以下の高さであった。
次に、接続端子A14にはんだペーストを印刷し、図6に示すように、上記実施例の半導体パッケージ36をボトムパッケージ35として使用し、トップパッケージ34の接続端子と位置合わせした後、リフローによって半導体パッケージ同士を接合した。このとき、半導体素子搭載用パッケージ基板1のキャビティ部9内に封止剤3のほぼ全体が収納され、ほとんど飛び出していないので、半導体パッケージ同士の接合のためのはんだボール径は、封止剤3の高さを考慮する必要がない。このため、はんだボール径はφ0.3mm以下で接合が可能であった。この結果、ボトムパッケージ35の封止剤3の最上部が、接続端子A14の上に設けられたはんだボール(φ0.3mm)の1/3以下の高さとなる状態で(即ち端子間距離44の1/3以下の高さである0.1mm以下程度で)、トップパッケージ34と接合することが可能であった。
[キャビティ層の作製]
キャビティ材7として用いるMCL−E679F(日立化成工業株式会社製、商品名)、の両面に貼り合わせる銅箔の厚みを9μmとした。また、キャビティ材7に仮付けする接着シートAS2600(日立化成工業株式会社製、商品名)の厚みを、10μmに変更した。これ以外は、実施例1と同様にしてキャビティ層5を作製した。このときの内層回路19の厚みは、9μmであった。
実施例1と同様に作製した。
実施例1と同様にして、キャビティ層5とベース層6とを積層し、半導体素子搭載用パッケージ基板を作製した。このとき接着剤8が流動するが、キャビティ材7上の貫通孔A24の周囲に設けたアニュラリングが、貫通孔A24の周囲を完全に取り囲んだダムとして作用するので、接着剤8が貫通孔A24内側に流動するのを抑制することができた。貫通孔A24内側への接着剤の流動は、貫通孔A24の内壁から接続パッド11上へのしみ出し量(しみ出した距離)として観察することができ、本実施例では、片側で20μm以下のレベルであった。また、内層回路19が厚み(9μm)を有するため、内層回路19に対応する部分の接着剤8は、それ以外の部分に比べて、厚みが薄く形成される。この実施例1では、キャビティ材7上の内層回路19とベース層6の感光性樹脂10との間に挟まれる部分の接着剤の厚みは、0.5〜2μmであり、これらに挟まれていない部分に比べて薄くなった。
[キャビティ層の作製]
キャビティ材7として用いるMCL−E679F(日立化成工業株式会社製、商品名)、の両面に貼り合わせる銅箔の厚みを、実施例1と同様に、9μm、12μm、18μmとした。また、キャビティ材7に仮付けする接着シートAS2600(日立化成工業株式会社製、商品名)の厚みを、50μmに変更した。これ以外は、実施例1と同様にしてキャビティ層5を作製した。このときの内層回路19の厚みは、9μm、12μm、18μmであった。
実施例1と同様に作製した。
実施例1と同様にして、キャビティ層5とベース層6とを積層し、半導体素子搭載用パッケージ基板を作製した。このとき接着剤8が流動するが、キャビティ材7上の貫通孔A24の周囲に設けたアニュラリングが、貫通孔A24の周囲を完全に取り囲んだダムとして作用するので、接着剤8が貫通孔A24内側に流動するのを抑制することができた。貫通孔A24内側への接着剤の流動は、貫通孔A24の内壁から接続パッド11上へのしみ出し量(しみ出した距離)として観察することができ、本実施例では、片側で50μm以下のレベルであった。また、内層回路19が厚み(9μm)を有するため、内層回路19に対応する部分の接着剤8は、それ以外の部分に比べて、厚みが薄く形成される。この実施例1では、キャビティ材7上の内層回路19とベース層6の感光性樹脂10との間に挟まれる部分の接着剤の厚みは、2〜7μmであり、これらに挟まれていない部分に比べて薄くなった。
[キャビティ層の作製]
キャビティ層5の回路形成の際に、一方の面については、貫通孔A24の周りに内層回路19を残さないように形成した。他方の面、即ち接続端子A14を形成する面については、ほぼ全面に銅箔40を残した。これ以外は、実施例1と同様にしてキャビティ材を作製した。
実施例1と同様に作製した。
実施例1と同様にして、キャビティ層5とベース層6とを積層し、半導体素子搭載用パッケージ基板を作製した。このとき接着剤8が流動するが、キャビティ材7上の貫通孔A24の周囲には、アニュラリングが設けられていないため、接着剤8の貫通孔A24内側への流動が実施例に比べて大きかった。貫通孔A24の内壁から接続パッド11上へのしみ出し量(しみ出した距離)は、本比較例では、片側で80μm以上のレベルであった。また、貫通孔A24の周囲には、内層回路19を設けていない。このため、貫通孔A24の周囲近傍の接着剤8の厚みは、流動によってそれ以外の部分より薄くはなるものの、内層回路19に対応する部分よりも厚く形成されている。この比較例1では、貫通孔A24の周囲において、キャビティ材7とベース層6の感光性樹脂10との間に挟まれる部分の接着剤の厚みは、10μm以上であった。
[キャビティ層の作製]
実施例1と同様にしてキャビティ層5を作成した。
実施例1と同様にしてベース層6を作製した。
層間接続31を形成する際に、有底ビア13内にスルーホールめっきのみを行い、導電樹脂17を充填しなかった。また、このため、有底ビア13の直上ではない位置に接続端子A14を形成したこと以外は、実施例1と同様である。
有底ビア13近傍の断面を、光学顕微鏡で観察して行った。
貫通孔A24内への接着剤8のしみ出し量は、貫通孔A24の内壁から接続パッド11上へのしみ出し量(しみ出した距離)として観察することができる。このため、キャビティ層5とベース層6とを積層した後、貫通孔A24の入り口側から、貫通孔A24の底部を光学顕微鏡で観察して測定した。
各実施例及び比較例で作製した導体素子搭載用パッケージ基板1を使用して、−55〜125℃の冷熱サイクル試験(それぞれ15分)を行い、100サイクルごとに有底ビア13の層間接続31を通した接続抵抗を測定し、1000サイクル後の接続不良の有無を確認した。接続抵抗が、初期値に比べて10%以上増加したものを不合格(×)とした。
Claims (7)
- キャビティ材と接着剤とを備え、これらを貫通する開口及び貫通孔を有するキャビティ層と、前記接着剤によって前記キャビティ層に積層されたベース層と、前記開口によって形成されたキャビティ部と、前記貫通孔によって形成された有底ビアと、を有する半導体素子搭載用パッケージ基板において、
前記キャビティ層に内層回路が設けられ、
この内層回路と接合するように、前記有底ビアの内壁に金属被覆がめっきにより形成され、
前記有底ビアに導電樹脂が充填される半導体素子搭載用パッケージ基板。 - 請求項1において、
有底ビアが、キャビティ材と接着剤とを貫通して、ベース層上のキャビティ層側に設けられる接続パッドに到るように設けられ、
前記接続パッドと、前記キャビティ層上のベース層と反対側に設けられる接続端子Aとを接続する層間接続が形成される半導体素子搭載用パッケージ基板。 - 請求項1または2において、
キャビティ層に設けられる内層回路が貫通孔の周囲に設けられるアニュラリングであり、
このアニュラリングと有底ビアの内壁に形成される金属被覆とが内層接続を形成する半導体素子搭載用パッケージ基板。 - 請求項1から3の何れかにおいて、
キャビティ層に設けられる内層回路が、前記キャビティ材上の接着剤側に設けられる半導体素子搭載用パッケージ基板。 - 請求項1から4の何れかにおいて、
キャビティ層に設けられる接着剤の厚みが、内層回路に対応する部分で、内層回路に対応しない部分に比べて薄い半導体素子搭載用パッケージ基板。 - 請求項1から5の何れかにおいて、
キャビティ層とベース層とを積層するための接着剤がエラストマー材である半導体素子搭載用パッケージ基板。 - 開口と貫通孔と内層回路を有するキャビティ材を形成する工程と、このキャビティ材に接着剤を介してベース層を積層し、前記開口によってキャビティ部を、前記貫通孔によって有底ビアを形成する工程と、前記有底ビアの内壁に金属被覆を形成し、この金属被覆と前記内層回路との内層接続を形成する工程と、前記金属被覆を下地として前記有底ビアに導電樹脂を充填する工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
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Cited By (3)
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JP2015015317A (ja) * | 2013-07-03 | 2015-01-22 | 日本特殊陶業株式会社 | 部品内蔵配線基板及びその製造方法 |
US9425156B2 (en) | 2013-07-29 | 2016-08-23 | Samsung Electronics Co., Ltd. | Semiconductor packages having semiconductor chips disposed in opening in shielding core plate |
US10141289B2 (en) | 2013-04-01 | 2018-11-27 | Samsung Electronics Co., Ltd. | Semiconductor packages having package-on-package structures |
Families Citing this family (9)
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TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8284561B2 (en) | 2010-08-05 | 2012-10-09 | Advanced Semiconductor Engineering, Inc. | Embedded component package structure |
CN101937855B (zh) * | 2010-08-10 | 2012-09-26 | 日月光半导体制造股份有限公司 | 元件内埋式封装结构的制作方法及其封装结构 |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
JP5659379B1 (ja) * | 2014-09-04 | 2015-01-28 | 東洋インキScホールディングス株式会社 | プリント配線板 |
KR102431587B1 (ko) * | 2015-08-12 | 2022-08-11 | 삼성전기주식회사 | 패키지 기판 및 그 제조방법 |
CN107731698B (zh) * | 2017-10-26 | 2024-03-26 | 日月光半导体(上海)有限公司 | 集成电路封装件、封装基板及其制造方法 |
KR20200051215A (ko) | 2018-11-05 | 2020-05-13 | 삼성전기주식회사 | 인쇄회로기판 및 이를 포함하는 패키지 구조물 |
KR102315052B1 (ko) | 2019-04-26 | 2021-10-20 | 에스비렘 주식회사 | 파쇄 장치 |
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- 2009-09-29 TW TW098132940A patent/TW201019439A/zh unknown
- 2009-09-29 WO PCT/JP2009/066918 patent/WO2010035866A1/ja active Application Filing
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US9425156B2 (en) | 2013-07-29 | 2016-08-23 | Samsung Electronics Co., Ltd. | Semiconductor packages having semiconductor chips disposed in opening in shielding core plate |
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KR20100130640A (ko) | 2010-12-13 |
KR101143042B1 (ko) | 2012-05-08 |
JP5370765B2 (ja) | 2013-12-18 |
TW201019439A (en) | 2010-05-16 |
WO2010035866A1 (ja) | 2010-04-01 |
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