JP2010103151A - 半導体装置の製造方法及び半導体装置の製造装置 - Google Patents
半導体装置の製造方法及び半導体装置の製造装置 Download PDFInfo
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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Abstract
【解決手段】基板に形成された低誘電率絶縁膜をエッチングするエッチング処理工程と、当該エッチング処理工程の後に基板をCO2プラズマに晒すCO2プラズマ処理工程と、CO2プラズマ処理工程の後に、低誘電率絶縁膜に紫外線を照射する紫外線処理工程とを有する半導体装置の製造方法。
【選択図】図4
Description
前記シリル化処理機構が、前記紫外線処理機構と同一のチャンバに設けられ、同一チャンバ内で紫外線処理工程とシリル化処理工程を実施できるように構成されていることを特徴とする。
Si−OH + Si−OH → Si−O−Si(シロキサン骨格)+ H2O
のみではなく、
Si−F + SiOH → Si−O−Si + SiHF
Si−F + Si−F → Si−O−Si + F2
等の縮合反応と類似の反応が並行して起き、低誘電率絶縁膜中のSi−OH成分だけでなく、Si−F成分も同時に低減して、膜中の分極を大幅に低減させることにより、低誘電率絶縁膜の特性が向上していると推測される。
Claims (12)
- 基板に形成した低誘電率絶縁膜をエッチングするエッチング処理工程と、当該エッチング処理工程の後に前記基板をCO2プラズマに晒すCO2プラズマ処理工程とを具備した半導体装置の製造方法であって、
前記CO2プラズマ処理工程の後に、前記低誘電率絶縁膜に紫外線を照射する紫外線処理工程を行うことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法であって、
前記CO2プラズマ処理工程が、前記エッチング処理工程にてエッチングマスクとして使用したフォトレジスト層を除去するためのCO2プラズマアッシング処理工程であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法であって、
前記CO2プラズマ処理工程が、前記エッチング工程にて発生した付着物を除去するためのクリーニング処理工程であることを特徴とする半導体装置の製造方法。 - 請求項1〜3いずれか1項記載の半導体装置の製造方法であって、
前記CO2プラズマ処理工程の後に、前記低誘電率絶縁膜をシリル化するシリル化処理工程を行うことを特徴とする半導体装置の製造方法。 - 基板に形成した低誘電率絶縁膜をエッチングするエッチング処理工程を行うためのエッチング処理機構と、
前記エッチング工程の後に前記基板をCO2プラズマに晒すCO2プラズマ処理工程を行うためCO2プラズマ処理機構と、
前記CO2プラズマ処理工程の後に、前記低誘電率絶縁膜に紫外線を照射する紫外線処理工程を行うための紫外線処理機構と、
前記基板を搬送するための搬送機構と
を具備したことを特徴とする半導体装置の製造装置。 - 請求項5記載の半導体装置の製造装置であって、
前記紫外線処理工程の後に、前記低誘電率絶縁膜をシリル化するシリル化処理工程を行うためのシリル化処理機構を更に具備したことを特徴とする半導体装置の製造装置。 - 請求項6記載の半導体装置の製造装置であって、
前記シリル化処理機構が、前記紫外線処理機構と同一のチャンバに設けられ、同一チャンバ内で紫外線処理工程とシリル化処理工程を実施できるように構成されていることを特徴とする半導体装置の製造装置。 - 請求項7記載の半導体装置の製造装置であって、
前記チャンバ内にシリル化剤の蒸気を供給するためのシリル化剤蒸気供給機構と、
前記シリル化剤蒸気供給機構とは独立に、前記チャンバ内に窒素ガスを供給するための窒素ガス供給機構と
を具備したことを特徴とする半導体装置の製造装置。 - 請求項5〜8いずれか1項記載の半導体装置の製造装置であって、
前記搬送機構が、真空チャンバ内に設けられ、前記基板を真空雰囲気中で搬送するよう構成されたことを特徴とする半導体装置の製造装置。 - 基板に形成した低誘電率絶縁膜の表面に所定の回路パターンを有するエッチングマスクを形成する工程と、
前記エッチングマスクを介して前記低誘電率絶縁膜をエッチングし、当該低誘電率絶縁膜に溝又は孔を形成するエッチング処理工程と、
前記エッチング処理工程の後に、前記エッチングマスクをCO2プラズマを用いて除去するCO2プラズマ処理工程と、
前記CO2プラズマ処理工程の後に、前記低誘電率絶縁膜に紫外線を照射する紫外線処理工程と、
を具備したことを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法であって、
前記紫外線処理工程の後に、前記低誘電率絶縁膜をシリル化するシリル化処理工程を行うことを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法であって、
前記シリル化処理工程の後に、前記溝又は孔内に導電性の金属を埋め込む工程を具備したことを特徴とする半導体装置の製造方法。
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JP2012204669A (ja) * | 2011-03-25 | 2012-10-22 | Tokyo Electron Ltd | 処理方法および記憶媒体 |
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KR101425332B1 (ko) | 2010-12-20 | 2014-08-01 | 노벨러스 시스템즈, 인코포레이티드 | Uv 처리를 사용하는 탄소 함유 로우-k 유전율 복구 |
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JP2018011061A (ja) * | 2012-07-02 | 2018-01-18 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | 気相化学曝露による低誘電率誘電体の損傷修復 |
JP2015079885A (ja) * | 2013-10-17 | 2015-04-23 | 東京エレクトロン株式会社 | 金属配線層形成方法、金属配線層形成装置および記憶媒体 |
US9847221B1 (en) | 2016-09-29 | 2017-12-19 | Lam Research Corporation | Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing |
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