JP2010061787A - 不揮発性強誘電体メモリの制御装置 - Google Patents
不揮発性強誘電体メモリの制御装置 Download PDFInfo
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- JP2010061787A JP2010061787A JP2009248212A JP2009248212A JP2010061787A JP 2010061787 A JP2010061787 A JP 2010061787A JP 2009248212 A JP2009248212 A JP 2009248212A JP 2009248212 A JP2009248212 A JP 2009248212A JP 2010061787 A JP2010061787 A JP 2010061787A
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- 238000005086 pumping Methods 0.000 claims abstract description 231
- 239000003990 capacitor Substances 0.000 claims description 70
- 230000004913 activation Effects 0.000 claims description 8
- 230000003213 activating effect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 13
- 230000001934 delay Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 230000004044 response Effects 0.000 description 7
- 230000007704 transition Effects 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000010287 polarization Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
Abstract
【解決手段】複数のサブデータ入/出力ピンで分けられた複数のデータ入/出力ピンにおいて、前記複数のサブデータ入/出力ピンの活性化の可否を設けるための入/出力設定制御部50、入/出力設定制御部の制御に伴い選択的に活性化されるレジスタアレイ60、レジスタアレイから印加されるデータを解析し、入/出力ピンの設定のための制御信号を出力するデータ入/出力制御部70を備え、前記レジスタアレイはポンピング電圧制御信号と、セルプレートポンピング電圧制御信号及びライトイネーブルポンピング電圧制御信号の電圧レベルに従いそれぞれの単位レジスタの出力信号をブースティングして出力する。
【選択図】図16
Description
11、21、23 … 遅延部
12、24、27 … 駆動部
20 … セルプレート電圧制御部
22 … ポンピング部
25 … レベル制御部
26 … レベルシフター部
30 …ライトイネーブル電圧制御部
40、60、100 … レジスタアレイ
41 … ポンピング電圧駆動部
42 … イコライジング部
43、47 … ライトイネーブルポンピング駆動部
44、46 … 強誘電体キャパシタ部
45 … 電圧駆動部
50 … 入/出力設定制御部
70 … データ入/出力制御部
80 … 入/出力バッファ
90 … セクター保護設定制御部
110 … メモリセクター制御部
120 … メモリアレイ領域
Claims (2)
- それぞれ複数のサブデータ入/出力ピンで分けられた複数のデータ入/出力ピンにおいて、前記複数のサブデータ入/出力ピンの活性化の可否を設けるための入/出力設定制御部、
不揮発性強誘電体キャパシタを含む複数の単位レジスタ等を備え、前記入/出力設定制御部の制御に伴い選択的に活性化されるレジスタアレイ、
前記レジスタアレイから印加されるデータを解析し、入/出力ピンの設定のための制御信号を出力するデータ入/出力制御部、及び
前記データ入/出力制御部から印加される制御信号に応じ、前記複数のサブデータ入/出力ピンの個数を選択的に活性化させる入/出力バッファ
を備えてなる不揮発性強誘電体メモリの制御装置。 - 前記レジスタアレイは、
電源制御信号の印加の際、電源電圧が低電圧領域か高電圧領域かに従いその出力レベルを異にする電源電圧制御信号を受信し、ポンピング電圧制御信号を出力するポンピング電圧制御部、
セルプレート制御信号の印加の際、前記電源電圧制御信号の状態に従いセルプレートポンピング電圧制御信号を出力するセルプレート電圧制御部、及び
ライトイネーブル制御信号の印加の際、前記電源電圧制御信号の状態に従いライトイネーブルポンピング電圧制御信号を出力するライトイネーブル電圧制御部をさらに備え、
前記ポンピング電圧制御信号、前記セルプレートポンピング電圧制御信号及び前記ライトイネーブルポンピング電圧制御信号の電圧レベルに従い、前記不揮発性強誘電体キャパシタに貯蔵されたデータの電圧をブースティングして出力する
ことを特徴とする請求項1に記載の不揮発性強誘電体メモリの制御装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0070066A KR100492800B1 (ko) | 2002-11-12 | 2002-11-12 | 불휘발성 강유전체 메모리 제어 장치 |
KR2002-070066 | 2002-11-12 |
Related Parent Applications (1)
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---|---|---|---|
JP2003183082A Division JP4570853B2 (ja) | 2002-11-12 | 2003-06-26 | 不揮発性強誘電体メモリの制御装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010061787A true JP2010061787A (ja) | 2010-03-18 |
JP5094813B2 JP5094813B2 (ja) | 2012-12-12 |
Family
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JP2003183082A Expired - Fee Related JP4570853B2 (ja) | 2002-11-12 | 2003-06-26 | 不揮発性強誘電体メモリの制御装置 |
JP2009248221A Expired - Fee Related JP5094814B2 (ja) | 2002-11-12 | 2009-10-28 | 不揮発性強誘電体メモリの制御装置 |
JP2009248212A Expired - Fee Related JP5094813B2 (ja) | 2002-11-12 | 2009-10-28 | 不揮発性強誘電体メモリの制御装置 |
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JP2003183082A Expired - Fee Related JP4570853B2 (ja) | 2002-11-12 | 2003-06-26 | 不揮発性強誘電体メモリの制御装置 |
JP2009248221A Expired - Fee Related JP5094814B2 (ja) | 2002-11-12 | 2009-10-28 | 不揮発性強誘電体メモリの制御装置 |
Country Status (3)
Country | Link |
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US (2) | US6898107B2 (ja) |
JP (3) | JP4570853B2 (ja) |
KR (1) | KR100492800B1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1303792B1 (en) * | 2000-07-16 | 2012-10-03 | Board Of Regents, The University Of Texas System | High-resolution overlay alignement methods and systems for imprint lithography |
US7050323B2 (en) * | 2002-08-29 | 2006-05-23 | Texas Instruments Incorporated | Ferroelectric memory |
JP4129453B2 (ja) * | 2004-12-01 | 2008-08-06 | 株式会社東芝 | 半導体記憶装置、半導体記憶装置の動作方法および半導体記憶装置のテスト方法 |
KR100776762B1 (ko) | 2006-08-11 | 2007-11-19 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
US8874935B2 (en) * | 2011-08-30 | 2014-10-28 | Microsoft Corporation | Sector map-based rapid data encryption policy compliance |
US10615967B2 (en) | 2014-03-20 | 2020-04-07 | Microsoft Technology Licensing, Llc | Rapid data protection for storage devices |
US9825945B2 (en) | 2014-09-09 | 2017-11-21 | Microsoft Technology Licensing, Llc | Preserving data protection with policy |
US9853812B2 (en) | 2014-09-17 | 2017-12-26 | Microsoft Technology Licensing, Llc | Secure key management for roaming protected content |
US9900295B2 (en) | 2014-11-05 | 2018-02-20 | Microsoft Technology Licensing, Llc | Roaming content wipe actions across devices |
US9853820B2 (en) | 2015-06-30 | 2017-12-26 | Microsoft Technology Licensing, Llc | Intelligent deletion of revoked data |
US9900325B2 (en) | 2015-10-09 | 2018-02-20 | Microsoft Technology Licensing, Llc | Passive encryption of organization data |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05234390A (ja) * | 1992-02-24 | 1993-09-10 | Fujitsu Ltd | 半導体集積回路装置 |
JPH08195079A (ja) * | 1995-01-11 | 1996-07-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH08273375A (ja) * | 1995-03-29 | 1996-10-18 | Ramtron Internatl Corp | 読出電圧と書込電圧とが異なる強誘電性メモリ感知方法 |
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US4873664A (en) * | 1987-02-12 | 1989-10-10 | Ramtron Corporation | Self restoring ferroelectric memory |
JP3672954B2 (ja) * | 1994-12-26 | 2005-07-20 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JP2720812B2 (ja) * | 1995-03-17 | 1998-03-04 | 日本電気株式会社 | 半導体記憶装置 |
US5592410A (en) | 1995-04-10 | 1997-01-07 | Ramtron International Corporation | Circuit and method for reducing a compensation of a ferroelectric capacitor by multiple pulsing of the plate line following a write operation |
US5818430A (en) * | 1997-01-24 | 1998-10-06 | C.A.M. Graphics Co., Inc. | Touch screen |
US6101155A (en) * | 1997-08-14 | 2000-08-08 | Seagate Technology, Inc. | Lens for optical data storage system |
US5917746A (en) | 1997-08-27 | 1999-06-29 | Micron Technology, Inc. | Cell plate structure for a ferroelectric memory |
KR100297874B1 (ko) * | 1997-09-08 | 2001-10-24 | 윤종용 | 강유전체랜덤액세스메모리장치 |
KR100333720B1 (ko) * | 1998-06-30 | 2002-06-20 | 박종섭 | 강유전체메모리소자의리던던시회로 |
JP2000049307A (ja) | 1998-07-29 | 2000-02-18 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR100303782B1 (ko) * | 1998-10-28 | 2001-09-24 | 박종섭 | 두개의 공급전위를 사용하여 메모리소자의 셀 플레이트 라인을구동하기 위한 장치 |
JP2001250375A (ja) * | 2000-03-08 | 2001-09-14 | Toshiba Corp | 強誘電体メモリ |
US6275425B1 (en) * | 2000-11-16 | 2001-08-14 | Ramtron International Corporation | Ferroelectric voltage boost circuits |
KR100425160B1 (ko) * | 2001-05-28 | 2004-03-30 | 주식회사 하이닉스반도체 | 불휘발성 강유전체 메모리 장치의 승압전압 발생회로 및그 발생방법 |
KR100451762B1 (ko) * | 2001-11-05 | 2004-10-08 | 주식회사 하이닉스반도체 | 불휘발성 강유전체 메모리 장치 및 그 구동방법 |
KR100463599B1 (ko) * | 2001-11-17 | 2004-12-29 | 주식회사 하이닉스반도체 | 불휘발성 강유전체 메모리 장치 및 그의 구동방법 |
KR100482996B1 (ko) * | 2002-08-30 | 2005-04-15 | 주식회사 하이닉스반도체 | 비휘발성 강유전체 메모리 장치 |
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2002
- 2002-11-12 KR KR10-2002-0070066A patent/KR100492800B1/ko not_active IP Right Cessation
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2003
- 2003-06-26 JP JP2003183082A patent/JP4570853B2/ja not_active Expired - Fee Related
- 2003-06-30 US US10/608,427 patent/US6898107B2/en not_active Expired - Lifetime
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2005
- 2005-04-13 US US11/104,579 patent/US7054182B2/en not_active Expired - Fee Related
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2009
- 2009-10-28 JP JP2009248221A patent/JP5094814B2/ja not_active Expired - Fee Related
- 2009-10-28 JP JP2009248212A patent/JP5094813B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05234390A (ja) * | 1992-02-24 | 1993-09-10 | Fujitsu Ltd | 半導体集積回路装置 |
JPH08195079A (ja) * | 1995-01-11 | 1996-07-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH08273375A (ja) * | 1995-03-29 | 1996-10-18 | Ramtron Internatl Corp | 読出電圧と書込電圧とが異なる強誘電性メモリ感知方法 |
Also Published As
Publication number | Publication date |
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US7054182B2 (en) | 2006-05-30 |
US20040090811A1 (en) | 2004-05-13 |
JP2005108267A (ja) | 2005-04-21 |
KR100492800B1 (ko) | 2005-06-07 |
JP5094813B2 (ja) | 2012-12-12 |
US20050201138A1 (en) | 2005-09-15 |
KR20040041955A (ko) | 2004-05-20 |
US6898107B2 (en) | 2005-05-24 |
JP2010061788A (ja) | 2010-03-18 |
JP4570853B2 (ja) | 2010-10-27 |
JP5094814B2 (ja) | 2012-12-12 |
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