JP2010056213A - 半導体装置の実装方法 - Google Patents
半導体装置の実装方法 Download PDFInfo
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- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/93—Batch processes
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
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Abstract
【解決手段】半導体装置1を実装部材2に実装する際に、実装部材2に接着材料3を配置し、接着材料3が配置された実装部材2の上方に支持材8に備えられた半導体装置1を配置する。そして、実装部材2の下方から実装部材2のうち接着材料3が配置されている部分を治具9により押し上げて接着材料3を半導体装置1に接触させる。その後、治具9を降下させることにより、半導体装置1を支持材8から分離して実装部材2に実装する。このような半導体装置1の実装方法によれば、支持材8に接着されている半導体装置1を実装部材2に直接実装することができるので、半導体装置1が割れたりすることや半導体装置1の一部が欠けたりすることを防止することができる。
【選択図】図2
Description
本発明の第1実施形態について説明する。図1は本実施形態の半導体装置の実装方法を適用して実装部材に実装された半導体装置の断面構成を示す図であり、この図に基づいて説明する。
上記第1実施形態では、導電性材料3として銀ペーストを例に挙げて説明したが、もちろん他の材料を用いることもできる。例えば、導電性材料3として熱硬化性材料を有する熱硬化性はんだを用いてもよい。導電性材料3として熱硬化性はんだを用いた場合には、治具9に治具9を加熱することのできる部材を備え、半導体装置1と導電性材料3とを接触させた状態で導電性材料3を加熱することができるようにし、治具9を加熱することにより導電性材料3を硬化させて、支持材8の接着力が導電性材料3の接着力より弱くなるようにしてもよい。
2 実装部材
3 導電性材料
4 半導体基板
5 第1電極
6 表面保護膜
7 第2電極
8 支持材
Claims (6)
- 複数の半導体素子が形成された半導体基板(4)を用意する工程と、
前記半導体基板(4)の表面に複数の前記半導体素子とそれぞれ電気的に接続される第1導体(5)を形成する工程と、
前記半導体基板(4)の表面に支持材(8)を配置し、前記支持材(8)に前記半導体基板(4)を接着する工程と、
前記半導体基板(4)を前記支持材(8)で支持しながら裏面から研削する工程と、
前記半導体基板(4)を前記半導体基板(4)の裏面から分割してチップ単位に分割された半導体装置(1)を形成する工程と、
前記半導体装置(1)を前記支持材(8)から分離して実装部材(2)に接着材料(3)を介して実装する工程と、を有する半導体装置の実装方法であって、
前記半導体装置(1)を前記実装部材(2)に実装する工程は、前記実装部材(2)に前記接着材料(3)を配置し、前記接着材料(3)が配置された前記実装部材(2)の上方に前記支持材(8)に備えられた前記半導体装置(1)を配置した後、前記実装部材(2)の下方から前記実装部材(2)のうち前記接着材料(3)が配置されている部分を治具(9)により押し上げて前記接着材料(3)を前記半導体装置(1)に接触させる工程と、前記治具(9)を降下させることにより、前記半導体装置(1)を前記支持材(8)から分離して前記実装部材(2)に実装する工程と、を含むことを特徴とする半導体装置の実装方法。 - 前記半導体装置(1)を前記実装部材(2)に実装する工程では、前記半導体装置(1)を形成する工程を行った後、前記支持材(8)の接着力を弱める工程を行い、少なくとも前記半導体装置(1)と前記接着材料(3)とが接触している状態において前記支持材(8)の弱められた接着力が前記接着材料(3)の接着力より弱くなるようにすることを特徴とする請求項1に記載の半導体装置の実装方法。
- 前記半導体装置(1)を実装する工程では、前記治具(9)のうち前記実装部材(2)を押し上げる部分の面積が前記半導体装置(1)の裏面の面積より大きい治具(9)を用いて行うことを特徴とする請求項1または2に記載の半導体装置の実装方法。
- 前記半導体装置(1)を実装する工程では、前記接着材料(3)として熱可塑性樹脂を用い、前記半導体装置(1)と前記接着材料(3)とが接触している状態で前記治具(9)を加熱することにより前記接着材料(3)を熱硬化させて前記半導体装置(1)を前記実装部材(2)に実装することを特徴とする請求項1ないし3のいずれか1つに記載の半導体装置の実装方法。
- 前記支持材(8)に前記半導体基板(4)を接着する工程を行った後、前記半導体装置(1)を形成する工程の前に、前記半導体基板(4)の裏面に複数の前記半導体素子とそれぞれ電気的に接続される第2導体(7)を形成する工程を行い、
前記半導体装置(1)を前記実装部材(2)に実装する工程では、前記接着材料(3)として導電性材料を有して構成した材料を用いることを特徴とする請求項1ないし4のいずれか1つに記載の半導体装置の実装方法。 - 前記支持材(8)を紫外線硬化性樹脂を有する材料で構成し、前記支持材(8)に紫外線を照射することにより前記支持材(8)の接着力を弱めることを特徴とする請求項1ないし5のいずれか1つに記載の半導体装置の実装方法。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04367250A (ja) * | 1991-06-14 | 1992-12-18 | Sharp Corp | 半導体チップの製造方法 |
JPH0730209A (ja) * | 1993-07-14 | 1995-01-31 | Matsushita Electric Ind Co Ltd | 光素子実装体の製造方法 |
JPH11330143A (ja) * | 1998-05-13 | 1999-11-30 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002009108A (ja) * | 2000-06-23 | 2002-01-11 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2003324112A (ja) * | 2002-04-30 | 2003-11-14 | Lintec Corp | 半導体装置の製造方法 |
JP2004014913A (ja) * | 2002-06-10 | 2004-01-15 | Seiko Epson Corp | 半導体集積回路、信号伝送装置、電気光学装置および電子機器 |
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2008
- 2008-08-27 JP JP2008218097A patent/JP5187075B2/ja not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04367250A (ja) * | 1991-06-14 | 1992-12-18 | Sharp Corp | 半導体チップの製造方法 |
JPH0730209A (ja) * | 1993-07-14 | 1995-01-31 | Matsushita Electric Ind Co Ltd | 光素子実装体の製造方法 |
JPH11330143A (ja) * | 1998-05-13 | 1999-11-30 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002009108A (ja) * | 2000-06-23 | 2002-01-11 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2003324112A (ja) * | 2002-04-30 | 2003-11-14 | Lintec Corp | 半導体装置の製造方法 |
JP2004014913A (ja) * | 2002-06-10 | 2004-01-15 | Seiko Epson Corp | 半導体集積回路、信号伝送装置、電気光学装置および電子機器 |
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