JP2010021286A - Bgaパッケージ - Google Patents
Bgaパッケージ Download PDFInfo
- Publication number
- JP2010021286A JP2010021286A JP2008179416A JP2008179416A JP2010021286A JP 2010021286 A JP2010021286 A JP 2010021286A JP 2008179416 A JP2008179416 A JP 2008179416A JP 2008179416 A JP2008179416 A JP 2008179416A JP 2010021286 A JP2010021286 A JP 2010021286A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- terminal
- package
- bga package
- terminal pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 32
- 229910000679 solder Inorganic materials 0.000 claims abstract description 20
- 238000005476 soldering Methods 0.000 claims abstract description 5
- 238000003466 welding Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 230000002787 reinforcement Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/0465—Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
【解決手段】 LSIパッケージ1と、LSIパッケージ1の裏面にグリッド状に配置された複数の端子パッド2と、端子パッド2を介して、LSIパッケージ1を電装基板にハンダ付けするためのハンダボールとを有し、LSIパッケージ1の最外周の4角に複数配置される端子パッド群を、他の端子パッドのサイズよりも大きくした一体型の補強用パッド6として構成したBGAパッケージ
【選択図】 図4
Description
LSIパッケージと、
LSIパッケージの裏面にグリッド状に配置された複数の第1の端子パッドと、
第1の端子パッドを介して、LSIパッケージを電装基板にハンダ付けするためのハンダボールとを有し、
LSIパッケージの最外周の4角に複数配置される第1の端子パッド群を、他の第1の端子パッドのサイズよりも大きくした一体型の第1の補強用パッドとして構成したことを特徴とする。
前記第1の補強用パッドはL型パターンとして一体的に構成されている。
この第2の端子パッドは前記第1の端子パッドと前記ハンダボールを介して接続されている。
2 端子パッド
3 ハンダボール
4 電装基板
5 端子パッド
6 補強用パッド
7 ハンダボール
8 改善補強用パッド
Claims (7)
- LSIパッケージと、
LSIパッケージの裏面にグリッド状に配置された複数の第1の端子パッドと、
第1の端子パッドを介して、LSIパッケージを電装基板にハンダ付けするためのハンダボールとを有し、
LSIパッケージの最外周の4角に複数配置される第1の端子パッド群を、他の第1の端子パッドのサイズよりも大きくした一体型の第1の補強用パッドとして構成したことを特徴とするBGAパッケージ。 - 前記LSIパッケージの最外周の4角には、前記第1の端子パッドがそれぞれ少なくとも3つ配置されており、
前記第1の補強用パッドはL型パターンとして一体的に構成されていることを特徴とする請求項1に記載のBGAパッケージ。 - 前記電装基板の上面には、グリッド状に複数の第2の端子パッドが配置されており、
この第2の端子パッドは前記第1の端子パッドと前記ハンダボールを介して接続されていることを特徴とする請求項1又は2に記載のBGAパッケージ。 - 前記電装基板の最外周の4角に複数配置される第2の端子パッド群を、他の第2の端子パッドのサイズよりも大きくした一体型の第2の補強用パッドとして構成したことを特徴とする請求項1から3のいずれか1項に記載のBGAパッケージ。
- 前記第1の補強用パッドと前記第2の補強用パッドとは、前記ハンダボールよりもサイズの大きなハンダボールを介して接続されることを特徴とする請求項1から4のいずれか1項に記載のBGAパッケージ。
- 前記第1の補強用パッドと前記第2の補強用パッドとは、前記ハンダボールよりもサイズの大きなハンダボールを介して熱溶着により接続されることを特徴とする請求項5に記載のBGAパッケージ。
- 前記第2の補強用パッドはGNDに接続されることを特徴とする請求項4から6のいずれか1項に記載のBGAパッケージ。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008179416A JP5213034B2 (ja) | 2008-07-09 | 2008-07-09 | Bgaパッケージ |
US12/498,137 US20100007008A1 (en) | 2008-07-09 | 2009-07-06 | Bga package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008179416A JP5213034B2 (ja) | 2008-07-09 | 2008-07-09 | Bgaパッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010021286A true JP2010021286A (ja) | 2010-01-28 |
JP5213034B2 JP5213034B2 (ja) | 2013-06-19 |
Family
ID=41504425
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008179416A Expired - Fee Related JP5213034B2 (ja) | 2008-07-09 | 2008-07-09 | Bgaパッケージ |
Country Status (2)
Country | Link |
---|---|
US (1) | US20100007008A1 (ja) |
JP (1) | JP5213034B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8766453B2 (en) | 2012-10-25 | 2014-07-01 | Freescale Semiconductor, Inc. | Packaged integrated circuit having large solder pads and method for forming |
US10313146B2 (en) * | 2013-05-13 | 2019-06-04 | Panasonic Intellectual Property Management Co., Ltd. | Communication method and communication apparatus |
JP6436738B2 (ja) * | 2014-11-19 | 2018-12-12 | キヤノン株式会社 | プリント配線板、半導体装置及びプリント回路板 |
US20170269988A1 (en) * | 2016-03-21 | 2017-09-21 | Intel Corporation | Determining problem solutions based on system state data |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002329812A (ja) * | 2001-04-26 | 2002-11-15 | Sharp Corp | 半導体パッケージ装置および半導体パッケージ装置実装用基板 |
JP2007294620A (ja) * | 2006-04-24 | 2007-11-08 | Denso Corp | 半導体装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6444563B1 (en) * | 1999-02-22 | 2002-09-03 | Motorlla, Inc. | Method and apparatus for extending fatigue life of solder joints in a semiconductor device |
JP2007165420A (ja) * | 2005-12-12 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US7646105B2 (en) * | 2007-11-16 | 2010-01-12 | Stats Chippac Ltd. | Integrated circuit package system with package substrate having corner contacts |
-
2008
- 2008-07-09 JP JP2008179416A patent/JP5213034B2/ja not_active Expired - Fee Related
-
2009
- 2009-07-06 US US12/498,137 patent/US20100007008A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002329812A (ja) * | 2001-04-26 | 2002-11-15 | Sharp Corp | 半導体パッケージ装置および半導体パッケージ装置実装用基板 |
JP2007294620A (ja) * | 2006-04-24 | 2007-11-08 | Denso Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20100007008A1 (en) | 2010-01-14 |
JP5213034B2 (ja) | 2013-06-19 |
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