JP2009528678A - 接点作成方法 - Google Patents
接点作成方法 Download PDFInfo
- Publication number
- JP2009528678A JP2009528678A JP2008556414A JP2008556414A JP2009528678A JP 2009528678 A JP2009528678 A JP 2009528678A JP 2008556414 A JP2008556414 A JP 2008556414A JP 2008556414 A JP2008556414 A JP 2008556414A JP 2009528678 A JP2009528678 A JP 2009528678A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- contacts
- cap
- conductive material
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 129
- 239000004020 conductor Substances 0.000 claims abstract description 55
- 125000006850 spacer group Chemical group 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 239000002648 laminated material Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000011810 insulating material Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 22
- 238000011049 filling Methods 0.000 claims description 20
- 230000015654 memory Effects 0.000 claims description 15
- 239000000945 filler Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- -1 Tungsten nitride Chemical class 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000003491 array Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 53
- 230000008569 process Effects 0.000 description 15
- 238000005530 etching Methods 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000002829 reductive effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 102100026827 Protein associated with UVRAG as autophagy enhancer Human genes 0.000 description 1
- 101710102978 Protein associated with UVRAG as autophagy enhancer Proteins 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 208000003580 polydactyly Diseases 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Electrical Connectors (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【選択図】図1
Description
含まれる。
116, 118, 120を形成した高さの下に、部品を形成してもよい。
ることなく、接点を形成できる。するとキャップの厚さを低減できる。例えば、いくつかの実施形態においては、キャップの厚さを約700Åにできる。こうするととりわけ以下のような利点がある。すなわち、ゲート構造体もしくは接点構造体のパターン化が簡単になること。部品の鉛直方向の大きさを縮められること。接点形成にかかる時間を減らせること。使用材料量を減らせること、である。
相互接続部、開口部、および溝を導電性材料で満たしてもよい。いくつかの実施形態においては、こうしたプラグ、相互接続部、開口部、および溝の充填を同時に行うことができる。
かの実施形態においては、キャップを平坦化してもよい。また、この工程中に、絶縁材料および/もしくは充填材料を浸蝕してもよい。
を持つ。
段 1292 によって制御される。
Claims (34)
- 接点を作成する方法であって、
絶縁積層材料に溝を、前記溝の一部が複数のゲートのうちの二つの間に位置するようにして、作成するステップと、
スペーサー材料を、前記溝の少なくともひとつ以上の側面に堆積するステップと、
導電性材料を前記溝内に堆積するステップと、
キャップ材料を前記溝内に堆積するステップと
を含む 、方法。 - 上塗材料を、前記溝および前記スペーサー材料に堆積するステップ
を含む、請求項1記載の方法。 - 約700オングストロームの高さであるキャップを各々が有する複数のゲートを作成するステップ
を含む、請求項1記載の方法。 - 700オングストローム以下の高さであるキャップを各々が有する複数のゲートを作成するステップ
を含む、請求項1記載の方法。 - 1500オングストローム以下の高さであるキャップを各々が有する複数のゲートを作成するステップ
を含む、請求項1記載の方法。 - 前記第一の溝を作成することになる絶縁積層材料を前記複数のゲートの上に堆積することに先立って、窒化珪素層を前記複数のゲートに被せて 堆積するステップ
を含む、請求項1記載の方法。 - 前記絶縁積層材料内に溝を作成することに先立って、前記絶縁積層材料から絶縁積層を作成するステップ
を含み、ここで、
前記層の厚さは、前記層の上面から、1800オングストロームである少なくともひとつのゲートの上面に至るまでである
ことを特徴とする、請求項1記載の方法。 - 導電性材料を前記溝に堆積する前記ステップ中に、複数の開口接点を、前記導電性材料で充填するステップ
を含む、請求項1記載の方法。 - 導電性材料を前記溝に堆積するステップが、
以下の
チタン、
窒化チタン、
窒化タングステン、
タングステン、
上述した物質のうちの二種以上の組み合わせ、
を含んだ群から選択される材料を堆積するステップ
を含む、請求項1記載の方法。 - 絶縁性材料を、各々がゲートキャップを有する複数のゲートに被せるように塗布して、絶縁積層を作成するステップと、
前記複数のゲートのうちの二つの間に第一の接点開口部を作成するステップと、
前記第一の接点開口部を、充填材料で充填するステップと、
前記充填材料内に、ひとつ以上の 側面を有する溝を形成するステップと、
前記ひとつ以上の側面を、スペーサー材料で蔽うステップと、
前記溝を、導電性材料で充填するステップと、
前記導電性材料内に凹部を形成するステップと、
前記凹部をキャップ材料で充填するステップと
を含む、方法。 - 上塗材料を、前記溝および前記スペーサー材料に塗布するステップ
を含む、請求項10記載の方法。 - 前記第一の接点開口部を充填材料で充填する前に、二重マスクかけ法を使って複数の接点を接点アレイとしてパターン化するステップ
を含む、請求項10記載の方法。 - 二重マスクかけ法を使って複数の接点を接点アレイとしてパターン化するステップが、
前記複数の接点を1500オングストローム以上の深さにパターン化するステップ
を含む、請求項12記載の方法。 - 二重マスクかけ法を使って複数の接点を接点アレイとしてパターン化するステップが、
接点乾式蝕刻法を使って前記複数の接点をパターン化するステップ
を含む、請求項13記載の方法。 - 前記溝を形成するステップが、
前記溝を約1500オングストロームの深さにパターン化するステップ
を含む、請求項10記載の方法。 - 前記ひとつ以上の側面をスペーサー材料で蔽うステップが、
スペーサー誘電材料を塗布して、前記溝の側壁を上塗りするステップ
を含む、請求項10記載の方法。 - 前記ひとつ以上の側面をスペーサー材料で蔽うステップが、
材料を厚さ約250オングストロームで塗布するステップ
を含む、請求項10記載の方法。 - 前記溝を導電性材料で充填する間に、複数の周縁接点開口部および複数の相互接続部を、導電性材料で充填するステップ
を含む、請求項10記載の方法。 - 絶縁材料内につくられた少なくともひとつの側壁を有する、溝構造 と、
前記少なくともひとつの側壁に付けるように配置された、スペーサー材料と、
前記溝構造内部に配置された、導電性材料と、
前記導電性材料に被せて配置された、キャップ材料と
を含む、半導体構造物。 - 前記溝構造が、象嵌溝構造である、請求項19記載の半導体構造物。
- 前記溝構造を、複数のデジット接点を跨ぎ且つ複数のセル接点には被さらないような経路に沿わせて形成する、請求項19記載の半導体構造物。
- 前記溝構造が、デジット接点の上だけにつくられる、請求項21記載の半導体構造物。
- 複数のセル接点および複数のデジット接点を有する 半導体基板と、
前記複数のデジット接点の上に配置され、且つ絶縁材料内につくられた少なくともひとつの側壁を有する、溝構造と、
前記少なくともひとつの側壁に付けるように配置された、スペーサー材料と、
前記溝構造内部に配置された、導電性材料と、
前記導電性材料に被せて配置された、キャップ材料と
を含む、集積回路。 - 前記導電性材料が、前記複数のデジット接点のうちのいくつかの上につくられた接点開口部の中に配置される、請求項23記載の集積回路。
- 前記キャップ材料が、前記複数のデジット接点のうちの前記いくつかに亙る前記接点開口部の中に配置される、請求項24記載の集積回路。
- 複数の接点を有する半導体基板と、
前記複数の接点の上に配置され、且つ絶縁材料内につくられた少なくともひとつの側壁を有する、溝構造と、
前記少なくともひとつの側壁に付けるように配置された、スペーサー材料と、
前記溝構造内部に配置された、導電性材料と、
前記導電性材料に被せて配置された、キャップ材料と
を含む、メモリ装置。 - 前記キャップ材料が、誘電性材料を含む、請求項26記載のメモリ装置。
- 前記キャップ材料が、窒化珪素材料である、請求項27記載のメモリ装置。
- 前記スペーサー材料が、オルト珪酸テトラエチルを含む、請求項26記載のメモリ装置。
- 前記充填材料が、犠牲材料を含む、請求項26記載のメモリ装置。
- 前記充填材料が、ポリシリコン材料を含むことを特徴とする、請求項26記載のメモリ装置。
- 制御手段と、
前記制御手段に接続し、且つ複数のメモリセルアレイ を有する、メモリ装置と
を含んだ電子システムであって、
前記複数のメモリセルが、
複数の接点を含んだ半導体基板と、
前記複数の接点のうちの一個以上をかたちづくり、且つ絶縁材料につくられたひとつ以上の側壁を有する、接点構造体と、
前記ひとつ以上の側壁に付くように配置された、スペーサー材料と、
前記接点構造体内部に配置された、導電性材料と、
前記導電性材料に被せて配置された、キャップ材料と
を有する
ことを特徴とする、電子システム。 - 前記メモリが、ダイナミックランダムアクセスメモリ装置である、請求項32記載の電子システム。
- 前記制御手段がプロセッサである、請求項32記載の電子システム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/363,661 | 2006-02-27 | ||
US11/363,661 US20070202677A1 (en) | 2006-02-27 | 2006-02-27 | Contact formation |
PCT/US2007/004573 WO2007098236A2 (en) | 2006-02-27 | 2007-02-20 | Contact formation |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009528678A true JP2009528678A (ja) | 2009-08-06 |
JP2009528678A5 JP2009528678A5 (ja) | 2010-04-15 |
JP5403398B2 JP5403398B2 (ja) | 2014-01-29 |
Family
ID=38284019
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008556414A Active JP5403398B2 (ja) | 2006-02-27 | 2007-02-20 | コンタクト形成方法 |
Country Status (8)
Country | Link |
---|---|
US (4) | US20070202677A1 (ja) |
EP (2) | EP1989734A2 (ja) |
JP (1) | JP5403398B2 (ja) |
KR (1) | KR101082288B1 (ja) |
CN (1) | CN101390208B (ja) |
SG (1) | SG183588A1 (ja) |
TW (1) | TWI343093B (ja) |
WO (1) | WO2007098236A2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070202677A1 (en) * | 2006-02-27 | 2007-08-30 | Micron Technology, Inc. | Contact formation |
JP5403862B2 (ja) * | 2006-11-28 | 2014-01-29 | チェイル インダストリーズ インコーポレイテッド | 微細金属パターンの製造方法 |
JP2009176819A (ja) * | 2008-01-22 | 2009-08-06 | Elpida Memory Inc | 半導体装置及びその製造方法 |
TWI419033B (zh) * | 2009-03-05 | 2013-12-11 | Elan Microelectronics Corp | Method for manufacturing two - layer circuit board structure for capacitive touch panel |
US8241944B2 (en) | 2010-07-02 | 2012-08-14 | Micron Technology, Inc. | Resistive RAM devices and methods |
US20160086956A1 (en) * | 2013-04-30 | 2016-03-24 | Ps5 Luxco S.A.R.L. | Semiconductor device and method for manufacturing semiconductor device |
US10998228B2 (en) * | 2014-06-12 | 2021-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned interconnect with protection layer |
TWI833245B (zh) * | 2022-04-21 | 2024-02-21 | 南亞科技股份有限公司 | 具有不同位元線接觸點之半導體元件的製備方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6066556A (en) * | 1997-12-23 | 2000-05-23 | Samsung Electronics Co., Ltd. | Methods of fabricating conductive lines in integrated circuits using insulating sidewall spacers and conductive lines so fabricated |
JP2001007039A (ja) * | 1999-06-18 | 2001-01-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2004241759A (ja) * | 2003-02-05 | 2004-08-26 | Hynix Semiconductor Inc | 半導体素子の金属配線形成方法 |
US20040173912A1 (en) * | 2003-03-04 | 2004-09-09 | Rhodes Howard E. | Damascene processes for forming conductive structures |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3146316B2 (ja) * | 1991-05-17 | 2001-03-12 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置及びその製造方法 |
US6531730B2 (en) * | 1993-08-10 | 2003-03-11 | Micron Technology, Inc. | Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same |
US5420061A (en) * | 1993-08-13 | 1995-05-30 | Micron Semiconductor, Inc. | Method for improving latchup immunity in a dual-polysilicon gate process |
JP2765478B2 (ja) * | 1994-03-30 | 1998-06-18 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JP3532325B2 (ja) * | 1995-07-21 | 2004-05-31 | 株式会社東芝 | 半導体記憶装置 |
JPH09260600A (ja) | 1996-03-19 | 1997-10-03 | Sharp Corp | 半導体メモリ素子の製造方法 |
JPH09293781A (ja) | 1996-04-26 | 1997-11-11 | Sony Corp | 半導体装置の製造方法 |
US5759892A (en) * | 1996-09-24 | 1998-06-02 | Taiwan Semiconductor Manufacturing Company Ltd | Formation of self-aligned capacitor contact module in stacked cyclindrical dram cell |
US6262450B1 (en) * | 1998-04-22 | 2001-07-17 | International Business Machines Corporation | DRAM stack capacitor with vias and conductive connection extending from above conductive lines to the substrate |
US6174767B1 (en) * | 1998-05-11 | 2001-01-16 | Vanguard International Semiconductor Corporation | Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise |
TW468276B (en) | 1998-06-17 | 2001-12-11 | United Microelectronics Corp | Self-aligned method for forming capacitor |
US6255168B1 (en) | 1999-09-13 | 2001-07-03 | United Microelectronics Corp. | Method for manufacturing bit line and bit line contact |
US6504210B1 (en) * | 2000-06-23 | 2003-01-07 | International Business Machines Corporation | Fully encapsulated damascene gates for Gigabit DRAMs |
US6376353B1 (en) * | 2000-07-03 | 2002-04-23 | Chartered Semiconductor Manufacturing Ltd. | Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects |
JP2003100769A (ja) * | 2001-09-20 | 2003-04-04 | Nec Corp | 半導体装置およびその製造方法 |
TW518719B (en) * | 2001-10-26 | 2003-01-21 | Promos Technologies Inc | Manufacturing method of contact plug |
KR100481173B1 (ko) * | 2002-07-12 | 2005-04-07 | 삼성전자주식회사 | 다마신 비트라인공정을 이용한 반도체 메모리장치 및 그의제조방법 |
US6696339B1 (en) * | 2002-08-21 | 2004-02-24 | Micron Technology, Inc. | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices |
KR100481177B1 (ko) * | 2002-08-21 | 2005-04-07 | 삼성전자주식회사 | 셀 패드 콘택의 저항을 감소시킨 반도체 장치 및 그제조방법 |
US7138719B2 (en) * | 2002-08-29 | 2006-11-21 | Micron Technology, Inc. | Trench interconnect structure and formation method |
US6730959B1 (en) * | 2002-10-30 | 2004-05-04 | Powerchip Semiconductor Corp. | Structure of flash memory device and fabrication method thereof |
KR100468784B1 (ko) * | 2003-02-14 | 2005-01-29 | 삼성전자주식회사 | 콘택으로부터 형성된 하드 마스크를 사용하는 다마신과정으로 배선을 형성하는 방법 |
US6921692B2 (en) * | 2003-07-07 | 2005-07-26 | Micron Technology, Inc. | Methods of forming memory circuitry |
US7217647B2 (en) * | 2004-11-04 | 2007-05-15 | International Business Machines Corporation | Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern |
US20060148168A1 (en) * | 2005-01-06 | 2006-07-06 | Sheng-Chin Li | Process for fabricating dynamic random access memory |
US8125018B2 (en) * | 2005-01-12 | 2012-02-28 | Spansion Llc | Memory device having trapezoidal bitlines and method of fabricating same |
US7723229B2 (en) * | 2005-04-22 | 2010-05-25 | Macronix International Co., Ltd. | Process of forming a self-aligned contact in a semiconductor device |
US7214621B2 (en) * | 2005-05-18 | 2007-05-08 | Micron Technology, Inc. | Methods of forming devices associated with semiconductor constructions |
US20070048951A1 (en) * | 2005-08-31 | 2007-03-01 | Hocine Boubekeur | Method for production of semiconductor memory devices |
US20070202677A1 (en) * | 2006-02-27 | 2007-08-30 | Micron Technology, Inc. | Contact formation |
-
2006
- 2006-02-27 US US11/363,661 patent/US20070202677A1/en not_active Abandoned
-
2007
- 2007-02-20 JP JP2008556414A patent/JP5403398B2/ja active Active
- 2007-02-20 SG SG2011012978A patent/SG183588A1/en unknown
- 2007-02-20 EP EP07751342A patent/EP1989734A2/en not_active Withdrawn
- 2007-02-20 WO PCT/US2007/004573 patent/WO2007098236A2/en active Application Filing
- 2007-02-20 KR KR1020087023686A patent/KR101082288B1/ko active IP Right Grant
- 2007-02-20 EP EP20100001798 patent/EP2194573A3/en not_active Withdrawn
- 2007-02-20 CN CN2007800068498A patent/CN101390208B/zh active Active
- 2007-02-26 TW TW096106457A patent/TWI343093B/zh active
-
2009
- 2009-03-11 US US12/401,996 patent/US7737022B2/en active Active
-
2010
- 2010-05-26 US US12/787,684 patent/US8034706B2/en active Active
-
2011
- 2011-09-20 US US13/237,126 patent/US8377819B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6066556A (en) * | 1997-12-23 | 2000-05-23 | Samsung Electronics Co., Ltd. | Methods of fabricating conductive lines in integrated circuits using insulating sidewall spacers and conductive lines so fabricated |
JP2001007039A (ja) * | 1999-06-18 | 2001-01-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2004241759A (ja) * | 2003-02-05 | 2004-08-26 | Hynix Semiconductor Inc | 半導体素子の金属配線形成方法 |
US20040173912A1 (en) * | 2003-03-04 | 2004-09-09 | Rhodes Howard E. | Damascene processes for forming conductive structures |
Also Published As
Publication number | Publication date |
---|---|
CN101390208B (zh) | 2012-06-13 |
EP2194573A2 (en) | 2010-06-09 |
US20090176365A1 (en) | 2009-07-09 |
WO2007098236A2 (en) | 2007-08-30 |
US7737022B2 (en) | 2010-06-15 |
US8377819B2 (en) | 2013-02-19 |
EP1989734A2 (en) | 2008-11-12 |
JP5403398B2 (ja) | 2014-01-29 |
KR20090003276A (ko) | 2009-01-09 |
US20070202677A1 (en) | 2007-08-30 |
TWI343093B (en) | 2011-06-01 |
WO2007098236A3 (en) | 2007-11-22 |
CN101390208A (zh) | 2009-03-18 |
KR101082288B1 (ko) | 2011-11-09 |
US20100233875A1 (en) | 2010-09-16 |
TW200739812A (en) | 2007-10-16 |
US8034706B2 (en) | 2011-10-11 |
EP2194573A3 (en) | 2013-05-01 |
US20120009779A1 (en) | 2012-01-12 |
SG183588A1 (en) | 2012-09-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5403398B2 (ja) | コンタクト形成方法 | |
US8378405B2 (en) | Integrated DRAM process/structure using contact pillars | |
JP3577197B2 (ja) | 半導体装置の製造方法 | |
US8691680B2 (en) | Method for fabricating memory device with buried digit lines and buried word lines | |
JP2009528678A5 (ja) | ||
CN111584489B (zh) | 半导体存储器件与其制作方法 | |
US20040173831A1 (en) | Semiconductor memory device and method for manufacturing the same | |
US20110183488A1 (en) | Semiconductor device and method of fabricating the same | |
JP2008113005A (ja) | 集積半導体構造の製造方法 | |
KR20000023287A (ko) | 불휘발성 반도체 기억 장치 및 그 제조 방법 | |
JP2000101048A (ja) | コンデンサ及びコンデンサの作製方法 | |
TWI497649B (zh) | 埋入式字元線結構及其製造方法 | |
US5930621A (en) | Methods for forming vertical electrode structures and related structures | |
TWI827385B (zh) | 積體電路(ic)裝置 | |
JP2001189434A (ja) | 半導体装置とその製造方法 | |
KR100663370B1 (ko) | 상부전극을 갖는 반도체소자 및 그 제조방법 | |
CN212570997U (zh) | 半导体存储器件 | |
US20080308902A1 (en) | Semiconductor device | |
CN100373623C (zh) | 动态随机存取存储单元和其阵列、及该阵列的制造方法 | |
JPH09246492A (ja) | 半導体記憶装置およびその製造方法 | |
KR20030002050A (ko) | 강유전체 메모리 셀구조 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20100219 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100219 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100219 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120925 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20121217 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121217 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130604 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20130826 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130826 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130924 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131017 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5403398 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |