JP2009527810A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2009527810A5 JP2009527810A5 JP2008555355A JP2008555355A JP2009527810A5 JP 2009527810 A5 JP2009527810 A5 JP 2009527810A5 JP 2008555355 A JP2008555355 A JP 2008555355A JP 2008555355 A JP2008555355 A JP 2008555355A JP 2009527810 A5 JP2009527810 A5 JP 2009527810A5
- Authority
- JP
- Japan
- Prior art keywords
- computer
- computers
- signal line
- array
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 19
- 238000004891 communication Methods 0.000 claims 13
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/355,513 US7904695B2 (en) | 2006-02-16 | 2006-02-16 | Asynchronous power saving computer |
| US11/355,495 US7904615B2 (en) | 2006-02-16 | 2006-02-16 | Asynchronous computer communication |
| PCT/US2007/004031 WO2007098007A2 (en) | 2006-02-16 | 2007-02-16 | Asynchronous computer communication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2009527810A JP2009527810A (ja) | 2009-07-30 |
| JP2009527810A5 true JP2009527810A5 (enExample) | 2010-04-08 |
Family
ID=37965009
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008555355A Pending JP2009527810A (ja) | 2006-02-16 | 2007-02-16 | 非同期コンピュータ通信 |
| JP2008555369A Pending JP2009527813A (ja) | 2006-02-16 | 2007-02-16 | 非同期電力節約コンピュータ |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008555369A Pending JP2009527813A (ja) | 2006-02-16 | 2007-02-16 | 非同期電力節約コンピュータ |
Country Status (7)
| Country | Link |
|---|---|
| EP (2) | EP1821174B9 (enExample) |
| JP (2) | JP2009527810A (enExample) |
| KR (2) | KR20090016642A (enExample) |
| AT (2) | ATE512409T1 (enExample) |
| DE (1) | DE602007007999D1 (enExample) |
| TW (2) | TW200813744A (enExample) |
| WO (2) | WO2007098007A2 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3731201B1 (en) | 2019-04-24 | 2022-11-09 | ABB Schweiz AG | A support system for an operator |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4589067A (en) * | 1983-05-27 | 1986-05-13 | Analogic Corporation | Full floating point vector processor with dynamically configurable multifunction pipelined ALU |
| JPS60204149A (ja) | 1984-03-29 | 1985-10-15 | Mitsubishi Electric Corp | デ−タ伝送装置 |
| DE3937807C2 (de) | 1988-11-19 | 1995-04-06 | Vaillant Joh Gmbh & Co | Verfahren zum Übertragen von Daten zwischen zwei sendenden und empfangenden Stationen |
| JPH03136136A (ja) * | 1989-10-23 | 1991-06-10 | Fujitsu Ltd | 命令実行時刻制御方式 |
| DE58908974D1 (de) * | 1989-11-21 | 1995-03-16 | Itt Ind Gmbh Deutsche | Datengesteuerter Arrayprozessor. |
| US5218682A (en) * | 1991-05-10 | 1993-06-08 | Chrysler Corporation | Two-way handshake circuit and method for communication between processors |
| JP2723712B2 (ja) * | 1991-08-30 | 1998-03-09 | 茨城日本電気株式会社 | マイクロプログラム制御回路 |
| US5692197A (en) * | 1995-03-31 | 1997-11-25 | Sun Microsystems, Inc. | Method and apparatus for reducing power consumption in a computer network without sacrificing performance |
| JPH0997128A (ja) * | 1995-09-26 | 1997-04-08 | Internatl Business Mach Corp <Ibm> | 情報処理システム |
| GB9704068D0 (en) * | 1997-02-27 | 1997-04-16 | Sgs Thomson Microelectronics | Trigger sequencing controller |
| FR2789501B1 (fr) | 1999-02-09 | 2001-04-13 | St Microelectronics Sa | Procede et dispositif de reduction de la consommation d'un microcontroleur |
| US6937538B2 (en) * | 2000-02-02 | 2005-08-30 | Broadcom Corporation | Asynchronously resettable decoder for a semiconductor memory |
| GB2370381B (en) | 2000-12-19 | 2003-12-24 | Picochip Designs Ltd | Processor architecture |
| JP4412905B2 (ja) * | 2003-01-28 | 2010-02-10 | パナソニック株式会社 | 低電力動作制御装置、およびプログラム最適化装置 |
| JP2004326222A (ja) * | 2003-04-22 | 2004-11-18 | Renesas Technology Corp | データ処理システム |
-
2007
- 2007-02-15 EP EP07250645A patent/EP1821174B9/en not_active Not-in-force
- 2007-02-15 AT AT07250648T patent/ATE512409T1/de not_active IP Right Cessation
- 2007-02-15 EP EP07250648A patent/EP1821217B1/en not_active Not-in-force
- 2007-02-15 DE DE602007007999T patent/DE602007007999D1/de active Active
- 2007-02-15 AT AT07250645T patent/ATE475927T1/de not_active IP Right Cessation
- 2007-02-15 TW TW096105684A patent/TW200813744A/zh unknown
- 2007-02-15 TW TW096105687A patent/TW200809530A/zh unknown
- 2007-02-16 JP JP2008555355A patent/JP2009527810A/ja active Pending
- 2007-02-16 KR KR1020077009920A patent/KR20090016642A/ko not_active Withdrawn
- 2007-02-16 WO PCT/US2007/004031 patent/WO2007098007A2/en not_active Ceased
- 2007-02-16 KR KR1020077009921A patent/KR20090016643A/ko not_active Withdrawn
- 2007-02-16 WO PCT/US2007/004080 patent/WO2007098023A2/en not_active Ceased
- 2007-02-16 JP JP2008555369A patent/JP2009527813A/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11151027B2 (en) | Methods and apparatuses for requesting ready status information from a memory | |
| US6785776B2 (en) | DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism | |
| CN103838687B (zh) | 贮存设备、包括其的计算系统及其数据传送方法 | |
| US20150026368A1 (en) | Direct memory access to storage devices | |
| US7707346B2 (en) | PCI express multi-root IOV endpoint retry buffer controller | |
| US20110153910A1 (en) | Flash Memory-Interface | |
| TW201439772A (zh) | 用於藉由使用一命令推動模型減少一資料儲存系統中之寫入延遲之方法及系統 | |
| JP2013525924A5 (enExample) | ||
| JP2013025792A5 (enExample) | ||
| TW201131368A (en) | Command queue for peripheral component | |
| WO2013129031A1 (ja) | データ転送装置、データ転送方法及びデータ転送プログラム | |
| TWI534615B (zh) | 串列周邊介面控制器、串列周邊介面快閃記憶體及其存取方法和存取控制方法 | |
| TWI570627B (zh) | 使用先進先出之介面仿真器 | |
| JPH0574111B2 (enExample) | ||
| JP2009527815A5 (enExample) | ||
| TW201344444A (zh) | 主機板及應用於該主機板的資料處理方法 | |
| JP2009527810A5 (enExample) | ||
| US20080082700A1 (en) | Interrupt processing method | |
| WO2012124431A1 (ja) | 半導体装置 | |
| CN102110066A (zh) | 一种税控加密卡的控制方法 | |
| JP2009527816A5 (enExample) | ||
| JP2006323541A (ja) | データ転送回路及びデータ転送方法 | |
| CN100511199C (zh) | 硬件加速器与数据传输方法 | |
| TW202011185A (zh) | 伺服器節電系統及其節電方法 | |
| JP5228552B2 (ja) | プロセス間通信機構 |