JP2009521113A5 - - Google Patents

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Publication number
JP2009521113A5
JP2009521113A5 JP2008546349A JP2008546349A JP2009521113A5 JP 2009521113 A5 JP2009521113 A5 JP 2009521113A5 JP 2008546349 A JP2008546349 A JP 2008546349A JP 2008546349 A JP2008546349 A JP 2008546349A JP 2009521113 A5 JP2009521113 A5 JP 2009521113A5
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JP
Japan
Prior art keywords
silicon
region
substrate
source
forming
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JP2008546349A
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English (en)
Japanese (ja)
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JP2009521113A (ja
JP4550146B2 (ja
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Priority claimed from US11/316,244 external-priority patent/US7531423B2/en
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Publication of JP2009521113A5 publication Critical patent/JP2009521113A5/ja
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JP2008546349A 2005-12-22 2006-12-05 抵抗が低減されたｆｉｎＦＥＴ及びその製造方法 Active JP4550146B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/316,244 US7531423B2 (en) 2005-12-22 2005-12-22 Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same
PCT/EP2006/069339 WO2007071555A1 (en) 2005-12-22 2006-12-05 Reduced-resistance finfets and methods of manufacturing the same

Publications (3)

Publication Number Publication Date
JP2009521113A JP2009521113A (ja) 2009-05-28
JP2009521113A5 true JP2009521113A5 (https=) 2010-04-08
JP4550146B2 JP4550146B2 (ja) 2010-09-22

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ID=37771049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008546349A Active JP4550146B2 (ja) 2005-12-22 2006-12-05 抵抗が低減されたｆｉｎＦＥＴ及びその製造方法

Country Status (8)

Country Link
US (2) US7531423B2 (https=)
EP (1) EP1964179B1 (https=)
JP (1) JP4550146B2 (https=)
KR (1) KR100992037B1 (https=)
CN (1) CN101317273B (https=)
AT (1) ATE441938T1 (https=)
DE (1) DE602006008984D1 (https=)
WO (1) WO2007071555A1 (https=)

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US20090001426A1 (en) * 2007-06-29 2009-01-01 Kangguo Cheng Integrated Fin-Local Interconnect Structure
US8063437B2 (en) * 2007-07-27 2011-11-22 Panasonic Corporation Semiconductor device and method for producing the same
US8004045B2 (en) 2007-07-27 2011-08-23 Panasonic Corporation Semiconductor device and method for producing the same
US8021939B2 (en) * 2007-12-12 2011-09-20 International Business Machines Corporation High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods
EP2311072B1 (en) * 2008-07-06 2013-09-04 Imec Method for doping semiconductor structures
US20110001169A1 (en) * 2009-07-01 2011-01-06 International Business Machines Corporation Forming uniform silicide on 3d structures
US8653608B2 (en) * 2009-10-27 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design with reduced current crowding
US8278179B2 (en) 2010-03-09 2012-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. LDD epitaxy for FinFETs
US8716798B2 (en) 2010-05-13 2014-05-06 International Business Machines Corporation Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors
US8431995B2 (en) * 2010-05-13 2013-04-30 International Business Machines Corporation Methodology for fabricating isotropically recessed drain regions of CMOS transistors
JP5837307B2 (ja) * 2011-02-07 2015-12-24 公益財団法人神奈川科学技術アカデミー 多孔性微粒子の製造方法
US8614134B2 (en) * 2011-03-21 2013-12-24 Globalfoundries Inc. Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation
US10629900B2 (en) 2011-05-04 2020-04-21 Corning Incorporated Porous silicon compositions and devices and methods thereof
CN103137478A (zh) * 2011-11-21 2013-06-05 中芯国际集成电路制造(上海)有限公司 FinFET器件的制造方法及结构
US8637931B2 (en) 2011-12-27 2014-01-28 International Business Machines Corporation finFET with merged fins and vertical silicide
KR101894221B1 (ko) 2012-03-21 2018-10-04 삼성전자주식회사 전계 효과 트랜지스터 및 이를 포함하는 반도체 장치
US8664072B2 (en) 2012-05-30 2014-03-04 Globalfoundries Inc. Source and drain architecture in an active region of a P-channel transistor by tilted implantation
KR20140097569A (ko) * 2012-07-09 2014-08-06 도호쿠 다이가쿠 3차원 구조의 mosfet 및 그 제조 방법
US8975125B2 (en) * 2013-03-14 2015-03-10 International Business Machines Corporation Formation of bulk SiGe fin with dielectric isolation by anodization
US8859379B2 (en) 2013-03-15 2014-10-14 International Business Machines Corporation Stress enhanced finFET devices
US8940602B2 (en) 2013-04-11 2015-01-27 International Business Machines Corporation Self-aligned structure for bulk FinFET
KR102083493B1 (ko) 2013-08-02 2020-03-02 삼성전자 주식회사 반도체 소자의 제조방법
US9583590B2 (en) 2013-09-27 2017-02-28 Samsung Electronics Co., Ltd. Integrated circuit devices including FinFETs and methods of forming the same
US9711645B2 (en) * 2013-12-26 2017-07-18 International Business Machines Corporation Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment
US9391173B2 (en) * 2014-04-22 2016-07-12 International Business Machines Corporation FinFET device with vertical silicide on recessed source/drain epitaxy regions
CN105702725B (zh) * 2014-11-27 2018-12-11 中国科学院微电子研究所 半导体器件及其制造方法
CN105702729B (zh) * 2014-11-27 2019-01-15 中国科学院微电子研究所 半导体器件及其制造方法
US9741811B2 (en) 2014-12-15 2017-08-22 Samsung Electronics Co., Ltd. Integrated circuit devices including source/drain extension regions and methods of forming the same
US9666716B2 (en) 2014-12-15 2017-05-30 Sang U. Kim FinFET transistor
CN105789301B (zh) * 2014-12-25 2018-09-11 中国科学院微电子研究所 鳍式场效应晶体管、鳍结构及其制造方法
US9837277B2 (en) 2015-08-12 2017-12-05 International Business Machines Corporation Forming a contact for a tall fin transistor
US9397197B1 (en) 2015-09-23 2016-07-19 International Business Machines Corporation Forming wrap-around silicide contact on finFET
US9484251B1 (en) * 2015-10-30 2016-11-01 Lam Research Corporation Contact integration for reduced interface and series contact resistance
WO2017091543A1 (en) * 2015-11-25 2017-06-01 Corning Incorporated Porous silicon compositions and devices and methods thereof
CN107452792A (zh) * 2016-06-01 2017-12-08 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US9853127B1 (en) * 2016-06-22 2017-12-26 International Business Machines Corporation Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
CN108155236B (zh) * 2016-12-05 2020-08-07 上海新昇半导体科技有限公司 具有黑磷沟道层的低接触电阻率FinFET及其制备方法
US10707331B2 (en) * 2017-04-28 2020-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device with a reduced width

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JP3209164B2 (ja) * 1997-10-07 2001-09-17 日本電気株式会社 半導体装置の製造方法
US6133124A (en) * 1999-02-05 2000-10-17 Advanced Micro Devices, Inc. Device improvement by source to drain resistance lowering through undersilicidation
US6255214B1 (en) * 1999-02-24 2001-07-03 Advanced Micro Devices, Inc. Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions
EP1417434A4 (en) * 2001-07-25 2008-11-19 Philmac Pty Ltd TRANSITION FITTING OR FITTING FOR ASSEMBLING METAL OR PLASTIC PIPES
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6864519B2 (en) * 2002-11-26 2005-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS SRAM cell configured using multiple-gate transistors
US7105894B2 (en) * 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
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US20050090067A1 (en) * 2003-10-27 2005-04-28 Dharmesh Jawarani Silicide formation for a semiconductor device
KR100526889B1 (ko) * 2004-02-10 2005-11-09 삼성전자주식회사 핀 트랜지스터 구조
KR20050108916A (ko) * 2004-05-14 2005-11-17 삼성전자주식회사 다마신 공정을 이용한 핀 전계 효과 트랜지스터의 형성 방법
JP3964885B2 (ja) * 2004-05-19 2007-08-22 株式会社東芝 半導体装置及びその製造方法
US7015126B2 (en) * 2004-06-03 2006-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming silicided gate structure
JP2006012898A (ja) * 2004-06-22 2006-01-12 Toshiba Corp 半導体装置及びその製造方法

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