JP2009516929A - ガラス絶縁体上の大面積半導体 - Google Patents

ガラス絶縁体上の大面積半導体 Download PDF

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Publication number
JP2009516929A
JP2009516929A JP2008542321A JP2008542321A JP2009516929A JP 2009516929 A JP2009516929 A JP 2009516929A JP 2008542321 A JP2008542321 A JP 2008542321A JP 2008542321 A JP2008542321 A JP 2008542321A JP 2009516929 A JP2009516929 A JP 2009516929A
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JP
Japan
Prior art keywords
semiconductor
layer
glass substrate
glass
donor
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Abandoned
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JP2008542321A
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English (en)
Japanese (ja)
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JP2009516929A5 (enExample
Inventor
ピー ガドカリー，キショー
エム マイオール，アレクサンドル
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Corning Inc
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Corning Inc
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Application filed by Corning Inc filed Critical Corning Inc
Publication of JP2009516929A publication Critical patent/JP2009516929A/ja
Publication of JP2009516929A5 publication Critical patent/JP2009516929A5/ja
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
JP2008542321A 2005-11-22 2006-10-26 ガラス絶縁体上の大面積半導体 Abandoned JP2009516929A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US73963105P 2005-11-22 2005-11-22
US11/517,908 US7691730B2 (en) 2005-11-22 2006-09-08 Large area semiconductor on glass insulator
PCT/US2006/041660 WO2007061563A1 (en) 2005-11-22 2006-10-26 Large area semiconductor on glass insulator

Publications (2)

Publication Number Publication Date
JP2009516929A true JP2009516929A (ja) 2009-04-23
JP2009516929A5 JP2009516929A5 (enExample) 2009-12-17

Family

ID=37636113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008542321A Abandoned JP2009516929A (ja) 2005-11-22 2006-10-26 ガラス絶縁体上の大面積半導体

Country Status (5)

Country Link
US (2) US7691730B2 (enExample)
EP (1) EP1955371A1 (enExample)
JP (1) JP2009516929A (enExample)
KR (1) KR20080080571A (enExample)
WO (1) WO2007061563A1 (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009033139A (ja) * 2007-06-29 2009-02-12 Semiconductor Energy Lab Co Ltd 半導体装置の製造方法
JP2009065134A (ja) * 2007-08-10 2009-03-26 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
JP2013521203A (ja) * 2010-02-26 2013-06-10 コーニング インコーポレイテッド バルク散乱特性を有するガラスセラミック、およびその製造方法
US8946820B2 (en) 2011-06-30 2015-02-03 Sharp Kabushiki Kaisha Method for manufacturing semiconductor substrate, substrate for forming semiconductor substrate, stacked substrate, semiconductor substrate, and electronic device
US8981519B2 (en) 2010-11-05 2015-03-17 Sharp Kabushiki Kaisha Semiconductor substrate, method of manufacturing semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescence apparatus, wireless communication apparatus, and light emitting apparatus
US9041147B2 (en) 2012-01-10 2015-05-26 Sharp Kabushiki Kaisha Semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescent apparatus, semiconductor substrate manufacturing method, and semiconductor substrate manufacturing apparatus

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US8728937B2 (en) * 2004-07-30 2014-05-20 Osram Opto Semiconductors Gmbh Method for producing semiconductor chips using thin film technology
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
US7456057B2 (en) 2005-12-31 2008-11-25 Corning Incorporated Germanium on glass and glass-ceramic structures
KR20080092403A (ko) * 2006-01-03 2008-10-15 코닝 인코포레이티드 게르마늄 온 유리 및 유리-세라믹 구조체
US20080157090A1 (en) * 2006-12-28 2008-07-03 Darren Brent Thomson Transplanted epitaxial regrowth for fabricating large area substrates for electronic devices
US7825007B2 (en) * 2007-05-11 2010-11-02 Semiconductor Energy Laboratory Co., Ltd. Method of joining a plurality of SOI substrates on a glass substrate by a heat treatment
US9434642B2 (en) 2007-05-21 2016-09-06 Corning Incorporated Mechanically flexible and durable substrates
CN101681807B (zh) * 2007-06-01 2012-03-14 株式会社半导体能源研究所 半导体器件的制造方法
US7776718B2 (en) * 2007-06-25 2010-08-17 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor substrate with reduced gap size between single-crystalline layers
CN101743616B (zh) * 2007-06-28 2012-02-22 株式会社半导体能源研究所 半导体装置的制造方法
US8431451B2 (en) 2007-06-29 2013-04-30 Semicondutor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5460984B2 (ja) * 2007-08-17 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2009094488A (ja) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd 半導体膜付き基板の作製方法
JP2009076729A (ja) * 2007-09-21 2009-04-09 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP5250228B2 (ja) * 2007-09-21 2013-07-31 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5452900B2 (ja) * 2007-09-21 2014-03-26 株式会社半導体エネルギー研究所 半導体膜付き基板の作製方法
US8217498B2 (en) * 2007-10-18 2012-07-10 Corning Incorporated Gallium nitride semiconductor device on SOI and process for making same
US7977206B2 (en) * 2008-01-16 2011-07-12 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate using the heat treatment apparatus
JP2010087345A (ja) * 2008-10-01 2010-04-15 Semiconductor Energy Lab Co Ltd 半導体基板の作製方法
US8443863B2 (en) * 2008-10-23 2013-05-21 Corning Incorporated High temperature sheet handling system and methods
US7816225B2 (en) 2008-10-30 2010-10-19 Corning Incorporated Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
US8003491B2 (en) * 2008-10-30 2011-08-23 Corning Incorporated Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
TWI430338B (zh) 2008-10-30 2014-03-11 Corning Inc 使用定向剝離作用製造絕緣體上半導體結構之方法及裝置
JP5562696B2 (ja) * 2009-03-27 2014-07-30 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR101127574B1 (ko) 2009-04-06 2012-03-23 삼성모바일디스플레이주식회사 액티브 매트릭스 기판의 제조방법 및 유기 발광 표시장치의 제조방법
KR101058105B1 (ko) * 2009-04-06 2011-08-24 삼성모바일디스플레이주식회사 액티브 매트릭스 기판의 제조방법 및 유기 발광 표시장치의 제조방법
JP5725430B2 (ja) * 2011-10-18 2015-05-27 富士電機株式会社 固相接合ウエハの支持基板の剥離方法および半導体装置の製造方法
KR101901627B1 (ko) 2012-02-22 2018-09-27 더블유.알. 그레이스 앤드 캄파니-콘. 점토 경감용 작용기가 부여된 폴리아민
US8587025B1 (en) 2012-07-03 2013-11-19 Infineon Technologies Ag Method for forming laterally varying doping concentrations and a semiconductor device
TWI771375B (zh) 2017-02-24 2022-07-21 美商康寧公司 高寬高比玻璃晶圓
CN111712907A (zh) 2018-02-09 2020-09-25 迪德鲁科技(Bvi)有限公司 制造具有无载体模腔的扇出型封装的方法
CN112005369B (zh) 2018-02-15 2024-05-28 成都奕成集成电路有限公司 制造半导体器件的方法及半导体器件
US10424524B2 (en) 2018-02-15 2019-09-24 Chengdu Eswin Sip Technology Co., Ltd. Multiple wafers fabrication technique on large carrier with warpage control stiffener
WO2019160567A1 (en) * 2018-02-19 2019-08-22 Didrew Technology (Bvi) Limited System and method of fabricating glass frame fan out packaging

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009033139A (ja) * 2007-06-29 2009-02-12 Semiconductor Energy Lab Co Ltd 半導体装置の製造方法
JP2009065134A (ja) * 2007-08-10 2009-03-26 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
JP2013521203A (ja) * 2010-02-26 2013-06-10 コーニング インコーポレイテッド バルク散乱特性を有するガラスセラミック、およびその製造方法
US8981519B2 (en) 2010-11-05 2015-03-17 Sharp Kabushiki Kaisha Semiconductor substrate, method of manufacturing semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescence apparatus, wireless communication apparatus, and light emitting apparatus
US8946820B2 (en) 2011-06-30 2015-02-03 Sharp Kabushiki Kaisha Method for manufacturing semiconductor substrate, substrate for forming semiconductor substrate, stacked substrate, semiconductor substrate, and electronic device
US9041147B2 (en) 2012-01-10 2015-05-26 Sharp Kabushiki Kaisha Semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescent apparatus, semiconductor substrate manufacturing method, and semiconductor substrate manufacturing apparatus

Also Published As

Publication number Publication date
US20100112784A1 (en) 2010-05-06
US7691730B2 (en) 2010-04-06
US20070117354A1 (en) 2007-05-24
EP1955371A1 (en) 2008-08-13
KR20080080571A (ko) 2008-09-04
WO2007061563A1 (en) 2007-05-31

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