JP2009246337A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
JP2009246337A
JP2009246337A JP2008328986A JP2008328986A JP2009246337A JP 2009246337 A JP2009246337 A JP 2009246337A JP 2008328986 A JP2008328986 A JP 2008328986A JP 2008328986 A JP2008328986 A JP 2008328986A JP 2009246337 A JP2009246337 A JP 2009246337A
Authority
JP
Japan
Prior art keywords
semiconductor device
bonding pad
manufacturing
shape
connection bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008328986A
Other languages
English (en)
Japanese (ja)
Inventor
Shiann-Tsong Tsai
蔡憲聰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UTAC Taiwan Corp
Original Assignee
UTAC Taiwan Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UTAC Taiwan Corp filed Critical UTAC Taiwan Corp
Publication of JP2009246337A publication Critical patent/JP2009246337A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding

Landscapes

  • Wire Bonding (AREA)
JP2008328986A 2008-03-28 2008-12-25 半導体装置及びその製造方法 Pending JP2009246337A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW97111224 2008-03-28
TW097122489A TW200941672A (en) 2008-03-28 2008-06-17 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
JP2009246337A true JP2009246337A (ja) 2009-10-22

Family

ID=41115868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008328986A Pending JP2009246337A (ja) 2008-03-28 2008-12-25 半導体装置及びその製造方法

Country Status (3)

Country Link
US (1) US7993970B2 (https=)
JP (1) JP2009246337A (https=)
TW (1) TW200941672A (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10333841B4 (de) * 2003-07-24 2007-05-10 Infineon Technologies Ag Verfahren zur Herstellung eines Nutzens mit in Zeilen und Spalten angeordneten Halbleiterbauteilpositionen und Verfahren zur Herstellung eines Halbleiterbauteils
JP2011009570A (ja) * 2009-06-26 2011-01-13 Fujitsu Ltd 電子部品パッケージおよびその製造方法
JP2011077307A (ja) * 2009-09-30 2011-04-14 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
US8766439B2 (en) * 2009-12-10 2014-07-01 International Business Machines Corporation Integrated circuit chip with pyramid or cone-shaped conductive pads for flexible C4 connections and a method of forming the integrated circuit chip
KR101932727B1 (ko) * 2012-05-07 2018-12-27 삼성전자주식회사 범프 구조물, 이를 갖는 반도체 패키지 및 이의 제조 방법
KR102420126B1 (ko) 2016-02-01 2022-07-12 삼성전자주식회사 반도체 소자
US10516092B2 (en) * 2016-05-06 2019-12-24 Qualcomm Incorporated Interface substrate and method of making the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251363A (ja) * 1998-03-03 1999-09-17 Olympus Optical Co Ltd フリップチップ実装方法及びフリップチップ実装構造
JP2001223243A (ja) * 2000-02-14 2001-08-17 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2003152024A (ja) * 2001-11-14 2003-05-23 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492738B2 (en) * 1999-09-02 2002-12-10 Micron Technology, Inc. Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
US20030001286A1 (en) * 2000-01-28 2003-01-02 Ryoichi Kajiwara Semiconductor package and flip chip bonding method therein
ATE459099T1 (de) * 2000-03-10 2010-03-15 Chippac Inc Flipchip-verbindungsstruktur und dessen herstellungsverfahren
TW583757B (en) * 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251363A (ja) * 1998-03-03 1999-09-17 Olympus Optical Co Ltd フリップチップ実装方法及びフリップチップ実装構造
JP2001223243A (ja) * 2000-02-14 2001-08-17 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2003152024A (ja) * 2001-11-14 2003-05-23 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器

Also Published As

Publication number Publication date
TW200941672A (en) 2009-10-01
US20090243096A1 (en) 2009-10-01
TWI360872B (https=) 2012-03-21
US7993970B2 (en) 2011-08-09

Similar Documents

Publication Publication Date Title
JP5347222B2 (ja) 半導体装置の製造方法
KR100600683B1 (ko) 반도체 장치 및 그 제조 방법
JP5120342B2 (ja) 半導体パッケージの製造方法
TW200834853A (en) Wiring board and semiconductor device
JP2009246337A (ja) 半導体装置及びその製造方法
JP2007157795A (ja) 回路装置および回路装置の製造方法
JP4131681B2 (ja) 半導体装置の製造方法
CN109390306A (zh) 电子封装件
TWI527186B (zh) 半導體封裝及其製造方法
JP2018037504A5 (https=)
JP2008288489A (ja) チップ内蔵基板の製造方法
JP2011187635A (ja) 半導体装置およびその製造方法
JP2006310530A (ja) 回路装置およびその製造方法
JP5233853B2 (ja) 半導体装置
JP2002368155A (ja) 配線基板、半導体装置及び配線基板の製造方法
JP5812123B2 (ja) 電子機器の製造方法
JP2010040884A (ja) 半導体装置及び半導体チップのボンディング方法
JP2004253598A (ja) 電子部品の実装方法
US20130140067A1 (en) Wafer or circuit board and joining structure of wafer or circuit board
JP2012023409A (ja) 回路装置およびその製造方法
CN101562159A (zh) 半导体装置及其制法
JP2005353854A (ja) 配線基板およびそれを用いた半導体装置
JP2006032625A (ja) 半導体装置及びその製造方法
JP4723312B2 (ja) 半導体チップおよび半導体装置
JP3870013B2 (ja) ウェハレベルｃｓｐの端子形成方法

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110823

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110830

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120214