TW200941672A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
TW200941672A
TW200941672A TW097122489A TW97122489A TW200941672A TW 200941672 A TW200941672 A TW 200941672A TW 097122489 A TW097122489 A TW 097122489A TW 97122489 A TW97122489 A TW 97122489A TW 200941672 A TW200941672 A TW 200941672A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
bump
pad
substrate
shape
Prior art date
Application number
TW097122489A
Other languages
English (en)
Chinese (zh)
Other versions
TWI360872B (https=
Inventor
Shiann-Tsong Tsai
Original Assignee
United Test Ct Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Test Ct Inc filed Critical United Test Ct Inc
Priority to TW097122489A priority Critical patent/TW200941672A/zh
Priority to JP2008328986A priority patent/JP2009246337A/ja
Priority to US12/412,444 priority patent/US7993970B2/en
Publication of TW200941672A publication Critical patent/TW200941672A/zh
Application granted granted Critical
Publication of TWI360872B publication Critical patent/TWI360872B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding

Landscapes

  • Wire Bonding (AREA)
TW097122489A 2008-03-28 2008-06-17 Semiconductor device and method of manufacturing the same TW200941672A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW097122489A TW200941672A (en) 2008-03-28 2008-06-17 Semiconductor device and method of manufacturing the same
JP2008328986A JP2009246337A (ja) 2008-03-28 2008-12-25 半導体装置及びその製造方法
US12/412,444 US7993970B2 (en) 2008-03-28 2009-03-27 Semiconductor device and fabrication method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW97111224 2008-03-28
TW097122489A TW200941672A (en) 2008-03-28 2008-06-17 Semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
TW200941672A true TW200941672A (en) 2009-10-01
TWI360872B TWI360872B (https=) 2012-03-21

Family

ID=41115868

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097122489A TW200941672A (en) 2008-03-28 2008-06-17 Semiconductor device and method of manufacturing the same

Country Status (3)

Country Link
US (1) US7993970B2 (https=)
JP (1) JP2009246337A (https=)
TW (1) TW200941672A (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10333841B4 (de) * 2003-07-24 2007-05-10 Infineon Technologies Ag Verfahren zur Herstellung eines Nutzens mit in Zeilen und Spalten angeordneten Halbleiterbauteilpositionen und Verfahren zur Herstellung eines Halbleiterbauteils
JP2011009570A (ja) * 2009-06-26 2011-01-13 Fujitsu Ltd 電子部品パッケージおよびその製造方法
JP2011077307A (ja) * 2009-09-30 2011-04-14 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
US8766439B2 (en) * 2009-12-10 2014-07-01 International Business Machines Corporation Integrated circuit chip with pyramid or cone-shaped conductive pads for flexible C4 connections and a method of forming the integrated circuit chip
KR101932727B1 (ko) * 2012-05-07 2018-12-27 삼성전자주식회사 범프 구조물, 이를 갖는 반도체 패키지 및 이의 제조 방법
KR102420126B1 (ko) 2016-02-01 2022-07-12 삼성전자주식회사 반도체 소자
US10516092B2 (en) * 2016-05-06 2019-12-24 Qualcomm Incorporated Interface substrate and method of making the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251363A (ja) * 1998-03-03 1999-09-17 Olympus Optical Co Ltd フリップチップ実装方法及びフリップチップ実装構造
US6492738B2 (en) * 1999-09-02 2002-12-10 Micron Technology, Inc. Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
US20030001286A1 (en) * 2000-01-28 2003-01-02 Ryoichi Kajiwara Semiconductor package and flip chip bonding method therein
JP2001223243A (ja) * 2000-02-14 2001-08-17 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
ATE459099T1 (de) * 2000-03-10 2010-03-15 Chippac Inc Flipchip-verbindungsstruktur und dessen herstellungsverfahren
JP3582513B2 (ja) * 2001-11-14 2004-10-27 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
TW583757B (en) * 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof

Also Published As

Publication number Publication date
US20090243096A1 (en) 2009-10-01
TWI360872B (https=) 2012-03-21
JP2009246337A (ja) 2009-10-22
US7993970B2 (en) 2011-08-09

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