JP2009231322A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2009231322A
JP2009231322A JP2008071321A JP2008071321A JP2009231322A JP 2009231322 A JP2009231322 A JP 2009231322A JP 2008071321 A JP2008071321 A JP 2008071321A JP 2008071321 A JP2008071321 A JP 2008071321A JP 2009231322 A JP2009231322 A JP 2009231322A
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JP
Japan
Prior art keywords
chip
lead
leads
plating layer
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008071321A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009231322A5 (enrdf_load_stackoverflow
Inventor
Akihiko Kameoka
昭彦 亀岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2008071321A priority Critical patent/JP2009231322A/ja
Publication of JP2009231322A publication Critical patent/JP2009231322A/ja
Publication of JP2009231322A5 publication Critical patent/JP2009231322A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Lead Frames For Integrated Circuits (AREA)
JP2008071321A 2008-03-19 2008-03-19 半導体装置の製造方法 Pending JP2009231322A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008071321A JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008071321A JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2009231322A true JP2009231322A (ja) 2009-10-08
JP2009231322A5 JP2009231322A5 (enrdf_load_stackoverflow) 2011-03-03

Family

ID=41246440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008071321A Pending JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2009231322A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012074495A (ja) * 2010-09-28 2012-04-12 Dainippon Printing Co Ltd 半導体装置
US9263374B2 (en) 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor
JP2018117009A (ja) * 2017-01-17 2018-07-26 株式会社三井ハイテック リードフレームの製造方法およびリードフレーム

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818947A (ja) * 1981-07-27 1983-02-03 Toshiba Corp リ−ドフレ−ム
JPS61292928A (ja) * 1985-06-21 1986-12-23 Hitachi Ltd 半導体装置
JPS62145754A (ja) * 1985-12-20 1987-06-29 Hitachi Ltd 半導体装置
JPH03185855A (ja) * 1989-12-15 1991-08-13 Mitsui High Tec Inc リードフレームの製造方法
JPH0982870A (ja) * 1995-09-14 1997-03-28 Toshiba Corp 半導体装置、リードフレーム及びその製造方法
JPH09219486A (ja) * 1996-02-08 1997-08-19 Toppan Printing Co Ltd リードフレーム
JP2002329829A (ja) * 1992-03-27 2002-11-15 Hitachi Ltd 半導体集積回路装置およびその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818947A (ja) * 1981-07-27 1983-02-03 Toshiba Corp リ−ドフレ−ム
JPS61292928A (ja) * 1985-06-21 1986-12-23 Hitachi Ltd 半導体装置
JPS62145754A (ja) * 1985-12-20 1987-06-29 Hitachi Ltd 半導体装置
JPH03185855A (ja) * 1989-12-15 1991-08-13 Mitsui High Tec Inc リードフレームの製造方法
JP2002329829A (ja) * 1992-03-27 2002-11-15 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH0982870A (ja) * 1995-09-14 1997-03-28 Toshiba Corp 半導体装置、リードフレーム及びその製造方法
JPH09219486A (ja) * 1996-02-08 1997-08-19 Toppan Printing Co Ltd リードフレーム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012074495A (ja) * 2010-09-28 2012-04-12 Dainippon Printing Co Ltd 半導体装置
US9263374B2 (en) 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor
JP2018117009A (ja) * 2017-01-17 2018-07-26 株式会社三井ハイテック リードフレームの製造方法およびリードフレーム

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