JP2009231322A5 - - Google Patents

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Publication number
JP2009231322A5
JP2009231322A5 JP2008071321A JP2008071321A JP2009231322A5 JP 2009231322 A5 JP2009231322 A5 JP 2009231322A5 JP 2008071321 A JP2008071321 A JP 2008071321A JP 2008071321 A JP2008071321 A JP 2008071321A JP 2009231322 A5 JP2009231322 A5 JP 2009231322A5
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JP
Japan
Prior art keywords
die pad
leads
manufacturing
semiconductor device
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008071321A
Other languages
English (en)
Japanese (ja)
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JP2009231322A (ja
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Publication date
Application filed filed Critical
Priority to JP2008071321A priority Critical patent/JP2009231322A/ja
Priority claimed from JP2008071321A external-priority patent/JP2009231322A/ja
Publication of JP2009231322A publication Critical patent/JP2009231322A/ja
Publication of JP2009231322A5 publication Critical patent/JP2009231322A5/ja
Pending legal-status Critical Current

Links

JP2008071321A 2008-03-19 2008-03-19 半導体装置の製造方法 Pending JP2009231322A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008071321A JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008071321A JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2009231322A JP2009231322A (ja) 2009-10-08
JP2009231322A5 true JP2009231322A5 (enrdf_load_stackoverflow) 2011-03-03

Family

ID=41246440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008071321A Pending JP2009231322A (ja) 2008-03-19 2008-03-19 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2009231322A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5699322B2 (ja) * 2010-09-28 2015-04-08 大日本印刷株式会社 半導体装置
US9263374B2 (en) 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor
JP6788509B2 (ja) * 2017-01-17 2020-11-25 株式会社三井ハイテック リードフレームの製造方法およびリードフレーム

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818947A (ja) * 1981-07-27 1983-02-03 Toshiba Corp リ−ドフレ−ム
JPS61292928A (ja) * 1985-06-21 1986-12-23 Hitachi Ltd 半導体装置
JPS62145754A (ja) * 1985-12-20 1987-06-29 Hitachi Ltd 半導体装置
JPH0821657B2 (ja) * 1989-12-15 1996-03-04 株式会社三井ハイテック リードフレームの製造方法
KR100552353B1 (ko) * 1992-03-27 2006-06-20 가부시키가이샤 히타치초엘에스아이시스템즈 리이드프레임및그것을사용한반도체집적회로장치와그제조방법
JPH0982870A (ja) * 1995-09-14 1997-03-28 Toshiba Corp 半導体装置、リードフレーム及びその製造方法
JPH09219486A (ja) * 1996-02-08 1997-08-19 Toppan Printing Co Ltd リードフレーム

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