JP2009224509A - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 139
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 306
- 229910052751 metal Inorganic materials 0.000 claims abstract description 306
- 238000002955 isolation Methods 0.000 claims abstract description 88
- 238000000034 method Methods 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 44
- 229910021332 silicide Inorganic materials 0.000 claims description 39
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 150000001875 compounds Chemical class 0.000 claims description 28
- 238000009751 slip forming Methods 0.000 claims description 9
- 238000005192 partition Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 6
- 208000011380 COVID-19–associated multisystem inflammatory syndrome in children Diseases 0.000 abstract description 37
- 230000010354 integration Effects 0.000 abstract description 10
- 230000009977 dual effect Effects 0.000 abstract description 4
- 239000012789 electroconductive film Substances 0.000 abstract 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 64
- 229920005591 polysilicon Polymers 0.000 description 63
- 230000015572 biosynthetic process Effects 0.000 description 50
- 239000010410 layer Substances 0.000 description 27
- 125000006850 spacer group Chemical group 0.000 description 23
- 238000005530 etching Methods 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 230000002250 progressing effect Effects 0.000 description 6
- 229910004129 HfSiO Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
【解決手段】NMISトランジスタのゲート電極122aは、第1の金属含有導電膜104aと、第1の金属含有導電膜104a上に形成された第3の金属含有導電膜113とから構成されており、PMISトランジスタのゲート電極122bは、第2の金属含有導電膜104bと、第2の金属含有導電膜104b上に形成された第3の金属含有導電膜113とから構成されている。第3の金属含有導電膜113は、第1の金属含有導電膜104a及び第2の金属含有導電膜104bのそれぞれと接するように、第1の金属含有導電膜104a上から素子分離領域102上を経て第2の金属含有導電膜104bの上まで連続的に形成されている。
【選択図】図1
Description
S.C.Song他、Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration、VLSI Techonology、2006年8月6日、P.16
以下、本発明の第1の実施形態に係る半導体装置及びその製造方法について、図面を参照しながら説明する。
以下、本発明の第2の実施形態に係る半導体装置及びその製造方法について、図面を参照しながら説明する。
101A 第1の活性領域
101B 第2の活性領域
101a Pウェル領域
101b Nウェル領域
102 素子分離領域
103a 第1のゲート絶縁膜
103b 第2のゲート絶縁膜
104a 第1の金属含有導電膜
104b 第2の金属含有導電膜
104c 第3の金属含有導電膜
105a、105b ハードマスク
106 ポリシリコン膜
107 絶縁性オフセットスペーサー
108a N型エクステンション領域
108b P型エクステンション領域
109 絶縁性サイドウォールスペーサー
110a N型ソース・ドレイン領域
110b P型ソース・ドレイン領域
111 シリサイド層
112 層間絶縁膜
113 第3の金属含有導電膜
121a 第1のゲート部
121b 第2のゲート部
122a 第1のゲート電極
122b 第2のゲート電極
131a 第1のゲート部
131b 第2のゲート部
132a 第1のゲート電極
132b 第2のゲート電極
RA NMIS形成領域
RB PMIS形成領域
RC 素子分離形成領域
Claims (20)
- 半導体基板における第1の活性領域上に形成され、第1の金属含有導電膜を有する第1のゲート電極と、
前記半導体基板における第2の活性領域上に形成され、第2の金属含有導電膜を有する第2のゲート電極と、
前記第1の活性領域と前記第2の活性領域とを区画するように前記半導体基板に形成された素子分離領域とを備え、
前記第1の金属含有導電膜及び前記第2の金属含有導電膜はそれぞれ前記素子分離領域上に互いに離間して形成されており、
前記第1の金属含有導電膜上から前記素子分離領域上を経て前記第2の金属含有導電膜の上まで、前記第1のゲート電極及び前記第2のゲート電極のそれぞれの一部となる第3の金属含有導電膜が連続的に形成されており、
前記第3の金属含有導電膜は、前記第1の金属含有導電膜及び前記第2の金属含有導電膜のそれぞれと接していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第3の金属含有導電膜は前記素子分離領域と接していることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第3の金属含有導電膜は、前記素子分離領域上における前記第1の金属含有導電膜と前記第2の金属含有導電膜とに挟まれたスペースを埋めるように形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第3の金属含有導電膜と前記素子分離領域との間にはシリコン領域が介在することを特徴とする半導体装置。 - 請求項1〜4のいずれか1項に記載の半導体装置において、
前記第3の金属含有導電膜はシリサイドからなることを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記シリサイドはTi、Ni、Co又はPtを含むことを特徴とする半導体装置。 - 請求項1〜3のいずれか1項に記載の半導体装置において、
前記第3の金属含有導電膜上に、前記第1のゲート電極及び前記第2のゲート電極のそれぞれの一部となるシリコン膜がさらに形成されていることを特徴とする半導体装置。 - 請求項7に記載の半導体装置において、
前記シリコン膜の表面はシリサイド化されていることを特徴とする半導体装置。 - 請求項1〜8のいずれか1項に記載の半導体装置において、
前記第1の活性領域と前記第1のゲート電極との間に形成された第1の高誘電率ゲート絶縁膜と、
前記第2の活性領域と前記第2のゲート電極との間に形成された第2の高誘電率ゲート絶縁膜とをさらに備えていることを特徴とする半導体装置。 - 請求項1〜9のいずれか1項に記載の半導体装置において、
前記第1のゲート電極はN型MISトランジスタのゲート電極であり、
前記第1の金属含有導電膜は、仕事関数が4.55eV以下の材料からなることを特徴とする半導体装置。 - 請求項10に記載の半導体装置において、
前記第1の金属含有導電膜は、Ta化合物及びHf化合物のうちの少なくとも1つを含む材料からなることを特徴とする半導体装置。 - 請求項1〜11のいずれか1項に記載の半導体装置において、
前記第2のゲート電極はP型MISトランジスタのゲート電極であり、
前記第2の金属含有導電膜は、仕事関数が4.65eV以上の材料からなることを特徴とする半導体装置。 - 請求項12に記載の半導体装置において、
前記第2の金属含有導電膜は、Ti化合物及びRu化合物のうちの少なくとも1つを含む材料からなることを特徴とする半導体装置。 - 半導体基板における第1の活性領域と第2の活性領域とを区画するように、前記半導体基板に素子分離領域を形成する工程(a)と、
前記第1の活性領域上に、第1のゲート電極の一部となる第1の金属含有導電膜を形成する工程(b)と、
前記第2の活性領域上に、第2のゲート電極の一部となる第2の金属含有導電膜を形成する工程(c)と、
前記第1の金属含有導電膜上から前記素子分離領域上を経て前記第2の金属含有導電膜の上まで、前記第1のゲート電極及び前記第2のゲート電極のそれぞれの一部となる第3の金属含有導電膜を前記第1の金属含有導電膜及び前記第2の金属含有導電膜のそれぞれと接するように連続的に形成する工程(d)とを備え、
前記工程(d)において、前記第1の金属含有導電膜及び前記第2の金属含有導電膜はそれぞれ前記素子分離領域上に互いに離間して形成されていることを特徴とする半導体装置の製造方法。 - 請求項14に記載の半導体装置の製造方法において、
前記工程(b)は、前記半導体基板上に前記第1の金属含有導電膜を形成した後、前記第2の活性領域上の前記第1の金属含有導電膜を選択的に除去する工程を含み、
前記工程(c)は、前記半導体基板上に前記第2の金属含有導電膜を形成した後、前記第1の活性領域上の前記第2の金属含有導電膜を選択的に除去する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項14又は15に記載の半導体装置の製造方法において、
前記工程(d)は、前記第3の金属含有導電膜を前記素子分離領域と接するように形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項16に記載の半導体装置の製造方法において、
前記工程(d)は、前記第3の金属含有導電膜を、前記素子分離領域上における前記第1の金属含有導電膜と前記第2の金属含有導電膜とに挟まれたスペースを埋めるように形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項14〜17のいずれか1項に記載の半導体装置の製造方法において、
前記工程(d)は、前記第1の金属含有導電膜、前記素子分離領域及び前記第2の金属含有導電膜のそれぞれの上にシリコン膜を形成した後、前記第1の金属含有導電膜、前記第2の金属含有導電膜及び前記シリコン膜を前記第1のゲート電極及び前記第2のゲート電極のそれぞれの形状にパターニングし、その後、パターニングされた前記シリコン膜をシリサイド化して前記第3の金属含有導電膜を形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項14〜17のいずれか1項に記載の半導体装置の製造方法において、
前記工程(d)よりも後に、前記第3の金属含有導電膜上に、前記第1のゲート電極及び前記第2のゲート電極のそれぞれの一部となるシリコン膜を形成する工程(e)をさらに備えていることを特徴とする半導体装置の製造方法。 - 請求項19に記載の半導体装置の製造方法において、
前記工程(e)よりも後に、前記第1の金属含有導電膜、前記第2の金属含有導電膜、前記第3の金属含有導電膜及び前記シリコン膜を前記第1のゲート電極及び前記第2のゲート電極のそれぞれの形状にパターニングし、その後、パターニングされた前記シリコン膜の表面をシリサイド化する工程をさらに備えていることを特徴とする半導体装置の製造方法。
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