JP2009206490A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2009206490A
JP2009206490A JP2008315572A JP2008315572A JP2009206490A JP 2009206490 A JP2009206490 A JP 2009206490A JP 2008315572 A JP2008315572 A JP 2008315572A JP 2008315572 A JP2008315572 A JP 2008315572A JP 2009206490 A JP2009206490 A JP 2009206490A
Authority
JP
Japan
Prior art keywords
active region
gate electrode
region
semiconductor device
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2008315572A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009206490A5 (https=
Inventor
Eiji Kitamura
英次 北村
Shinichi Horiba
信一 堀場
Nobuyuki Nakamura
暢之 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP2008315572A priority Critical patent/JP2009206490A/ja
Priority to US12/362,498 priority patent/US20090189248A1/en
Publication of JP2009206490A publication Critical patent/JP2009206490A/ja
Priority to US13/252,006 priority patent/US8729642B2/en
Publication of JP2009206490A5 publication Critical patent/JP2009206490A5/ja
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP2008315572A 2008-01-30 2008-12-11 半導体装置及びその製造方法 Ceased JP2009206490A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008315572A JP2009206490A (ja) 2008-01-30 2008-12-11 半導体装置及びその製造方法
US12/362,498 US20090189248A1 (en) 2008-01-30 2009-01-30 Semiconductor device and method of manufacturing the same
US13/252,006 US8729642B2 (en) 2008-01-30 2011-10-03 Semiconductor device comprising a gate electrode having an opening

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008019163 2008-01-30
JP2008315572A JP2009206490A (ja) 2008-01-30 2008-12-11 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2009206490A true JP2009206490A (ja) 2009-09-10
JP2009206490A5 JP2009206490A5 (https=) 2011-11-24

Family

ID=40898355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008315572A Ceased JP2009206490A (ja) 2008-01-30 2008-12-11 半導体装置及びその製造方法

Country Status (2)

Country Link
US (2) US20090189248A1 (https=)
JP (1) JP2009206490A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012043970A (ja) * 2010-08-19 2012-03-01 Renesas Electronics Corp 半導体装置、メモリ装置への書込方法、メモリ装置からの読出方法、及び半導体装置の製造方法
KR101145383B1 (ko) 2010-02-25 2012-05-15 에스케이하이닉스 주식회사 반도체 장치의 전기적 퓨즈 및 그 제조방법
WO2014203813A1 (ja) * 2013-06-19 2014-12-24 ピーエスフォー ルクスコ エスエイアールエル 半導体装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8587037B1 (en) 2009-07-08 2013-11-19 Hrl Laboratories, Llc Test structure to monitor the in-situ channel temperature of field effect transistors
JP4937316B2 (ja) * 2009-08-21 2012-05-23 株式会社東芝 不揮発性半導体記憶装置
JP5727204B2 (ja) * 2009-12-11 2015-06-03 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR20120006707A (ko) * 2010-07-13 2012-01-19 주식회사 하이닉스반도체 반도체 소자의 안티퓨즈 및 그 제조 방법
US9842802B2 (en) 2012-06-29 2017-12-12 Qualcomm Incorporated Integrated circuit device featuring an antifuse and method of making same
US9502424B2 (en) 2012-06-29 2016-11-22 Qualcomm Incorporated Integrated circuit device featuring an antifuse and method of making same
US8975724B2 (en) * 2012-09-13 2015-03-10 Qualcomm Incorporated Anti-fuse device
WO2015148944A1 (en) * 2014-03-27 2015-10-01 Qualcomm Incorporated Integrated circuit device featuring an antifuse and method of making same
CN107667426B (zh) * 2015-06-25 2021-06-18 英特尔公司 反熔丝编程电压的受控修改
US10720389B2 (en) * 2017-11-02 2020-07-21 Nanya Technology Corporation Anti-fuse structure
US10522556B1 (en) * 2018-07-13 2019-12-31 Nanya Technology Corporation Antifuse structure
US11916016B2 (en) 2021-12-30 2024-02-27 Winbond Electronics Corp. Anti-fuse device and manufacturing method thereof
CN119053153B (zh) * 2023-05-22 2025-09-19 长鑫存储技术有限公司 反熔丝结构、反熔丝阵列及其操作方法、存储器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515344B1 (en) * 1999-10-28 2003-02-04 Advanced Micro Devices, Inc. Thin oxide anti-fuse
US20060226509A1 (en) * 2005-03-31 2006-10-12 Min Won G Antifuse element and electrically redundant antifuse array for controlled rupture location
JP2007536744A (ja) * 2004-05-06 2007-12-13 サイデンス コーポレーション 分割チャネルアンチヒューズアレイ構造

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3275893B2 (ja) 1999-09-27 2002-04-22 日本電気株式会社 半導体記憶素子
US6531410B2 (en) 2001-02-27 2003-03-11 International Business Machines Corporation Intrinsic dual gate oxide MOSFET using a damascene gate process
US7872897B2 (en) * 2003-04-11 2011-01-18 International Business Machines Corporation Programmable semiconductor device
US6879021B1 (en) * 2003-10-06 2005-04-12 International Business Machines Corporation Electronically programmable antifuse and circuits made therewith
US7755162B2 (en) * 2004-05-06 2010-07-13 Sidense Corp. Anti-fuse memory cell
US7553704B2 (en) * 2005-06-28 2009-06-30 Freescale Semiconductor, Inc. Antifuse element and method of manufacture
JP2007194486A (ja) 2006-01-20 2007-08-02 Elpida Memory Inc 半導体装置
WO2008057371A2 (en) * 2006-11-01 2008-05-15 Gumbo Logic, Inc Trap-charge non-volatile switch connector for programmable logic
JP5537020B2 (ja) * 2008-01-18 2014-07-02 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515344B1 (en) * 1999-10-28 2003-02-04 Advanced Micro Devices, Inc. Thin oxide anti-fuse
JP2007536744A (ja) * 2004-05-06 2007-12-13 サイデンス コーポレーション 分割チャネルアンチヒューズアレイ構造
US20060226509A1 (en) * 2005-03-31 2006-10-12 Min Won G Antifuse element and electrically redundant antifuse array for controlled rupture location

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101145383B1 (ko) 2010-02-25 2012-05-15 에스케이하이닉스 주식회사 반도체 장치의 전기적 퓨즈 및 그 제조방법
JP2012043970A (ja) * 2010-08-19 2012-03-01 Renesas Electronics Corp 半導体装置、メモリ装置への書込方法、メモリ装置からの読出方法、及び半導体装置の製造方法
WO2014203813A1 (ja) * 2013-06-19 2014-12-24 ピーエスフォー ルクスコ エスエイアールエル 半導体装置

Also Published As

Publication number Publication date
US20120018841A1 (en) 2012-01-26
US8729642B2 (en) 2014-05-20
US20090189248A1 (en) 2009-07-30

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