JP2009182289A - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 230000007547 defect Effects 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000001629 suppression Effects 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 16
- 230000005669 field effect Effects 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 2
- 230000002401 inhibitory effect Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 57
- 229910021332 silicide Inorganic materials 0.000 description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 230000007423 decrease Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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Abstract
【解決手段】この半導体装置100の製造方法は、p型シリコン基板1上にイオン注入による欠陥の増加を抑制する窒化膜30を形成する第1工程と、窒化膜30上からイオンを注入し、p型シリコン基板1表面にソース領域12およびドレイン領域13などの素子活性領域を形成する第2工程と、窒化膜30を除去する第3工程と、素子活性領域の界面準位の上昇を抑制する第1酸化膜5を素子活性領域上に形成する第4工程とを含む半導体装置の製造方法であって、窒化膜30は、第1酸化膜5よりも欠陥の増加を抑制でき、第1酸化膜5は、窒化膜30よりも界面準位の上昇を抑制できることを特徴とする。
【選択図】図1
Description
4 シリサイド膜(金属膜)
5 第1酸化膜(界面準位抑制膜)
6 第2酸化膜(応力緩和膜)
7 窒化膜(防湿膜)
10 電界効果型トランジスタ
12 ソース領域(素子活性領域)
13 ドレイン領域(素子活性領域)
20 バイポーラトランジスタ(接合型トランジスタ)
22 エミッタ層(素子活性領域)
23 ベース層(素子活性領域)
24 コレクタ層(素子活性領域)
30 窒化膜(欠陥抑制膜)
100 半導体装置
Claims (5)
- 半導体基板上に不純物の注入による欠陥の増加を抑制する欠陥抑制膜を形成する第1工程と、
前記欠陥抑制膜上から前記不純物を注入し、前記半導体基板表面に素子活性領域を形成する第2工程と、
前記欠陥抑制膜を除去する第3工程と、
前記素子活性領域の界面準位の上昇を抑制する界面準位抑制膜を前記素子活性領域上に形成する第4工程と、
を含む半導体装置の製造方法であって、
前記欠陥抑制膜は、前記界面準位抑制膜よりも前記欠陥の増加を抑制でき、
前記界面準位抑制膜は、前記欠陥抑制膜よりも前記界面準位の上昇を抑制できることを特徴とする半導体装置の製造方法。 - 前記素子活性領域上の、前記界面準位抑制膜の一部を開口する第5工程と、
前記開口された前記素子活性領域の前記半導体基板表面を金属化し、金属膜を形成する第6工程と、
前記金属膜上に応力緩和膜を形成する第7工程と、
前記界面準位抑制膜上に防湿膜を形成する第8工程と、
を含むことを特徴とする請求項1に記載された半導体装置の製造方法。 - 前記応力緩和膜は、前記界面準位抑制膜と前記防湿膜と接するように形成されることを特徴とする請求項2に記載された半導体装置の製造方法。
- 前記第4工程は、前記半導体基板上に酸化膜を堆積し、酸素雰囲気下にて前記酸化膜をアニールすることにより前記界面準位抑制膜を形成する工程を含むことを特徴とする請求項1から3のいずれかに記載された半導体装置の製造方法。
- 前記半導体基板には、接合型トランジスタと電界効果型トランジスタとが形成され、
前記第2工程には、
前記電界効果型トランジスタのソース領域およびドレイン領域を形成するための不純物を注入する工程と、
前記接合型トランジスタのエミッタ領域およびコレクタ領域およびベース領域のいずれかの領域を形成するための不純物を注入する工程と、
を含むことを特徴とする請求項1から4のいずれかに記載された半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2008022366A JP5283916B2 (ja) | 2008-02-01 | 2008-02-01 | 半導体装置の製造方法 |
CN2009100048546A CN101499439B (zh) | 2008-02-01 | 2009-01-21 | 半导体装置的制造方法 |
US12/363,553 US8110463B2 (en) | 2008-02-01 | 2009-01-30 | Method of fabricating semiconductor device |
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JP2008022366A JP5283916B2 (ja) | 2008-02-01 | 2008-02-01 | 半導体装置の製造方法 |
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JP2009182289A true JP2009182289A (ja) | 2009-08-13 |
JP5283916B2 JP5283916B2 (ja) | 2013-09-04 |
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JP2008022366A Active JP5283916B2 (ja) | 2008-02-01 | 2008-02-01 | 半導体装置の製造方法 |
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US (1) | US8110463B2 (ja) |
JP (1) | JP5283916B2 (ja) |
CN (1) | CN101499439B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011210743A (ja) * | 2010-03-17 | 2011-10-20 | Asahi Kasei Electronics Co Ltd | 半導体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04216634A (ja) * | 1990-12-14 | 1992-08-06 | Sharp Corp | 半導体装置の製造方法 |
JPH08339970A (ja) * | 1995-04-14 | 1996-12-24 | Sharp Corp | 半導体装置及びその製造方法 |
JP2000353670A (ja) * | 1999-06-10 | 2000-12-19 | Nec Corp | 半導体装置の製造方法 |
JP2004128388A (ja) * | 2002-10-07 | 2004-04-22 | Oki Electric Ind Co Ltd | Mosトランジスタの製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH056961A (ja) | 1991-06-26 | 1993-01-14 | Olympus Optical Co Ltd | 半導体装置の製造方法 |
KR940007466B1 (ko) * | 1991-11-14 | 1994-08-18 | 삼성전자 주식회사 | BiCMOS 소자의 제조방법 |
JP3240823B2 (ja) | 1994-04-27 | 2001-12-25 | ソニー株式会社 | BiCMOS型半導体装置の製造方法 |
US5525529A (en) * | 1994-11-16 | 1996-06-11 | Texas Instruments Incorporated | Method for reducing dopant diffusion |
FR2756100B1 (fr) * | 1996-11-19 | 1999-02-12 | Sgs Thomson Microelectronics | Transistor bipolaire a emetteur inhomogene dans un circuit integre bicmos |
US6420273B1 (en) * | 1997-06-30 | 2002-07-16 | Koninklijke Philips Electronics N.V. | Self-aligned etch-stop layer formation for semiconductor devices |
JP3953706B2 (ja) * | 2000-04-21 | 2007-08-08 | 松下電器産業株式会社 | 不揮発性半導体記憶装置の製造方法 |
SE519382C2 (sv) * | 2000-11-03 | 2003-02-25 | Ericsson Telefon Ab L M | Integrering av självinriktade MOS-högspänningskomponenter samt halvledarstruktur innefattande sådana |
JP2003234423A (ja) * | 2002-02-07 | 2003-08-22 | Sony Corp | 半導体装置及びその製造方法 |
US7402480B2 (en) * | 2004-07-01 | 2008-07-22 | Linear Technology Corporation | Method of fabricating a semiconductor device with multiple gate oxide thicknesses |
JP2007115971A (ja) * | 2005-10-21 | 2007-05-10 | Fujitsu Ltd | 半導体装置とその製造方法 |
JP3971442B2 (ja) | 2006-07-20 | 2007-09-05 | 株式会社東芝 | 半導体装置の製造方法 |
-
2008
- 2008-02-01 JP JP2008022366A patent/JP5283916B2/ja active Active
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2009
- 2009-01-21 CN CN2009100048546A patent/CN101499439B/zh not_active Expired - Fee Related
- 2009-01-30 US US12/363,553 patent/US8110463B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04216634A (ja) * | 1990-12-14 | 1992-08-06 | Sharp Corp | 半導体装置の製造方法 |
JPH08339970A (ja) * | 1995-04-14 | 1996-12-24 | Sharp Corp | 半導体装置及びその製造方法 |
JP2000353670A (ja) * | 1999-06-10 | 2000-12-19 | Nec Corp | 半導体装置の製造方法 |
JP2004128388A (ja) * | 2002-10-07 | 2004-04-22 | Oki Electric Ind Co Ltd | Mosトランジスタの製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011210743A (ja) * | 2010-03-17 | 2011-10-20 | Asahi Kasei Electronics Co Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
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JP5283916B2 (ja) | 2013-09-04 |
US8110463B2 (en) | 2012-02-07 |
CN101499439A (zh) | 2009-08-05 |
US20090197378A1 (en) | 2009-08-06 |
CN101499439B (zh) | 2012-05-16 |
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