JP2009147029A5 - - Google Patents

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Publication number
JP2009147029A5
JP2009147029A5 JP2007321390A JP2007321390A JP2009147029A5 JP 2009147029 A5 JP2009147029 A5 JP 2009147029A5 JP 2007321390 A JP2007321390 A JP 2007321390A JP 2007321390 A JP2007321390 A JP 2007321390A JP 2009147029 A5 JP2009147029 A5 JP 2009147029A5
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JP
Japan
Prior art keywords
solder resist
conductor patterns
pattern group
pattern
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007321390A
Other languages
English (en)
Japanese (ja)
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JP2009147029A (ja
JP5107012B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2007321390A priority Critical patent/JP5107012B2/ja
Priority claimed from JP2007321390A external-priority patent/JP5107012B2/ja
Priority to US12/330,946 priority patent/US7880314B2/en
Publication of JP2009147029A publication Critical patent/JP2009147029A/ja
Publication of JP2009147029A5 publication Critical patent/JP2009147029A5/ja
Application granted granted Critical
Publication of JP5107012B2 publication Critical patent/JP5107012B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2007321390A 2007-12-12 2007-12-12 配線基板及び電子部品の実装構造の製造方法 Expired - Fee Related JP5107012B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007321390A JP5107012B2 (ja) 2007-12-12 2007-12-12 配線基板及び電子部品の実装構造の製造方法
US12/330,946 US7880314B2 (en) 2007-12-12 2008-12-09 Wiring substrate and electronic component mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007321390A JP5107012B2 (ja) 2007-12-12 2007-12-12 配線基板及び電子部品の実装構造の製造方法

Publications (3)

Publication Number Publication Date
JP2009147029A JP2009147029A (ja) 2009-07-02
JP2009147029A5 true JP2009147029A5 (https=) 2010-10-14
JP5107012B2 JP5107012B2 (ja) 2012-12-26

Family

ID=40752124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007321390A Expired - Fee Related JP5107012B2 (ja) 2007-12-12 2007-12-12 配線基板及び電子部品の実装構造の製造方法

Country Status (2)

Country Link
US (1) US7880314B2 (https=)
JP (1) JP5107012B2 (https=)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853001B2 (en) 2003-11-08 2014-10-07 Stats Chippac, Ltd. Semiconductor device and method of forming pad layout for flipchip semiconductor die
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
TWI534915B (zh) 2003-11-10 2016-05-21 恰巴克有限公司 引線上凸塊之倒裝晶片互連
US8350384B2 (en) 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8076232B2 (en) * 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
JP2008535225A (ja) 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
US20060255473A1 (en) 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
US8349721B2 (en) 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US7897502B2 (en) 2008-09-10 2011-03-01 Stats Chippac, Ltd. Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
US8198186B2 (en) 2008-12-31 2012-06-12 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US20100237500A1 (en) * 2009-03-20 2010-09-23 Stats Chippac, Ltd. Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
US8039384B2 (en) 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US8409978B2 (en) 2010-06-24 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
US8536718B2 (en) * 2010-06-24 2013-09-17 Stats Chippac Ltd. Integrated circuit packaging system with trenches and method of manufacture thereof
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8435834B2 (en) 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US10461060B2 (en) * 2017-05-31 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with redistribution layers

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3390664B2 (ja) 1997-10-16 2003-03-24 新光電気工業株式会社 フリップチップ実装用基板及びフリップチップ実装構造
JP3420076B2 (ja) 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
JP3554533B2 (ja) * 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
US6821878B2 (en) * 2003-02-27 2004-11-23 Freescale Semiconductor, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
JP4088561B2 (ja) * 2003-06-17 2008-05-21 新光電気工業株式会社 フリップチップ実装用基板
TWI245389B (en) * 2003-10-02 2005-12-11 Siliconware Precision Industries Co Ltd Conductive trace structure and semiconductor package having the conductive trace structure
JP2005116685A (ja) * 2003-10-06 2005-04-28 Seiko Epson Corp プリント配線基板、電子部品モジュール及び電子機器
US20060091542A1 (en) * 2004-11-03 2006-05-04 Broadcom Corporation Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same
JP2007116040A (ja) * 2005-10-24 2007-05-10 Alps Electric Co Ltd 回路基板
JP2008060159A (ja) * 2006-08-29 2008-03-13 Renesas Technology Corp 半導体装置およびその製造方法

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