JP2009117465A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 238000004519 manufacturing process Methods 0.000 title claims description 50
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 51
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 48
- 238000002955 isolation Methods 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 30
- 238000001039 wet etching Methods 0.000 claims description 25
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 9
- 238000005192 partition Methods 0.000 claims description 6
- 239000003963 antioxidant agent Substances 0.000 claims description 2
- 230000003078 antioxidant effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 84
- 239000010408 film Substances 0.000 description 322
- 239000012535 impurity Substances 0.000 description 26
- 238000012986 modification Methods 0.000 description 20
- 230000004048 modification Effects 0.000 description 19
- 230000008569 process Effects 0.000 description 19
- 239000010410 layer Substances 0.000 description 15
- 230000000694 effects Effects 0.000 description 8
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Abstract
【解決手段】低電圧系トランジスタ形成領域Aに形成された第1のMIS型トランジスタは、ゲート絶縁膜5と、金属膜6及び多結晶シリコン膜9からなる第1のゲート電極とを含む。高電圧系トランジスタ形成領域Bに形成された第2のMIS型トランジスタは、ゲート絶縁膜5と、多結晶シリコン膜9からなる第2のゲート電極とを含む。低電圧系トランジスタ形成領域Aのゲート絶縁膜5の等価酸化膜厚は、高電圧系トランジスタ形成領域Bのゲート絶縁膜5の等価酸化膜厚よりも薄く、低電圧系トランジスタ形成領域Aの基板表面高さは、高電圧系トランジスタ形成領域Bの基板表面高さよりも高い。
【選択図】図3
Description
以下に、本発明の一実施形態の変形例1及び変形例2について、図面を参照しながら説明する。本変形例1及び変形例2では、上述した実施形態における高電圧系トランジスタ形成領域Bのシリコン窒化膜7を除去する工程に関して、上述とは異なる工程を採用するものであって、上述した実施形態では生じ得る以下の事態を考慮したものである。すなわち、上述した実施形態における図2(d)に示す工程において、薄膜のゲート絶縁膜5をエッチングストップ膜として用いて、シリコン窒化膜7をドライエッチングにより除去する際に、薄膜のゲート絶縁膜5及びシリコン窒化膜7のエッチング選択比を十分に大きく取れない場合には、シリコン窒化膜7のウエハ面内における膜厚バラツキ、又は、薄膜のゲート絶縁膜5のウエハ面内における膜厚バラツキが大きくなり、ドライエッチング時にウエハ面内の一部領域において薄膜のゲート絶縁膜5が削り取られてしまうことが想定される。そうなると、高電圧系トランジスタ形成領域における半導体基板1bの表面がドライエッチングに曝されてしまうために、半導体基板1bの表面に荒れが生じて、高電圧系トランジスタの特性バラツキが大きくなったり、信頼性が損なわれたりすることが予想される。
以下に、本発明の一実施形態の変形例1に係る半導体装置及びその製造方法について説明する。なお、本変形例1では、以下で説明するように、高電圧系トランジスタ形成領域Bにおけるシリコン窒化膜7をウエットエッチングにより除去するものであって、シリコン窒化膜7の除去方法のプロセスマージンを広げるものである。
以下に、本発明の一実施形態の変形例2に係る半導体装置及びその製造方法について説明する。なお、本変形例2では、以下で説明するように、金属膜6をエッチングストップ膜として用いて、高電圧系トランジスタ形成領域Bにおけるシリコン窒化膜7をドライエッチングにより除去するものである。
B 高電圧系トランジスタ形成領域
1a、1b 半導体基板
2 犠牲酸化膜
3 素子分離領域
4a、4b 不純物層
5 薄膜のゲート絶縁膜
6 金属膜
7 シリコン窒化膜
8 厚膜のゲート絶縁膜
9 多結晶シリコン膜
11 シリコン酸化膜
51〜55 レジストパターン
d1 半導体基板表面の後退量
h 素子分離領域上の段差
s1 素子分離領域における窪み量
s2 素子分離領域における窪み量
t1 薄膜のゲート絶縁膜の膜厚
t2 厚膜のゲート絶縁膜の膜厚
101a、101b 半導体基板
102 犠牲酸化膜
103 素子分離領域
104a、104b 不純物層
105 厚膜のゲート絶縁膜
106 レジストマスク
107 薄膜のゲート絶縁膜
108 多結晶シリコン膜
d101 半導体基板表面の後退量
d102 半導体基板表面の後退量
Claims (16)
- 半導体基板における第1の領域上に形成された第1のMIS型トランジスタと、前記半導体基板における前記第1の領域とは異なる第2の領域に形成された第2のMIS型トランジスタとを有する半導体装置であって、
前記第1のMIS型トランジスタは、
前記第1の領域上に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に、金属膜及び多結晶シリコン膜が下から順に形成されてなる第1のゲート電極とを含み、
前記第2のMIS型トランジスタは、
前記第2の領域上に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成された多結晶シリコン膜からなる第2のゲート電極とを含み、
前記第1のゲート絶縁膜の等価酸化膜厚は、前記第2のゲート絶縁膜の等価酸化膜厚よりも薄く、
前記第1の領域における前記半導体基板の表面高さは、前記第2の領域における前記半導体基板の表面高さよりも高い、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1のゲート絶縁膜は、シリコン酸化膜の比誘電率よりも高い比誘電率を有する絶縁膜を含んでいる、半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第2のゲート絶縁膜は、シリコン酸化膜からなる、半導体装置。 - 請求項1〜3のうちのいずれか1項に記載の半導体装置において、
前記半導体基板に、前記第1の領域及び前記第2の領域の各々を区画すると共に前記第1の領域と前記第2の領域とを電気的に分離するように形成された素子分離領域をさらに備え、
前記第1の領域と前記第2の領域との境界において、前記第1の領域側の前記素子分離領域の高さは、前記第2の領域側の前記素子分離領域の高さよりも高い、半導体装置。 - 請求項1〜4のうちのいずれか1項に記載の半導体装置において、
前記半導体基板に、前記第1の領域及び前記第2の領域の各々を区画すると共に前記第1の領域と前記第2の領域とを電気的に分離するように形成された素子分離領域をさらに備え、
前記第1の領域における前記素子分離領域に形成された窪み量は、前記第2の領域における前記素子分離領域に形成された窪み量よりも小さい、半導体装置。 - 請求項1〜5のうちのいずれか1項に記載の半導体装置において、
前記第1のMIS型トランジスタは、低電圧系トランジスタであり、
前記第2のMIS型トランジスタは、高電圧系トランジスタである、半導体装置。 - 請求項1〜6のうちのいずれか1項に記載の半導体装置において、
前記第1のMIS型トランジスタ及び前記第2のMIS型トランジスタは、同一の導電型のトランジスタである、半導体装置。 - 半導体基板における第1の領域及び第2の領域上に、第1のゲート絶縁膜及び金属膜を下から順に形成する工程(a)と、
前記第2の領域上の前記金属膜を除去する工程(b)と、
前記工程(b)の後に、前記第2の領域上の前記第1のゲート絶縁膜を除去する工程(c)と、
前記工程(c)の後に、前記第1の領域上に前記第1のゲート絶縁膜及び前記金属膜を残存させた状態で、前記第2の領域上に、前記第1のゲート絶縁膜の等価酸化膜厚よりも厚い等価酸化膜厚を有する第2のゲート絶縁膜を形成する工程(d)と、
前記工程(d)の後に、前記第1の領域上に露出する前記金属膜と前記第2の領域上に露出する前記第2のゲート絶縁膜との上に多結晶シリコン膜を形成する工程(e)と、
前記多結晶シリコン膜及び前記金属膜をパターニングして、前記第1の領域上に前記第1のゲート絶縁膜を介して前記金属膜及び前記多結晶シリコン膜からなる第1のゲート電極を形成すると共に、前記第2の領域上に前記第2のゲート絶縁膜を介して前記多結晶シリコン膜からなる第2のゲート電極を形成する工程(f)とを備える、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記工程(b)の後で、前記工程(c)の前に、前記第1の領域上の前記金属膜を覆うマスク膜を形成する工程(g)をさらに備え、
前記工程(c)では、前記マスク膜をエッチングマスクに用いたエッチングにより、前記第2の領域上の前記第1のゲート絶縁膜を除去する、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記工程(g)は、前記第1の領域及び前記第2の領域の上にシリコン窒化膜を形成する工程(g1)と、前記第1の領域上の前記シリコン窒化膜を覆うレジストパターンをエッチングマスクに用いたドライエッチングにより、前記第2の領域上の前記シリコン窒化膜を除去して、前記シリコン窒化膜からなる前記マスク膜を形成する工程(g2)とを含む、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記工程(g)は、前記第1の領域及び前記第2の領域の上にシリコン窒化膜を形成する工程(g1)と、前記第1の領域上の前記シリコン窒化膜を覆うシリコン酸化膜をエッチングマスクに用いたウェットエッチングにより、前記第2の領域上の前記シリコン窒化膜を除去して、前記シリコン窒化膜からなる前記マスク膜を形成する工程(g2)とを含む、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記工程(b)は、前記第1の領域及び前記第2の領域上の前記金属膜の上にシリコン窒化膜を形成する工程(b1)と、前記第2の領域上の前記シリコン窒化膜を除去して、前記第1の領域上の前記金属膜を覆う前記シリコン窒化膜からなるマスク膜を形成する工程(b2)と、前記マスク膜をエッチングマスクに用いたエッチングより、前記第2の領域上の前記金属膜を除去する工程(b3)とを含み、
前記工程(c)では、前記マスク膜をエッチングマスクに用いたエッチングにより、前記第2の領域上の前記第1のゲート絶縁膜を除去する、半導体装置の製造方法。 - 請求項9〜12のうちのいずれか1項に記載の半導体装置の製造方法において、
工程(d)は、前記マスク膜を酸化防止マスクに用いた熱酸化法により、前記第2のゲート絶縁膜を形成する工程を含む、半導体装置の製造方法。 - 請求項9〜13のうちのいずれか1項に記載の半導体装置の製造方法において、
工程(d)は、熱酸化法により第1のシリコン酸化膜を形成した後、CVD法により前記第1のシリコン酸化膜上に第2のシリコン酸化膜を形成することにより、前記第1のシリコン酸化膜及び前記第2のシリコン酸化膜からなる前記第2のゲート絶縁膜を形成する工程を含む、半導体装置の製造方法。 - 請求項8〜14のうちのいずれか1項に記載の半導体装置の製造方法において、
工程(a)は、前記第1の領域及び前記第2の領域上に、シリコン酸化膜と、前記シリコン酸化膜の比誘電率よりも高い比誘電率を有する絶縁膜とを下から順に形成してなる前記第1のゲート絶縁膜を形成する工程を含む、半導体装置の製造方法。 - 請求項8〜15のうちのいずれか1項に記載の半導体装置の製造方法において、
工程(c)は、弗酸を用いたウエットエッチングにより、前記第1のゲート絶縁膜を除去する工程を含む、半導体装置の製造方法。
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