JP2009105366A - 半導体装置及び半導体装置の製造方法ならびに半導体装置の実装体 - Google Patents

半導体装置及び半導体装置の製造方法ならびに半導体装置の実装体 Download PDF

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Publication number
JP2009105366A
JP2009105366A JP2008097648A JP2008097648A JP2009105366A JP 2009105366 A JP2009105366 A JP 2009105366A JP 2008097648 A JP2008097648 A JP 2008097648A JP 2008097648 A JP2008097648 A JP 2008097648A JP 2009105366 A JP2009105366 A JP 2009105366A
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JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
metal layer
tape carrier
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008097648A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009105366A5 (enrdf_load_stackoverflow
Inventor
Yoshifumi Nakamura
嘉文 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2008097648A priority Critical patent/JP2009105366A/ja
Priority to US12/211,364 priority patent/US20090091021A1/en
Publication of JP2009105366A publication Critical patent/JP2009105366A/ja
Publication of JP2009105366A5 publication Critical patent/JP2009105366A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP2008097648A 2007-10-03 2008-04-04 半導体装置及び半導体装置の製造方法ならびに半導体装置の実装体 Withdrawn JP2009105366A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008097648A JP2009105366A (ja) 2007-10-03 2008-04-04 半導体装置及び半導体装置の製造方法ならびに半導体装置の実装体
US12/211,364 US20090091021A1 (en) 2007-10-03 2008-09-16 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007259296 2007-10-03
JP2008097648A JP2009105366A (ja) 2007-10-03 2008-04-04 半導体装置及び半導体装置の製造方法ならびに半導体装置の実装体

Publications (2)

Publication Number Publication Date
JP2009105366A true JP2009105366A (ja) 2009-05-14
JP2009105366A5 JP2009105366A5 (enrdf_load_stackoverflow) 2011-04-14

Family

ID=40538210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008097648A Withdrawn JP2009105366A (ja) 2007-10-03 2008-04-04 半導体装置及び半導体装置の製造方法ならびに半導体装置の実装体

Country Status (2)

Country Link
JP (1) JP2009105366A (enrdf_load_stackoverflow)
CN (1) CN101404267A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853851B2 (en) 2011-03-25 2014-10-07 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing the same
KR20160000543A (ko) * 2014-06-24 2016-01-05 매그나칩 반도체 유한회사 방열 반도체 칩 패키지 및 그 제조 방법
CN113327899A (zh) * 2021-04-22 2021-08-31 成都芯源系统有限公司 倒装芯片封装单元及封装方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8508056B2 (en) * 2009-06-16 2013-08-13 Dongbu Hitek Co., Ltd. Heat releasing semiconductor package, method for manufacturing the same, and display apparatus including the same
TWI485825B (zh) * 2009-07-28 2015-05-21 Xintec Inc 晶片封裝體及其形成方法
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8848380B2 (en) * 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
WO2013172814A1 (en) 2012-05-14 2013-11-21 Intel Corporation Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
CN103594434B (zh) * 2013-10-23 2017-12-29 广东明路电力电子有限公司 带复合散热层的功率部件
TWI697079B (zh) * 2019-03-06 2020-06-21 南茂科技股份有限公司 薄膜覆晶封裝結構
KR102601150B1 (ko) * 2019-08-23 2023-11-09 삼성전자주식회사 반도체 패키지
JP7107295B2 (ja) * 2019-09-27 2022-07-27 株式会社デンソー 電子装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853851B2 (en) 2011-03-25 2014-10-07 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing the same
US8962394B2 (en) 2011-03-25 2015-02-24 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing the same
KR20160000543A (ko) * 2014-06-24 2016-01-05 매그나칩 반도체 유한회사 방열 반도체 칩 패키지 및 그 제조 방법
KR101630769B1 (ko) * 2014-06-24 2016-06-16 매그나칩 반도체 유한회사 방열 반도체 칩 패키지 및 그 제조 방법
US10340156B2 (en) 2014-06-24 2019-07-02 Magnachip Semiconductor, Ltd. Heat releasing semiconductor chip package and method for manufacturing the same
US11289345B2 (en) 2014-06-24 2022-03-29 Magnachip Semiconductor, Ltd. Heat releasing semiconductor chip package and method for manufacturing the same
CN113327899A (zh) * 2021-04-22 2021-08-31 成都芯源系统有限公司 倒装芯片封装单元及封装方法

Also Published As

Publication number Publication date
CN101404267A (zh) 2009-04-08

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