JP2009088500A - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP2009088500A
JP2009088500A JP2008233578A JP2008233578A JP2009088500A JP 2009088500 A JP2009088500 A JP 2009088500A JP 2008233578 A JP2008233578 A JP 2008233578A JP 2008233578 A JP2008233578 A JP 2008233578A JP 2009088500 A JP2009088500 A JP 2009088500A
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Japan
Prior art keywords
layer
substrate
semiconductor substrate
insulating layer
semiconductor
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JP2008233578A
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Japanese (ja)
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JP2009088500A5 (https=
Inventor
Shunpei Yamazaki
舜平 山崎
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008233578A priority Critical patent/JP2009088500A/ja
Publication of JP2009088500A publication Critical patent/JP2009088500A/ja
Publication of JP2009088500A5 publication Critical patent/JP2009088500A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Thin Film Transistor (AREA)
JP2008233578A 2007-09-14 2008-09-11 Ｓｏｉ基板の作製方法 Withdrawn JP2009088500A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008233578A JP2009088500A (ja) 2007-09-14 2008-09-11 Ｓｏｉ基板の作製方法

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Application Number Priority Date Filing Date Title
JP2007239524 2007-09-14
JP2008233578A JP2009088500A (ja) 2007-09-14 2008-09-11 Ｓｏｉ基板の作製方法

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JP2009088500A true JP2009088500A (ja) 2009-04-23
JP2009088500A5 JP2009088500A5 (https=) 2011-10-13

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JP2008233578A Withdrawn JP2009088500A (ja) 2007-09-14 2008-09-11 Ｓｏｉ基板の作製方法

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US (1) US8314009B2 (https=)
JP (1) JP2009088500A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7508034B2 (en) * 2002-09-25 2009-03-24 Sharp Kabushiki Kaisha Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device
TWI493609B (zh) * 2007-10-23 2015-07-21 半導體能源研究所股份有限公司 半導體基板、顯示面板及顯示裝置的製造方法
US8735263B2 (en) 2011-01-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

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JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH08255762A (ja) * 1995-03-17 1996-10-01 Nec Corp 半導体デバイスの製造方法
JPH10162770A (ja) * 1996-05-15 1998-06-19 Semiconductor Energy Lab Co Ltd ドーピング装置およびドーピング処理方法
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US8314009B2 (en) 2012-11-20

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