JP2009076771A - 半導体ウェーハの作製方法 - Google Patents
半導体ウェーハの作製方法 Download PDFInfo
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- JP2009076771A JP2009076771A JP2007245809A JP2007245809A JP2009076771A JP 2009076771 A JP2009076771 A JP 2009076771A JP 2007245809 A JP2007245809 A JP 2007245809A JP 2007245809 A JP2007245809 A JP 2007245809A JP 2009076771 A JP2009076771 A JP 2009076771A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
- H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Abstract
【解決手段】第1の半導体ウェーハの表面上に接合層を形成し、イオンドーピング装置によりH3 +イオンを第1の半導体ウェーハに照射して接合層の下方に分離層を形成する。高い電圧によって加速されたH3 +イオンは、半導体ウェーハ表面で分離されて3つのH+イオンとなり、それぞれのH+イオンは深く侵入することはできない。従って、従来のイオン注入法よりも半導体ウェーハの浅い領域にH+イオンを高濃度に添加することができる。
【選択図】図1
Description
102:接合層
103:分離層
104:単結晶半導体層
105:第2の半導体ウェーハ
106:保護層
107:素子分離絶縁層
108:ゲート絶縁層
109:ゲート電極
110:第2の絶縁膜
111:第1不純物領域
112:第2不純物領域
113:サイドウォール絶縁層
114:サイドウォール絶縁層
115:第3不純物領域
116:第4不純物領域
120:層間絶縁膜
121:コンタクトプラグ
122:nFET
123:pFET
Claims (6)
- 第1の半導体ウェーハの表面上に接合層を形成し、
イオンドーピング装置によりH3 +イオンを前記第1の半導体ウェーハに照射して前記接合層の下方に分離層を形成し、
前記第1の半導体ウェーハの接合層を第2の半導体ウェーハの一方の面に貼り合わせ、
熱処理を行うことにより前記分離層の層内または前記分離層界面を劈開面として前記第1の半導体ウェーハの一部を分離して、前記第2の半導体ウェーハの一方の面上に、前記接合層と、前記接合層上に単結晶半導体層とを有する半導体ウェーハの作製方法。 - 請求項2において、前記照射されたH3 +イオンは、前記接合層の表面で3つのH+イオンに分離し、前記第1の半導体ウェーハ中に添加される半導体ウェーハの作製方法。
- 請求項1または請求項2において、前記接合層は、プラズマCVD法により得られる酸化シリコンを含む絶縁膜である半導体ウェーハの作製方法。
- 請求項1乃至3のいずれか一において、前記H3 +イオンの照射は、断面が線状または長方形のイオン流を発生させて照射する半導体ウェーハの作製方法。
- 請求項1乃至4のいずれか一において、さらに第2の半導体ウェーハの一方の面に接合層を形成した後、該接合層を前記第1の半導体ウェーハの接合層に貼り合わせる半導体ウェーハの作製方法。
- 請求項1乃至5のいずれか一において、前記第1の半導体ウェーハの結晶方位は、(100)面である半導体ウェーハの作製方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007245809A JP5325404B2 (ja) | 2007-09-21 | 2007-09-21 | Soi基板の作製方法 |
US12/210,304 US7829434B2 (en) | 2007-09-21 | 2008-09-15 | Method for manufacturing semiconductor wafer |
KR20080091426A KR101493301B1 (ko) | 2007-09-21 | 2008-09-18 | 반도체 웨이퍼의 제작 방법 |
CN2008101494944A CN101393860B (zh) | 2007-09-21 | 2008-09-18 | 半导体片的制造方法 |
TW097135883A TWI446413B (zh) | 2007-09-21 | 2008-09-18 | 半導體晶片的製造方法 |
US12/862,197 US8043939B2 (en) | 2007-09-21 | 2010-08-24 | Method for manufacturing semiconductor wafer |
Applications Claiming Priority (1)
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JP2007245809A JP5325404B2 (ja) | 2007-09-21 | 2007-09-21 | Soi基板の作製方法 |
Publications (3)
Publication Number | Publication Date |
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JP2009076771A true JP2009076771A (ja) | 2009-04-09 |
JP2009076771A5 JP2009076771A5 (ja) | 2010-10-21 |
JP5325404B2 JP5325404B2 (ja) | 2013-10-23 |
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Application Number | Title | Priority Date | Filing Date |
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JP2007245809A Expired - Fee Related JP5325404B2 (ja) | 2007-09-21 | 2007-09-21 | Soi基板の作製方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7829434B2 (ja) |
JP (1) | JP5325404B2 (ja) |
KR (1) | KR101493301B1 (ja) |
CN (1) | CN101393860B (ja) |
TW (1) | TWI446413B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011135775A1 (ja) | 2010-04-26 | 2011-11-03 | 信越半導体株式会社 | イオン注入状況の確認方法および半導体ウェーハの製造方法 |
JP2015216313A (ja) * | 2014-05-13 | 2015-12-03 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
Families Citing this family (21)
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CN101657907B (zh) * | 2007-04-13 | 2012-12-26 | 株式会社半导体能源研究所 | 光伏器件及其制造方法 |
US7825007B2 (en) * | 2007-05-11 | 2010-11-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of joining a plurality of SOI substrates on a glass substrate by a heat treatment |
US7795111B2 (en) * | 2007-06-27 | 2010-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate and manufacturing method of semiconductor device |
WO2009001836A1 (en) * | 2007-06-28 | 2008-12-31 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US8431451B2 (en) | 2007-06-29 | 2013-04-30 | Semicondutor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
US8501585B2 (en) * | 2007-10-10 | 2013-08-06 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US8163628B2 (en) * | 2007-11-01 | 2012-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate |
JP5548351B2 (ja) * | 2007-11-01 | 2014-07-16 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
KR101127574B1 (ko) * | 2009-04-06 | 2012-03-23 | 삼성모바일디스플레이주식회사 | 액티브 매트릭스 기판의 제조방법 및 유기 발광 표시장치의 제조방법 |
WO2011058913A1 (en) | 2009-11-13 | 2011-05-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8735263B2 (en) | 2011-01-21 | 2014-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
US9653614B2 (en) * | 2012-01-23 | 2017-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US9024282B2 (en) | 2013-03-08 | 2015-05-05 | Varian Semiconductor Equipment Associates, Inc. | Techniques and apparatus for high rate hydrogen implantation and co-implantion |
US9881832B2 (en) * | 2015-03-17 | 2018-01-30 | Sunedison Semiconductor Limited (Uen201334164H) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
CN104979152A (zh) * | 2015-07-28 | 2015-10-14 | 中国科学技术大学 | 一种离子注入设备 |
WO2017091515A1 (en) | 2015-11-24 | 2017-06-01 | University Of Washington | Photosensitive medical tape |
US10985204B2 (en) * | 2016-02-16 | 2021-04-20 | G-Ray Switzerland Sa | Structures, systems and methods for electrical charge transport across bonded interfaces |
US9704820B1 (en) * | 2016-02-26 | 2017-07-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor manufacturing method and associated semiconductor manufacturing system |
JP6787268B2 (ja) * | 2017-07-20 | 2020-11-18 | 株式会社Sumco | 半導体エピタキシャルウェーハおよびその製造方法、ならびに固体撮像素子の製造方法 |
US11442039B2 (en) * | 2018-02-09 | 2022-09-13 | Hamamatsu Photonics K.K. | Sample support body, production method for sample support body, and sample ionization method |
WO2020264291A1 (en) | 2019-06-28 | 2020-12-30 | University Of Washington | Apparatus, system, and method for activating a low-adhesion state of thermal-sensitive tape |
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JP2006032920A (ja) * | 2004-06-14 | 2006-02-02 | Semiconductor Energy Lab Co Ltd | 半導体装置、及びそれらの作製方法 |
JP2006173577A (ja) * | 2004-10-29 | 2006-06-29 | Soi Tec Silicon On Insulator Technologies | 高い熱放散を伴う複合構造 |
JP2006196614A (ja) * | 2005-01-12 | 2006-07-27 | Canon Inc | 半導体基板の製造方法 |
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2007
- 2007-09-21 JP JP2007245809A patent/JP5325404B2/ja not_active Expired - Fee Related
-
2008
- 2008-09-15 US US12/210,304 patent/US7829434B2/en not_active Expired - Fee Related
- 2008-09-18 KR KR20080091426A patent/KR101493301B1/ko active IP Right Grant
- 2008-09-18 TW TW097135883A patent/TWI446413B/zh not_active IP Right Cessation
- 2008-09-18 CN CN2008101494944A patent/CN101393860B/zh not_active Expired - Fee Related
-
2010
- 2010-08-24 US US12/862,197 patent/US8043939B2/en not_active Expired - Fee Related
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JP2006032920A (ja) * | 2004-06-14 | 2006-02-02 | Semiconductor Energy Lab Co Ltd | 半導体装置、及びそれらの作製方法 |
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WO2011135775A1 (ja) | 2010-04-26 | 2011-11-03 | 信越半導体株式会社 | イオン注入状況の確認方法および半導体ウェーハの製造方法 |
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JP2015216313A (ja) * | 2014-05-13 | 2015-12-03 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101393860A (zh) | 2009-03-25 |
CN101393860B (zh) | 2013-10-30 |
KR101493301B1 (ko) | 2015-02-13 |
US8043939B2 (en) | 2011-10-25 |
JP5325404B2 (ja) | 2013-10-23 |
US7829434B2 (en) | 2010-11-09 |
TWI446413B (zh) | 2014-07-21 |
US20100317161A1 (en) | 2010-12-16 |
TW200937503A (en) | 2009-09-01 |
US20090081849A1 (en) | 2009-03-26 |
KR20090031258A (ko) | 2009-03-25 |
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