JP2009070865A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2009070865A
JP2009070865A JP2007234919A JP2007234919A JP2009070865A JP 2009070865 A JP2009070865 A JP 2009070865A JP 2007234919 A JP2007234919 A JP 2007234919A JP 2007234919 A JP2007234919 A JP 2007234919A JP 2009070865 A JP2009070865 A JP 2009070865A
Authority
JP
Japan
Prior art keywords
base material
semiconductor device
semiconductor chip
film substrate
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007234919A
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English (en)
Japanese (ja)
Other versions
JP2009070865A5 (https=
Inventor
Takeshi Sunaga
武史 須永
Taro Nishioka
太郎 西岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2007234919A priority Critical patent/JP2009070865A/ja
Publication of JP2009070865A publication Critical patent/JP2009070865A/ja
Publication of JP2009070865A5 publication Critical patent/JP2009070865A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts

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  • Wire Bonding (AREA)
JP2007234919A 2007-09-11 2007-09-11 半導体装置 Pending JP2009070865A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007234919A JP2009070865A (ja) 2007-09-11 2007-09-11 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007234919A JP2009070865A (ja) 2007-09-11 2007-09-11 半導体装置

Publications (2)

Publication Number Publication Date
JP2009070865A true JP2009070865A (ja) 2009-04-02
JP2009070865A5 JP2009070865A5 (https=) 2010-10-14

Family

ID=40606844

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007234919A Pending JP2009070865A (ja) 2007-09-11 2007-09-11 半導体装置

Country Status (1)

Country Link
JP (1) JP2009070865A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8236615B2 (en) 2009-11-25 2012-08-07 International Business Machines Corporation Passivation layer surface topography modifications for improved integrity in packaged assemblies
JP2015070047A (ja) * 2013-09-27 2015-04-13 京セラ株式会社 電子部品搭載用基板および電子装置
JP2020150117A (ja) * 2019-03-13 2020-09-17 株式会社リコー 電子装置、および電子装置の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001203229A (ja) * 2000-01-18 2001-07-27 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2006005302A (ja) * 2004-06-21 2006-01-05 Matsushita Electric Ind Co Ltd フレキシブル基板およびその製造方法
JP2006156869A (ja) * 2004-12-01 2006-06-15 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP2006302966A (ja) * 2005-04-15 2006-11-02 Sharp Corp 配線基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001203229A (ja) * 2000-01-18 2001-07-27 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2006005302A (ja) * 2004-06-21 2006-01-05 Matsushita Electric Ind Co Ltd フレキシブル基板およびその製造方法
JP2006156869A (ja) * 2004-12-01 2006-06-15 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP2006302966A (ja) * 2005-04-15 2006-11-02 Sharp Corp 配線基板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8236615B2 (en) 2009-11-25 2012-08-07 International Business Machines Corporation Passivation layer surface topography modifications for improved integrity in packaged assemblies
US8786059B2 (en) 2009-11-25 2014-07-22 International Business Machines Corporation Passivation layer surface topography modifications for improved integrity in packaged assemblies
JP2015070047A (ja) * 2013-09-27 2015-04-13 京セラ株式会社 電子部品搭載用基板および電子装置
JP2020150117A (ja) * 2019-03-13 2020-09-17 株式会社リコー 電子装置、および電子装置の製造方法

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