JP2009038372A - 多層キャパシタ構造及びこれの製造方法(方向に依存しない多層beolキャパシタ) - Google Patents
多層キャパシタ構造及びこれの製造方法(方向に依存しない多層beolキャパシタ) Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004020 conductor Substances 0.000 claims abstract description 184
- 239000003989 dielectric material Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 9
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims 2
- 238000010276 construction Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004964 aerogel Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
【解決手段】
基板上に設けられ、且つそれぞれが誘電体材料層に設けられた複数個の細長い導電体を有する複数の導電体坦持層であって、それぞれの導電体坦持層の複数個の細長い導電体のそれぞれが、誘電体材料層の正方形領域の辺に対して平行に延び且つ少なくとも1つの90度の曲がり部を有し、複数個の細長い導電体は、カソード端子に接続される第1組の細長い導電体及びアノード端子に接続される第2組の細長い導電体を含む複数の導電体坦持層と、複数の導電体坦持層相互間に設けられた高誘電率誘電体層とを備え、複数の導電体坦持層のうち基板に接して設けられている最下部の導電性坦持層にカソード端子に接続される第1組の細長い導電体のみが設けられている多層キャパシタ構造。
【選択図】図3
Description
24 貫通バイア
25 カソード端子
27 アノード端子
112−117 細長い導電体
124 貫通バイア
125 カソード端子
127 アノード端子
201−204 導電体坦持層
206,208,210 誘電材料層
212 基板
Claims (16)
- 基板上に設けられ、且つそれぞれが誘電材料に複数個の細長い導電体が設けられている複数の導電体坦持層であって、それぞれの導電体坦持層の前記複数個の細長い導電体のそれぞれが、前記誘電材料の正方形領域の辺に対して平行に延び且つ少なくとも1つの90度の曲がり部を有し、前記複数個の細長い導電体は、カソード端子に接続される第1組の細長い導電体及びアノード端子に接続される第2組の細長い導電体を含む前記複数の導電体坦持層と、
該複数の導電体坦持層相互間に設けられた高誘電率誘電材料層とを備え、
前記複数の導電体坦持層のうち前記基板に接して設けられている最下部の導電体坦持層に前記カソード端子に接続される第1組の細長い導電体のみが設けられている多層キャパシタ構造。 - 前記導電体坦持層の前記誘電材料は、低誘電率誘電材料である、請求項1に記載の多層キャパシタ構造。
- 前記細長い導電体は、1以上の金属若しくは金属含有合金からなる低抵抗導電性材料を使用して形成される、請求項1に記載の多層キャパシタ構造。
- 前記複数の導電体坦持層相互間は、前記高誘電率誘電材料層により分離されている、
請求項1に記載の多層キャパシタ構造。 - 前記高誘電率誘電材料層は、五二酸化タンタル及び窒化シリコンの少なくとも1つである、請求項4に記載の多層キャパシタ構造。
- 前記低誘電率誘電材料は、フッ素化ガラス、エーロゲル、ポリアリルエーテル系材料及びハイドロジェンシルセスキオキサンからなる群から選択される、請求項2に記載の多層キャパシタ構造。
- 前記低抵抗導電性材料は、アルミニウム及び銅の少なくとも1つである、請求項3に記載の多層キャパシタ構造。
- 前記低抵抗導電性材料の前記細長い導電体は、ダマシン後工程により設けられる、請求項8に記載の多層キャパシタ構造。
- それぞれが誘電材料に複数個の細長い導電体が設けられている複数個の細長い導電体を有する複数の導電体坦持層であって、それぞれの導電体坦持層の前記複数個の細長い導電体のそれぞれが、前記誘電材料層の正方形領域の辺に対して平行に延び且つ少なくとも1つの90度の曲がり部を有する前記複数の導電体坦持層相互間に高誘電率誘電材料層を設けた多層キャパシタ構造を基板上に形成するステップと、
前記複数個の細長い導電体は第1組の細長い導電体及び第2組の細長い導電体からなり、前記第1組の細長い導電体をカソード端子に接続し、前記第2組の細長い導電体をアノード端子に接続するステップとを含み、
前記複数の導電体坦持層のうち前記基板に接して設けられている最下部の導電体坦持層に前記カソード端子に接続される第1組の細長い導電体のみが設けられている、多層キャパシタ構造の製造方法。 - 前記導電体坦持層の前記誘電材料は、低誘電率誘電材料である、請求項9に記載の製造方法。
- 前記細長い導電体は、1以上の金属若しくは金属含有合金からなる低抵抗導電性材料を使用して形成される、請求項9に記載の製造方法。
- 前記複数の導電体坦持層相互間は、前記高誘電率誘電材料層により分離されている、
請求項9に記載の製造方法。 - 前記高誘電率誘電材料層は、五二酸化タンタル及び窒化シリコンの少なくとも1つである、請求項12に記載の製造方法。
- 前記低誘電率誘電材料は、フッ素化ガラス、エーロゲル、ポリアリルエーテル系材料及びハイドロジェンシルセスキオキサンからなる群から選択される、請求項10に記載の製造方法。
- 前記低抵抗導電性材料は、アルミニウム及び銅の少なくとも1つである、請求項11に記載の製造方法。
- 前記低抵抗導電性材料の前記細長い導電体は、ダマシン後工程により形成される、請求項15に記載の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/831,208 US7701037B2 (en) | 2007-07-31 | 2007-07-31 | Orientation-independent multi-layer BEOL capacitor |
US11/831208 | 2007-07-31 |
Publications (2)
Publication Number | Publication Date |
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JP2009038372A true JP2009038372A (ja) | 2009-02-19 |
JP5284708B2 JP5284708B2 (ja) | 2013-09-11 |
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JP2008189789A Expired - Fee Related JP5284708B2 (ja) | 2007-07-31 | 2008-07-23 | 多層キャパシタ構造及びこれの製造方法(方向に依存しない多層beolキャパシタ) |
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US (1) | US7701037B2 (ja) |
JP (1) | JP5284708B2 (ja) |
CN (1) | CN101359663B (ja) |
TW (1) | TW200912975A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014120615A (ja) * | 2012-12-17 | 2014-06-30 | Fujitsu Semiconductor Ltd | 容量素子、容量アレイおよびa/d変換器 |
JP2017076829A (ja) * | 2017-02-07 | 2017-04-20 | 株式会社ソシオネクスト | 容量素子、容量アレイおよびa/d変換器 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5540520B2 (ja) * | 2009-02-16 | 2014-07-02 | ソニー株式会社 | 容量素子、容量素子の設計方法および容量素子を含む集積回路装置 |
GB201003808D0 (en) * | 2010-03-08 | 2010-04-21 | Mantock Paul L | A high energy storage capacitor |
US8916919B2 (en) | 2011-06-23 | 2014-12-23 | International Business Machines Corporation | Interdigitated vertical native capacitor |
US8765595B2 (en) * | 2012-01-06 | 2014-07-01 | International Business Machines Corporation | Thick on-chip high-performance wiring structures |
US10643985B2 (en) | 2017-12-15 | 2020-05-05 | Qualcomm Incorporated | Capacitor array overlapped by on-chip inductor/transformer |
US10600731B2 (en) * | 2018-02-20 | 2020-03-24 | Qualcomm Incorporated | Folded metal-oxide-metal capacitor overlapped by on-chip inductor/transformer |
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JP2002124575A (ja) * | 2000-08-31 | 2002-04-26 | Texas Instr Inc <Ti> | チップ上のキャパシタ |
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2007
- 2007-07-31 US US11/831,208 patent/US7701037B2/en not_active Expired - Fee Related
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2008
- 2008-07-18 CN CN2008101377279A patent/CN101359663B/zh not_active Expired - Fee Related
- 2008-07-23 JP JP2008189789A patent/JP5284708B2/ja not_active Expired - Fee Related
- 2008-07-29 TW TW097128610A patent/TW200912975A/zh unknown
Patent Citations (4)
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JP2003530715A (ja) * | 2000-04-10 | 2003-10-14 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | ディープ・サブミクロンcmos用の交互に接続された同心ラインを備えた多層キャパシタ構造体 |
JP2002124575A (ja) * | 2000-08-31 | 2002-04-26 | Texas Instr Inc <Ti> | チップ上のキャパシタ |
JP2005197396A (ja) * | 2004-01-06 | 2005-07-21 | Renesas Technology Corp | 半導体装置 |
US20070126078A1 (en) * | 2005-12-07 | 2007-06-07 | Winbond Electronics Corp. | Interdigitized capacitor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2014120615A (ja) * | 2012-12-17 | 2014-06-30 | Fujitsu Semiconductor Ltd | 容量素子、容量アレイおよびa/d変換器 |
JP2017076829A (ja) * | 2017-02-07 | 2017-04-20 | 株式会社ソシオネクスト | 容量素子、容量アレイおよびa/d変換器 |
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Publication number | Publication date |
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CN101359663A (zh) | 2009-02-04 |
US7701037B2 (en) | 2010-04-20 |
JP5284708B2 (ja) | 2013-09-11 |
TW200912975A (en) | 2009-03-16 |
US20090032904A1 (en) | 2009-02-05 |
CN101359663B (zh) | 2010-12-01 |
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